PM8355 QuadPHY-II™ Advance 4-Channel 2.125, 2.5 and 3.125 Gbit/s Transceiver with Half-rate Support GENERAL DESCRIPTION SERIAL I/O TEST FEATURES The QuadPHY-II is a physical layer transceiver ideal for systems requiring high speed point-to-point communication links. It is applicable for PMAPMD connections in 10 GE, Infiniband 1 or 4 x 2.5 Gbit/s links, 1 and 2 Gbit/s Fibre Channel, as well as high speed serial backplanes for high capacity systems. • Redundant high speed serial I/O channels for convenient switching to redundant fabric. • High speed outputs with optional preemphasis to drive longer backplanes. • High speed I/O with on-chip termination resistors to directly drive dual-terminated 50 Ohm lines. • Extensive control of loopback, BIST, and operating modes via 802.3 compliant MDC/MDIO serial interface. • On-chip packet generator/checkerprovides at-speed diagnostics. • Built-in error counters per channel. • Support for IEEE 1149.1 JTAG testing on all pins. FEATURES PARALLEL I/O PHYSICAL • 10-bit Dual Data Rate (DDR) parallel interface. • Selectable source simultaneous or source synchronous transmit and receive parallel interfaces. • Convenient output clock for user friendly ASIC timing. • Interoperates with SSTL2 and 1.8V LVCMOS standard. • 1.8V, 0.18 micron standard CMOS technology with 2.5V tolerant I/O. • 289-ball PBGA (19mm x 19mm package). GENERAL • 10Gbit/s, bi-directional, XAUI to XGMII link supporting the proposed IEEE 802.3ae (the standard is draft and is subject to change). • Four independent 2.125, 2.5 and 3.125 Gbit/s Serdes for Fibre Channel, Infiniband, 10 GE line cards and highspeed backplane applications. • Half/Full rate mode selectable per channel. • Integrated serializer/ deserializer, clock synthesis, clock recovery and 8B/10B encode/decode logic. • Under 2 Watts typical power. TRUNKING &TIMING • Integrated Receive FIFO synchronizes incoming data to local clock domain. • Trunking feature de-skews and aligns all four channels to form a single 10 Gbit/s logical link. APPLICATIONS • • • • • • High speed serial backplanes 10 GE links Fibre Channel transceivers Infiniband transceivers XAUI retimers Intra-system interconnect BLOCK DIAGRAM Transmit Channel A (1 of 4) TXD[9:0] 2 TDOXP/ TDOXN TDOYP/ TDOYN (per channel) FIFO & /A/ insert 8B/10B Encoder Serializer 10 Adaptive Sampler (per channel) 9 or 10 2 TXCLK (shared) Receive Channel A (1 of 4) 10B/8B Decoder 8 or 10 FIFO & Trunking Logic RXD[9:0] (per channel) 9 or 10 RDIXP/ RDIXN RDIYP/ RDIYN RXCLK (per channel) 2 Clock Recovery Deserialize & Byte Align 2 (per channel) PMC-2000791 (A4) PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE SYSCLK (1x or 2x rate) REFCLK SYSCLK RATE RESET, MDC, MDIO Mode strapping pins JTAG interface BIST pins Clock Synthesizer PLL_LOCK Common Control Logic © Copyright PMC-Sierra, Inc. 2001 Advance PM8355 QuadPHY-II™ 4-Channel 2.125, 2.5 and 3.125 Gbit/s Transceiver with Half-rate Support EXAMPLE ARCHITECTURE interface to a working and protect fabric. The figure below shows a multi-service switching platform using QuadPHY-II devices for backplane interconnect and client signal physical interfaces. The 10GE line cards use the QuadPHYII as a PHY supporting XAUI on the line side and mating to a 10GE MAC using XGMII. As a serial backplane transceiver, the redundant high-speed links simplify the Infiniband and Fibre Channel line cards applications are also shown. The half- rate mode of the QuadPHY-II enables 1 and 2 Gbit/s support using the same device. The other applications shown are a XAUI retimer and an XGMII extender where the MAC and Optics module separated by longer distance. APPLICATION EXAMPLE - MULTI-SERVICE SWITCHING PLATFORM 1Gig Fibre Channel Link QuadPHY-II Upper Layer Functions MAC Optical Tranceiver XAUI XGMII Switch Fabric Device 1G / 2G Fibre Channel Card QuadPHY-II QuadPHY-II QuadPHY-II QuadPHY-II ASIC / FPGA FiberChannel MAC + Upper Layer Functions 10 GE 4x3.125 WDM WDM 10 Gigabit Ethernet LAN Line Card QuadPHY-II QuadPHY-II Optical Tranceiver 2 Gig Fibre Channel Link Custom ASIC Upper Layer Functions MAC Optical Tranceiver TBI • • • 10 Gigabit Ethernet LAN Line Card XGMII 4x2.5Gig Fibre Infiniband Line Card QuadPHY-II QuadPHY-II QuadPHY-II QuadPHY-II To order documentation, send email to: [email protected] or contact the head office, Attn: Document Coordinator Optical Tranceiver XAUI EXTENDER Infiniband ASIC Upper Layer Functions MAC XGMII Head Office: PMC-Sierra, Inc. #105 - 8555 Baxter Place Burnaby, B.C. V5A 4V7 Canada Tel: 604.415.6000 Fax: 604.415.6200 10 GE LAN XAUI Redundant Switch Fabric Device • • • QuadPHY-II ASIC or FPGA QuadPHY-II GMII/TBI XAUI Retimer QuadPHY-II QuadPHY-II QuadPHY-II Gigabit Ethernet Upper Layer Functions nxGE MACs QuadPHY-II Quad/ Octal PHYs QuadPHY-II Optical Xceivers XAUI XGMII Gigabit Ethernet Card Gigabit Ethernet • • • Custom ASIC TBI 2 Gig Fibre Channel Link • • • QuadPHY II 1Gig Fibre Channel Link FiberChannel MAC + Upper Layer Functions QuadPHY-II Quad/ Octal PHYs QuadPHY-II ASIC / FPGA Optical Tranceiver 10 GE 10Gig Serial LAN Serial 10 Gigabit Ethernet LAN Line Card QuadPHY-II • • • Switch Fabric Module 1G Fibre Channel Card All product documentation is available on our web site at: http://www.pmc-sierra.com For corporate information, send email to: [email protected] Optical Tranceiver 4 x 2.5Gig PMC-2000791 (A4) © Copyright PMC-Sierra, Inc. 2001. All rights reserved. S/UNI is a registered trademark of PMC-Sierra Inc. SPECTRA, CHESS and QuadPHY-II are trademarks of PMC-Sierra, Inc. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE