MAXIM DS4100H

Rev 0; 11/07
100MHz HCSL Clock Generator
The DS4100H is a low-jitter 100MHz clock generator
with a high-speed current steering logic (HCSL) output.
It combines an AT-cut crystal, an oscillator, and a lownoise phase-locked loop (PLL) in a 5mm by 3.2mm
ceramic package. Typical phase jitter is 0.9psRMS from
12kHz to 20MHz. The device operates from a single
+3.3V supply.
Applications
PCI Express®
Features
♦ 100MHz Output Frequency
♦ 3.3V ±5% Operating Voltage
♦ HCSL Output
♦ Phase Jitter (RMS): 0.9ps Typical
♦ ±39ppm Frequency Stability Over Voltage,
Temperature, 10 Years of Aging
♦ Output-Enable (OE) Control Input
♦ 5mm x 3.2mm x 1.49mm Ceramic Package (LCCC)
♦ Pb Free/RoHS Compliant
Ordering Information
PART
TEMP RANGE
PIN-PACKAGE
DS4100H+
-40°C to +85°C
10 LCCC
TOP
MARK
10H
+Denotes a lead-free package. The lead finish is JESD97
category e4 (Au over Ni) and is compatible with both lead-based
and lead-free soldering processes.
Pin Configuration
Typical Operating Circuit
TOP VIEW
OE
1
RREF
2
GND
3
6
VCC
5
OUTN
4
OUTP
RS
VCC
OUTP
DS4100H
RREF
PCI Express
LOAD OR
CONNECTOR
RS
OUTN
GND
475Ω
±1%
N.C.
+
3.3V
OE
N.C.
RT
DS4100H
*EP
RT
N.C.
N.C.
(5.00mm × 3.20mm × 1.49mm)
*EXPOSED PAD
PCI Express is a registered trademark of PCI-SIG Corp.
________________________________________________________________ Maxim Integrated Products
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
1
DS4100H
General Description
DS4100H
100MHz HCSL Clock Generator
ABSOLUTE MAXIMUM RATINGS
Power-Supply Voltage (VCC) .......................................-0.3V, +4V
Continuous Power Dissipation (TA = +70°C) ...................280mW
Operating Temperature Range ...........................-40°C to +85°C
Junction Temperature ......................................................+150°C
Storage Temperature Range ...............................-40°C to +85°C
Soldering Temperature Profile
(3 passes max) .......................................................Refer to the
IPC/JEDEC J-STD-020 specification.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VCC = 3.135V to 3.465V, TA = -40°C to +85°C. Typical values are at VCC = +3.3V and TA = +25°C, unless otherwise noted.)
PARAMETER
Supply Voltage
SYMBOL
CONDITIONS
MIN
TYP
MAX
3.135 3.300 3.465
UNITS
VCC
(Note 1)
V
Supply Current
ICC
OE = VIH, Figure 2
85
mA
Input High Voltage (OE)
VIH
(Note 1)
2.0
VCC
V
Input Low Voltage (OE)
VIL
(Note 1)
0
0.8
V
Input Leakage Current
(OE)
I IN
GND OE VCC
-55
+10
μA
HCSL OUTPUTS (OUTP, OUTN)
475 resistor connected between RREF and GND, VOUTN
or VOUTP = 1.2V, VCC = 3.3V ±5%
12.25 13.92 15.59
VOH
RS = 0, RT = 50 (Notes 1, 2)
612.5 696.0 779.5
mV
VOL
RS = 0, RT = 50 (Notes 1, 2)
0
50
mV
Output High Current
IOH
Output High Voltage
Output Low Voltage
mA
Output Leakage High
Current
I_LEAKH
VOE = 0; VOUTN, VOUTP = VCC
-10
+10
μA
Output Leakage Low
Current
I_LEAKL
VOE = 0; VOUTN, VOUTP = 0
-10
+10
μA
Measure current out of OUTN pin at V OUTN = 0.5V and 1.0V;
R O = 0.5 / I0.5 - I1.0
Output Resistance
RO
3000
Crossover Voltage
VCROSS
Output Rise Time
tR
20% to 80%, CL = 2pF
175
700
ps
Output Fall Time
tF
80% to 20%, CL = 2pF
175
700
ps
Measure crossing voltage at OUTP and OUTN
(Notes 1, 2, and 3)
(50% x
VOH) ±5%
mV
Overshoot
VOVER
Measure overshoot voltage at OUTP and OUTN
(Notes 1, 2, and 3)
VOH +
0.2V
V
Undershoot
VUNDER
Measure undershoot voltage at OUTP and OUTN
(Notes 1, 2, and 3)
-0.2
V
Output-Enable Time to
Low Level
t PZL
Figure 3 (Note 4)
200
ns
Output-Enable Time to
High Level
t PZH
Figure 3 (Note 5)
200
ns
2
_______________________________________________________________________________________
100MHz HCSL Clock Generator
(VCC = 3.135V to 3.465V, TA = -40°C to +85°C. Typical values are at VCC = +3.3V and TA = +25°C, unless otherwise noted.)
PARAMETER
SYMBOL
Output Disable Time
t PZ
CONDITIONS
MIN
TYP
Figure 3 (Note 6)
CLOCK OUTPUT AS MEASURED AT OUTP WITH RESPECT TO OUTN
Clock Output
f OUT
Frequency Stability
Total
f / f O
Over temperature range, aging, load, and supply (Note 7)
Initial Frequency
Tolerance
f_TOL
VCC = 3.3V, TA = +25°C
MAX
UNITS
10
ns
100
-39
MHz
+39
±15
ppm
ppm
Frequency Stability
vs. Temperature
f / fO | TA VCC = 3.3V
-30
+30
ppm
Frequency Stability
vs. VCC
f / f O | V VCC = 3.3V ±5%
-3
+3
ppm/V
Frequency Stability
vs. Load
f / f O
| LOAD
Aging (10 Years)
fAGING
Phase Jitter (RMS)
PJRMS
Accumulated
Deterministic Jitter Due
to Power-Supply Noise
(Note 8)
DJPN,P-P
Rise and Fall Time
Mismatching
Duty Cycle
tDC
Oscillation Startup Time
Clock Output SSB
Phase Noise
Note 1:
Note 2:
Note 3:
Note 4:
Note 5:
Note 6:
Note 7:
Note 8:
Note 9:
±10% variation in termination resistance
±1
-7
+7
12kHz to 20MHz
0.9
10kHz
3.0
100kHz
27
200kHz
15
1MHz
7.0
20% to 80%; CL = 2pF; Figure 2;
2 x (tR - tF) / (tR + tF)
±20
Measure at OUTP and OUTN, Figure 2
(Note 9)
ppm
45
ps
ps
%
55
3
100Hz
-90.0
1kHz
-112
10kHz
-115
100kHz
-123
1MHz
-142
10MHz
-147
ppm
%
ms
ps
All voltages are referenced to ground.
With 50Ω load to ground on each output pin.
Guaranteed by design and not production tested.
tPZL is defined as the time at which VOE = 1.0V on the rising edge of OE to the time at which VOUTP or VOUTN = 0.1VOH on
the falling edge of OUTP or OUTN.
tPZH is defined as the time at which the voltage on the rising edge of OE is equal to 1.0V to the time at which VOUTP or
VOUTN = 0.9VOH on the rising edge of VOUTP or VOUTN.
tPZ is defined as the time at which VOE = 1.0V on the falling edge of OE to the time at which both VOUTP and VOUTN are
less than 0.1VOH.
Frequency stability is calculated as: ΔfTOTAL = ΔfTEMP + ΔfVCC x 0.165 + ΔfLOAD + ΔfAGING.
Measured with 50mVP-P sinusoidal signal on the supply from 10kHz to 1MHz.
Including oscillator startup time and PLL acquisition time measured after VCC reaches 3.0V from power-on.
_______________________________________________________________________________________
3
DS4100H
ELECTRICAL CHARACTERISTICS (continued)
Typical Operating Characteristics
(VCC = +3.3V, TA = +25°C, unless otherwise noted.)
0
-5
-10
-20
0
20
40
60
80
0.5
0.3
0.0
-0.3
-0.5
-0.8
3.190
3.245
3.300
3.355
3.410
3.465
DS4100H toc03
DS4100H toc02
0.8
-1.0
3.135
-15
75.0
fOUT DEVIATION FROM VCC = 3.3V (ppm)
5
1.0
fOUT DEVIATION FROM VCC = 3.3V (ppm)
DS4100H toc01
10
-40
SUPPLY CURRENT vs. SUPPLY VOLTAGE
CLOCK OUTPUT vs. SUPPLY VOLTAGE
FREQUENCY vs. TEMPERATURE
15
fOUT DEVIATION (ppm)
DS4100H
100MHz HCSL Clock Generator
70.0
65.0
60.0
55.0
50.0
3.135
3.190
3.245
3.300
3.355
3.410
VCC (V)
VCC (V)
TEMPERATURE (°C)
VCC
COUNTER
N
DS4100H
OSCILLATOR
AMPLIFIER
PFD
LOOP
FILTER
OE
VCO
OUTPUT
BUFFER
COUNTER
M
OUTP
OUTN
RREF
CURRENT
ADJUST
GND
Figure 1. Functional Diagram
4
_______________________________________________________________________________________
3.465
100MHz HCSL Clock Generator
Z0
RS
DS4100H
OUTP
OUTP
CL
OUTPUT
BUFFER
Z0 = 50Ω, 35in LENGTH
RECEIVER
RS
OUTN
Z0
RT
RT
OUTN
CL
CL = 2pF
RT = 50Ω
RS = 0Ω FOR TEST, 0 TO 33Ω TO MINIMIZE RINGING IN APPLICATION.
CL = SIMULATES RECEIVER INPUT CAPACITANCE FOR TEST ONLY.
Figure 2. Typical Termination for HCSL Driver and Test Conditions
0.7 x VCC
OE
0.3 x VCC
tPZH
tPZ
OUTP
GND
tPZL
OUTN
GND
Figure 3. HCSL Output Timing Diagram When OE is Enabled and Disabled
Pin Description
PIN
NAME
FUNCTION
Output Enable. On-chip pullup resistor. If connected to logic-high or left open, the clock output is
enabled. If connected to logic-low, the output is three-stated.
1
OE
2
RREF
Connect a 475 ±1% resistor from RREF to ground.
3
GND
Ground
4
OUTP
Positive Clock Output. Requires a series resistor and a pulldown resistor.
5
OUTN
6
VCC
7–10
N.C.
—
EP
Negative Clock Output. Requires a series resistor and a pulldown resister.
+3.3V Supply Input. Device power can range from 3.135V to 3.465V.
No Connection
Exposed Paddle. The exposed pad must be used for thermal relief. This pad can be connected to
ground.
_______________________________________________________________________________________
5
DS4100H
100MHz HCSL Clock Generator
Detailed Description
The DS4100H is a low-jitter HCSL 100MHz clock generator. It combines an AT-cut crystal, an oscillator, and a
low-noise PLL in a 5mm by 3.2mm ceramic package.
The typical phase jitter is 0.9ps RMS from 12kHz to
20MHz. The device operates from a single +3.3V supply.
Chip Information
TRANSISTOR COUNT: 2850
SUBSTRATE CONNECTED TO GROUND
PROCESS: Bipolar SiGe
Thermal Information
PLL
The PLL generates a 1.6GHz high-speed clock signal
based on the 25MHz crystal oscillator output. Clockdivider circuit M generates the output clock by scaling
the VCO output frequency. Clock-divider circuit N
applies a scaled version of the output clock signal to
the phase/frequency detector (PFD) circuit.
Output Drivers
The DS4100H is available with HCSL output buffers.
When not needed, the output buffers can be disabled
by driving the OE input to a logic-low. OE has an internal pullup resistor so that, if OE is left open, the outputs
are enabled by default. When disabled, the output
buffer goes to a high-impedance state.
THETA-JA (°C/W)
90
Package Information
(For the latest package outline information go to
www.maxim-ic.com/DallasPackInfo.)
PACKAGE TYPE
DOCUMENT NO.
10 LCCC
56-G5032-002
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
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© 2007 Maxim Integrated Products
is a registered trademark of Maxim Integrated Products, Inc.