ETC REFERENCEMANUAL

AMENDMENT
Élan™SC400 Microcontroller
Register Set Reference Manual
Including Changes for the ÉlanSC410 Microcontroller
This document amends the Élan™SC400 Microcontroller Register Set Reference Manual, order #21032A, including
additional information for the ÉlanSC410 microcontroller. It consists of three parts:
■ “Documentation Defects and Corrections” lists documentation defects found in the original publication.
■ “Changes for the ÉlanSC410 Microcontroller” on page 25 gives an overview of differences between the
ÉlanSC400 microcontroller and the ÉlanSC410 microcontroller, and lists all the registers and bits not supported
on the ÉlanSC410 microcontroller.
■ The Index beginning on page 35 includes all of the registers listed in this document, with index offsets listed separately by subsystem.
DOCUMENTATION DEFECTS AND CORRECTIONS
Table 1 lists defects that have been found in the
Élan™SC400 Microcontroller Register Set Reference
Manual, order #21032A. Defects are listed in page order. Each entry lists the following:
the original and changed default values are shown for
the whole register. If other text is changed, the entry describes the affected part of the diagram and lists the
original and changed text.
■ page number
Each item description includes the register name, so
changes affecting a particular register can be found by
consulting the index in this document.
■ item to be corrected
■ original text
■ corrected text
■ comments explaining the change
Table entries that correct text in a diagram do not contain the entire diagram. If a default value is changed,
Unchanged portions of a paragraph are replaced by an
ellipsis (...) in entries where this might make the
change easier to find. The whole paragraph is included
if it is useful for understanding why the change was
made.
Table 1. Corrections to the Élan™SC400 Microcontroller Register Set Reference Manual
Page Item
Original Text
Change To
Comment
Title Page
Élan™SC400 Microcontroller
Register Set Reference Manual
Élan™SC400 and ÉlanSC410
Microcontrollers Register Set
Reference Manual
Add ÉlanSC410
microcontroller
to book title.
When set up for either BCD or 16-bit
binary count operation, the
maximum count for Channel 0 is
achieved by writing the internal
counting element associated with
this register to 0. See direct-mapped
register 43h for more detail.
Same change
for all three
pages. Notation
“0000h/d” is
misleading. Zero
value written
can be binary
(hex) or BCD
(decimal).
Chapter 2: PC/AT-Compatible Direct-Mapped Registers
2-36 Programmable Interval
Timer #1 Channel 0
Count Register, Address
0040h; last paragraph
2-37 Programmable Interval
Timer #1 Channel 1
Count Register, Address
0041h; last paragraph
When set up for either BCD or 16-bit
binary count operation, the
maximum count for Channel 0 is
achieved by writing the internal
counting element associated with
this register to 0000h/d. See directmapped register 43h for more detail.
2-38 Programmable Interval
Timer #1 Channel 2
Count Register, Address
0042h; last paragraph
This document contains information on a product under development at Advanced Micro Devices. The information
is intended to help you evaluate this product. AMD reserves the right to change or discontinue work on this product
without notice.
Publication# 21032 Rev: A Amendment/1
Issue Date: December 1997
A M E N D M E N T
Table 1.
Corrections to the Élan™SC400 Microcontroller Register Set Reference Manual (Continued)
Page Item
Original Text
2-49 PC/AT Keyboard
When CSC index C0h[0] is set, this
Mouse Interface Status bit is a PC/2 mouse-compatible
Register, Address
mouse output buffer full flay...
0064h; bit 5 description
2-52 RTC/CMOS RAM
Index Register,
Address 0070h;
diagram (bit 7 column)
RTC/CMOS RAM
Index Register,
Address 0070h; bit 7
description
RTC/CMOS RAM
Index Register,
Address 0070h;
Programming Notes
Change To
Comment
When CSC index C0h[0] is set, this
bit is a PS/2 mouse-compatible
mouse output buffer full flag...
Two corrections:
“PS/2 mouse”
and “flag.”
Reserved
NMI_GATE
–
0
W
7 Reserved
Reserved
During read/modify/
write operations,
software must
preserve this bit.
Programming Notes
7 NMI_GATE Master NMI Mask
1 = NMI events are
gated off from
reaching the core
The NMI_GATE
function has not
moved to CSC
index 9Dh[2] in
the ÉlanSC400
or ÉlanSC410
microcontrollers.
0 = NMI events will
propagate to the CPU
core
Programming Notes
Bit 7 of this register is the master NMI
gate control in a typical PC/AT
Compatible system. For various
reason, this bit has been made to
reside at CSC index 9Dh[2]...
(entire paragraph)
2-92 Master Software
DRQ(n) Request
Register, Address
00D2h; default bit
values in diagram
Master Software
DRQ(n) Request
Register, Address
00D2h; bits 1–0
description
00000000
xxxxxxxx
00=
Mask/unmask DMA Channel 0 0 =
4 mask per the REQDMA bit
01=
Mask/unmask DMA Channel
5 mask per the REQDMA bit 0 1 =
10=
Mask/unmask DMA Channel
6 mask per the REQDMA bit
11=
Mask/unmask DMA Channel 1 0 =
7 mask per the REQDMA bit
11=
2
“x” = nondeterministic.
Set/Reset DMA Channel 4
This field selects
internal DMA request per the the DMA
REQDMA bit
request channel
to assert or
Set/Reset DMA Channel 5
internal DMA request per the deassert,
depending on
REQDMA bit
the state of bit 2.
Set/Reset DMA Channel 6
internal DMA request per the
REQDMA bit
Set/Reset DMA Channel 7
internal DMA request per the
REQDMA bit
00000000
2-93 Master DMA Mask
Register Channels 4–7,
Address 00D4h; default
bit values in diagram
xxxxxxxx
“x” = nondeterministic.
2-94 Master DMA Mode
00000000
Register Channels 4–7,
Address 00D6h; default
bit values in diagram
xxxxxxxx
“x” = nondeterministic.
2-95 Master DMA Clear Byte 0 0 0 0 0 0 0 0
Pointer Register,
Address 00D8h; default
bit values in diagram
xxxxxxxx
“x” = nondeterministic.
Élan™SC400 Microcontroller Register Set Reference Manual Amendment
A M E N D M E N T
Table 1.
Corrections to the Élan™SC400 Microcontroller Register Set Reference Manual (Continued)
Page Item
Original Text
Change To
Comment
2-96 Master DMA Controller 0 0 0 0 0 0 0 0
Reset Register,
Address 00DAh; default
bit values in diagram
xxxxxxxx
“x” = nondeterministic.
2-97 Master DMA Controller 0 0 0 0 0 0 0 0
Temporary Register,
Address 00DAh; default
bit values in diagram
xxxxxxxx
“x” = nondeterministic.
2-98 Master DMA Reset
00000000
Mask Register, Address
00DCh; default bit
values in diagram
xxxxxxxx
“x” = nondeterministic.
2-103 Parallel Port 2 Status
2-104 Register, Address
0279h; default bit
values in diagram
?????xxx
“x” = nondeterministic.
Parallel Port 2 Status
Register, Address
0279h; Programming
Notes
————————
“?” = depends
on input state.
Programming Notes
Programming Notes
(entire note)
On power-up, the parallel port
defaults to PC/AT-Compatible mode.
Upon switching to EPP mode the bit
defaults change to ?????xx0b
————————
2-105 Parallel Port 2 Status
Register (EPP Mode),
Address 0279h; default
bit values in diagram
Parallel Port 2 Status
Register (EPP Mode),
Address 0279h;
Programming Notes
Programming Notes
?????xx0
Clarify behavior.
“x” = nondeterministic.
“?” = depends
on input state.
Programming Notes
Clarify behavior.
On power-up, the parallel port
defaults to PC/AT-Compatible mode.
Upon switching to EPP mode the bit
defaults change to ?????xx0b
Élan™SC400 Microcontroller Register Set Reference Manual Amendment
3
A M E N D M E N T
Table 1.
Corrections to the Élan™SC400 Microcontroller Register Set Reference Manual (Continued)
Page Item
Original Text
2-111 COM2 Baud Clock
00000000
Divisor Latch LSB,
Address 02F8h; default
bit values in diagram
COM2 Baud Clock
Divisor Latch LSB,
Address 02F8h;
Programming Notes
Programming Notes
2-112 COM2 Baud Clock
Divisor Latch MSB,
Address 02F9h;
Programming Notes
Change To
Comment
00000001
Divisor must be
nonzero.
Programming Notes
In order to determine the UART baud
rate that will result from a particular
setting of the baud rate divisor latch,
the 16x baud clock is divided by 16 to
give a normalized baud rate. Because
the standard 16x baud clock runs at
1.8432 MHz, the “normalized” baud
rate is 115200. This rate is then
divided by the value of the 16-bit baud
clock divisor latch register. It is invalid
to program a baud rate divisor of 0.
Add text to
programming
notes on both
pages.
The baud rate divisor latch, being a
16-bit value, provides for up to 64k–1
different baud rates (0 is not a valid
baud rate). However, only a few of the
available rates are ever used in
common practice. See the following
table for the commonly used baud
rates along with the baud rate divisor
required to achieve them:
Baud
2-114 COM2 Interrupt ID
Register, Address
02FAh; bits 7–6
description
2-121 COM2 Modem Status
Register, Address
02FEh; default bit
values in diagram
4
0 0 = No significance
0 1 = No significance
Divisor Latch Value
110
0417h
150
0300h
300
0180h
600
00C0h
1200
0060h
2400
0030h
4800
0018h
9600
000Ch
19200
0006h
38400
0003h
57600
0002h
115200
0001h
0 0 = 16450-Compatible mode is
enabled (default)
1 0 = 16450-compatible mode is
enabled
0 1 = No significance
1 1 = 16550-compatible mode is
enabled
1 1 = 16550-Compatible mode is
enabled
xxxx0000
????0000
1 0 = No significance
Élan™SC400 Microcontroller Register Set Reference Manual Amendment
Default of 0 0
indicates 16450Compatible
mode.
“?” = depends
on input state
A M E N D M E N T
Table 1.
Corrections to the Élan™SC400 Microcontroller Register Set Reference Manual (Continued)
Page Item
Original Text
Change To
Comment
2-124 Parallel Port 1 Status
2-125 Register, Address
0379h; default bit
values in diagram
————————
?????xxx
“x” = nondeterministic.
Parallel Port 1 Status
Register, Address
0379h; Programming
Notes
“?” = depends
on input state.
Programming Notes
Programming Notes
(entire note)
On power-up, the parallel port
defaults to PC/AT-Compatible mode.
Upon switching to EPP mode the bit
defaults change to ?????xx0b
2-126 Parallel Port 1 Status
————————
Register (EPP Mode),
Address 0379h; default
bit values in diagram
Parallel Port 1 Status
Register (EPP Mode),
Address 0379h;
Programming Notes
Programming Notes
?????xx0
Clarify behavior.
“x” = nondeterministic.
“?” = depends
on input state.
Programming Notes
Clarify behavior.
On power-up, the parallel port
defaults to PC/AT-Compatible mode.
Upon switching to EPP mode the bit
defaults change to ?????xx0b
Élan™SC400 Microcontroller Register Set Reference Manual Amendment
5
A M E N D M E N T
Table 1.
Corrections to the Élan™SC400 Microcontroller Register Set Reference Manual (Continued)
Page Item
Original Text
2-144 COM1 Baud Clock
00000000
Divisor Latch LSB,
Address 03F8h; default
bit values in diagram
COM1 Baud Clock
Divisor Latch LSB,
Address 03F8h;
Programming Notes
Programming Notes
2-145 COM1 Baud Clock
Divisor Latch MSB,
Address 03F9h;
Programming Notes
Change To
Comment
00000001
Divisor must be
nonzero
Programming Notes
In order to determine the UART baud
rate that will result from a particular
setting of the baud rate divisor latch,
the 16x baud clock is divided by 16 to
give a normalized baud rate. Because
the standard 16x baud clock runs at
1.8432 MHz, the “normalized” baud
rate is 115200. This rate is then
divided by the value of the 16-bit baud
clock divisor latch register. It is invalid
to program a baud rate divisor of 0.
Add text to
programming
notes on both
pages.
The baud rate divisor latch, being a
16-bit value, provides for up to 64k–1
different baud rates (0 is not a valid
baud rate). However, only a few of the
available rates are ever used in
common practice. See the following
table for the commonly used baud
rates along with the baud rate divisor
required to achieve them:
Baud
2-147 COM1 Interrupt ID
Register, Address
03FAh; default value
for bit 0 in diagram
0 0 = No significance
0 1 = No significance
Divisor Latch Value
110
0417h
150
0300h
300
0180h
600
00C0h
1200
0060h
2400
0030h
4800
0018h
9600
000Ch
19200
0006h
38400
0003h
57600
0002h
115200
0001h
0 0 = 16450-Compatible mode is
enabled (default)
1 0 = 16450-compatible mode is
enabled
0 1 = No significance
1 1 = 16550-compatible mode is
enabled
1 1 = 16550-Compatible mode is
enabled
1 0 = No significance
Default of 0 0
indicates 16450Compatible
mode.
2-150 COM1 Modem Control Enable COM2 Interrupts
Register, Address
03FCh; bit 3
description
Enable COM1 Interrupts
Correction.
2-153 COM1 Modem Status
Register, Address
03FEh; default bit
values in diagram
????0000
“?” = depends
on input state.
6
xxxx0000
Élan™SC400 Microcontroller Register Set Reference Manual Amendment
A M E N D M E N T
Table 1.
Corrections to the Élan™SC400 Microcontroller Register Set Reference Manual (Continued)
Page Item
Original Text
Change To
Comment
Programming Notes
Add note text.
Chapter 3: Chip Setup and Control (CSC) Indexed Registers
3-15 DRAM Control
Register, Index 04h;
Programming Notes
Programming Notes
The CAS precharge delay
(controlled by TCP, bit 3) always has
at least one added state (t) during
CPU write-back and copy-back
cycles. This is required due to the
amount of time it takes for CPU data
to be valid during subsequent cycles
of a burst. Furthermore, if the DRAM
width for the bank receiving the writeback or copy-back is 16 bits, the
added wait state occurs only
between DWORDs.
3-16 DRAM Refresh Control When the 32-KHz clock is used....
Register, Index 05h;
Thus, selecting the divide by 1 option
bits 1–0 description
results in a refresh interval of
15.6 ms. For the divide by 2, 4, and 8
selections, the refresh intervals are
31.2 ms, 62.5 ms, and 125 ms
respectively.
When the 32-KHz clock is used...
Change all times
Thus, selecting the divide by 1 option to microseconds
results in a refresh interval of
(µs).
15.6 µs. For the divide by 2, 4, and 8
selections, the refresh intervals are
31.2 µs, 62.5 µs, and 125 µs
respectively.
3-20 Non-Cacheable
Window 0 Address/
Attributes/SMM
Register, Index 11h;
default bit values in
diagram
00000000
x0000000
“x” = nondeterministic.
3-23 Cache and VL
Miscellaneous
Register, Index 14h;
bit 4 VL_RESET
description
Vesa Local Bus Reset
0 = VL_RESET deasserted
1 = VL_RESET asserted
Vesa Local Bus Reset
0 = VL_RST signal deasserted
1 = VL_RST signal asserted
Vesa local bus
reset signal
name is
VL_RST.
3-26 Linear ROMCS0/
Shadow Register,
Index 21h; default bit
values in diagram
x0000000
00000000
Bit 7 default is
zero.
3-31 ROMCS0 Configuration 00 = 0 wait states
Register B, Index 24h;
bits 4–3 description
Note: Bit 6 and
bits 4–1 are
reserved in the
ÉlanSC410
microcontroller.
00 = Reserved—Not Valid
Zero wait states
not supported
for Fast ROM.
000 = Reserved—Not Valid
Zero wait states
not supported
for Fast ROM.
These two bits can be read back to
determine the ROMCS1 data bus
width.
Delete reference
to pin strapping
(which applies to
ROMCS0 only).
Élan™SC400 Microcontroller Register Set Reference Manual Amendment
7
ROMCS0 Configuration 000 = 0 wait states
Register B, Index 24h;
bits 2–0 description
3-33 ROMCS1 Configuration These two bits can be read back to
Register A, Index 25h; determine the ROMCS1 data bus
bits 2–1 description
width which is set via pin strapping
options, and latched at power-on
reset.
A M E N D M E N T
Table 1.
Corrections to the Élan™SC400 Microcontroller Register Set Reference Manual (Continued)
Page Item
Original Text
Change To
Comment
00 = Reserved—Not Valid
Zero wait states
not supported
for Fast ROM.
000 = Reserved—Not Valid
Zero wait states
not supported
for Fast ROM.
3-36 ROMCS2 Configuration These two bits can be read back to
Register A, Index 27h; determine the ROMCS2 data bus
width which is set via pin strapping
bits 2–1 description
options, and latched at power-on
reset.
These two bits can be read back to
determine the ROMCS2 data bus
width.
Delete reference
to pin strapping
(which applies to
ROMCS0 only).
3-37 ROMCS2 Configuration 00 = 0 wait states
Register B, Index 28h;
bits 4–3 description
00 = Reserved—Not Valid
Zero wait states
not supported
for Fast ROM.
000 = Reserved—Not Valid
Zero wait states
not supported
for Fast ROM.
3-34 ROMCS1 Configuration 00 = 0 wait states
Register B, Index 26h;
bits 4–3 description
ROMCS1 Configuration 000 = 0 wait states
Register B, Index 26h;
bits 2–0 description
ROMCS2 Configuration 000 = 0 wait states
Register B, Index 28h;
bits 2–0 description
3-44 Pin Mux Register A,
Index 38h; diagram, (bit
5 column)
8
Reserved
Reserved
0
x
Correction.
R/W
Pin Mux Register A,
Index 38h; bit 5
description
Reserved
Reserved
Correct
During read/modify/write operations, omission.
software must preserve this bit.
Pin Mux Register A,
Index 38h; bits 2–1
descriptions
Select GPIO... or ISA PIRQx
Select GPIO... or PIRQx
0 = ...
0 = ...
1 = ISA signal is available...
1 = PIRQx signal...
Pin Mux Register A,
Index 38h;
Programming Notes
Programming Notes
Programming Notes
Clarify. Bit 0 is
Bit 0 of this register must be set in
not just for ISA
order to use most ISA I/O
DMA devices.
peripherals. This is because it
enables the AEN signal which,
although listed in the DMA signal
group, is generated by the DMA
controller for consumption by all
other ISA I/O devices which are not
part of the current DMA transfer.
These I/O devices should ignore I/O
cycles on the bus if AEN is active
because it means that fly-by DMA is
occurring, not an I/O cycle.
Élan™SC400 Microcontroller Register Set Reference Manual Amendment
“ISA PIRQ” is
misleading. The
PIRQ pins can
be assigned to
other interrupts.
A M E N D M E N T
Table 1.
Corrections to the Élan™SC400 Microcontroller Register Set Reference Manual (Continued)
Page Item
Original Text
Change To
Comment
3-53 PMU Present and Last Set this bit to immediately time out
Mode Register, Index
the current mode timer. This bit does
41h; bit 6 description
not need to be cleared and is not
read back. Software should not
invoke this feature for at least 15
microseconds after a wake-up from
Suspend mode. Software can read
the last mode from bits 5–3 of this
register and delay 15 microseconds
if the last mode was Suspend mode
before setting this bit.
Set this bit to force an immediate
time-out of the current mode timer,
causing the PMU to drop to the next
lower speed. This bit does not need to
be cleared and is not read back. This
function is designed for debugging
power management software.
Expand
description.
3-57 Wake-Up Pause/HighSpeed Clock Timers
Register, Index 45h;
bits 2–0 description
Selects the required delay from the
time a wake-up is sensed and the
PLLs are started up to allow the
power supplies to stabilize before the
microcontroller begins driving its
outputs or using its inputs. Read
returns the last value written.
3-59 Wake-Up Source
Enable Register A,
Index 52h; diagram, (bit
3 column)
Wake-Up Source
Enable Register A,
Index 52h; bit 3
description
Timer value to count down after a
wake up is sensed and the PLLs are
started up (if necessary) and the
GPIO_CSx signals are switched to
High-Speed (or Low-Speed) mode
levels (for those GPIO_CSx signals
that are programmed to change
based on PMU mode) to allow the
power supplies to stabilize before the
ÉlanSC400 microcontroller starts
driving its outputs or using its inputs.
Read returns the last value written.
Software should not invoke this
feature for at least one 32-KHz clock
cycle (30.5 µs) after a wake-up from
Suspend mode. Software can read
the last mode from bits 5–3 of this
register and delay 30.5 µs if the last
mode was Suspend mode before
setting this bit.
Reserved
Reserved
0
x
Increase delay.
Forced time-out
might be missed
(bit not latched)
if used too soon
after wake-up
from Suspend
mode.
Rewrite.
Remove
reference to
programmed
GPIO_CSx
signals. All chip
functions are
delayed.
Correction.
R/W
Reserved
Reserved
Correct
During read/modify/write operations, omission.
software must preserve this bit.
3-61 Wake-Up Source
Enable Register C,
Index 54h; diagram
(bits 7–6 columns)
PDRQ1_WAKE
PDRQ0_WAKE
RESERVED
RESERVED
0
0
x
x
R/W
R/W
Wake-Up Source
Enable Register C,
Index 54h; bit 7
description
PDRQ1_WAKE
Reserved
Programmable DMA Request 1
(PDRQ1) Wake-Up Control
Reserved
DMA requests
do not support
wake-ups.
DMA requests
do not support
wake-ups.
0 = Do not wake up system
1 = Wake up system
Wake-Up Source
Enable Register C,
Index 54h; bit 6
description
PDRQ0_WAKE
Reserved
Programmable DMA Request 0
(PDRQ0) Wake-Up Control
Reserved
DMA requests
do not support
wake-ups.
0 = Do not wake up system
1 = Wake up system
Élan™SC400 Microcontroller Register Set Reference Manual Amendment
9
A M E N D M E N T
Table 1.
Corrections to the Élan™SC400 Microcontroller Register Set Reference Manual (Continued)
Page Item
Original Text
3-63 Wake-Up Source
Status Register A,
Index 56h; diagram, (bit
3 column)
Wake-Up Source
Status Register A,
Index 56h; bit 3
description
3-65 Wake-Up Source
Status Register C,
Index 58h; diagram
(bits 7–6 columns)
Wake-Up Source
Status Register C,
Index 58h; bit 7
description
Change To
Reserved
Reserved
0
x
Comment
Correction.
R/W
Reserved
Reserved
Correct
During read/modify/write operations, omission.
software must preserve this bit.
PDRQ1_WOKE PDRQ0_WOKE
0
0
R/W
R/W
RESERVED
RESERVED
x
x
PDRQ1_WOKE
Reserved
Programmable DMA Request 1
(PDRQ1) Wake-Up Status
Reserved
DMA requests
do not support
wake-ups.
DMA requests
do not support
wake-ups.
Write to ‘0b to clear.
0 = Did not wake up system
1 = Awakened system
Wake-Up Source
Status Register C,
Index 58h; bit 6
description
PDRQ0_WOKE
Reserved
Programmable DMA Request 0
(PDRQ0) Wake-Up Status
Reserved
DMA requests
do not support
wake-ups.
Write to ‘0b’ to clear.
0 = Did not wake up system
1 = Awakened system
3-73 Activity Source Enable
Register C, Index 64h;
diagram (bit 6 column)
DRQ_IS_ACT
0
R/W
RESERVED
x
Activity Source Enable \
Register C, Index 64h;
space below diagram
Activity Source Enable DRQ_IS_ACT
Register C, Index 64h; DMA Request Will Be Activity
bit 6 description
0 = Not an activity
1 = Will be activity
DMA requests
do not support
activities.
Remove stray
backslash
character.
Reserved
DMA requests
do not support
activities.
3-74 Activity Source Enable INTREG_WAS_ACT
Register D, Index 65h;
diagram (bit 7)
INTREG_IS_ACT
Correction.
Activity Source Enable INTREG_WAS_ACT
Register D, Index 65h;
bit 7 description
INTREG_IS_ACT
Correction.
10
Reserved
Élan™SC400 Microcontroller Register Set Reference Manual Amendment
A M E N D M E N T
Table 1.
Corrections to the Élan™SC400 Microcontroller Register Set Reference Manual (Continued)
Page Item
Original Text
3-77 Activity Source Status
Register C, Index 68h;
diagram (bit 6 column)
Activity Source Status
Register C, Index 68h;
bit 6 description
Change To
DRQ_WAS_ACT
RESERVED
0
x
R/W
DRQ_WAS_ACT
Reserved
DMA Request Activity Status
Reserved
Write to ‘0b’ to clear.
Comment
DMA requests
do not support
activities.
DMA requests
do not support
activities.
0 = Not detected as activity
1 = Detected as activity
3-81 Activity Classification
Register C, Index 6Ch;
diagram (bit 6 column)
DRQ_SEC_ACT
RESERVED
0
x
R/W
Activity Classification
DRQ_SEC_ACT
Register C, Index 6Ch; DMA Request Activity Status
bit 6 description
0 = Primary activity
Reserved
Reserved
DMA requests
do not support
activities.
DMA requests
do not support
activities.
1 = Secondary activity
3-85 Battery/AC Pin
Configuration
Register B, Index 71h;
bit 0 description, last
paragraph
...to enter Suspend mode.8
...to enter Suspend mode.
Remove stray
character.
3-86 Battery/AC Pin State
Register, Index 72h;
bits 4–0 default values
in diagram
xxx00000
xxx?????
“x” = nondeterministic.
3-87 CPU Clock Speed
Register, Index 80h;
bit 0 description
1 = Clock tripled (99 MHz)
1 = Clock tripled (100 MHz)
The ÉlanSC400 microcontroller and
ÉlanSC410 microcontroller may
require special packaging to safely
support clock-tripled mode.
Selection of clock-tripled mode
results in much higher heat
generation by the device. Selecting
clock-tripled mode for an ÉlanSC400
microcontroller device which uses a
package that is not specifically
approved by AMD for use at clocktripled speed may result in erratic
system operation, loss of data, or
damage to the ÉlanSC400
microcontroller device.
Selection of clock-tripled mode
results in much higher heat
generation by the device.
ÉlanSC400 and ÉlanSC410
microcontroller devices that use the
292-pin BGA (Ball Grid Array)
package type can safely support
clock-tripled mode under AMDapproved operating conditions.
“?” = depends
on input state.
Correction.
Rewrite.
AMD may make the ÉlanSC400 and
ÉlanSC410 microcontroller devices
available in other package types that
are not approved by AMD for use at
clock-tripled speed. Selecting clocktripled mode for such devices may
result in erratic system operation,
loss of data, or damage to the
microcontroller device.
Élan™SC400 Microcontroller Register Set Reference Manual Amendment
11
A M E N D M E N T
Table 1.
Corrections to the Élan™SC400 Microcontroller Register Set Reference Manual (Continued)
Page Item
Original Text
Change To
Comment
3-88 CPU Clock Auto
Slowdown Register,
Index 81h; bit 4
description
The PMU modes or states provide a
way to trade off performance for
processing power in discrete steps. The
auto slowdown feature allows the
(average power/average performance)
to be fine tuned when the PMU is
operating in the highest available PMU
mode. This can be either be
Hyper-Speed mode or High-Speed
mode, depending on whether or not
Hyper-Speed mode is disabled.
Enabling this feature causes the CPU
clock to switch between the fast speed
and slow speed operating frequencies
as defined by the FAST_PERIOD and
SLOW_PERIOD bit fields.
The PMU modes or states provide a
way to trade off performance for
processing power in discrete steps. The
auto slowdown feature allows the
(average power/average performance)
to be fine tuned by allowing the PMU to
toggle between High-Speed and LowSpeed PMU modes with a duty cycle
which is user configurable via the
FAST_PERIOD and SLOW_PERIOD
bit fields in this register. The auto
slowdown feature must not be enabled
if Hyper-Speed mode is enabled, or
unexpected system operation may
occur.
Auto slowdown
is not supported
in Hyper-Speed
mode.
CPU Clock Auto
Slowdown Register,
Index 81h; bits 3–2
description
When Auto Slowdown is enabled, these
bits define how long the CPU clock runs
at the slow clock frequency before
switching up to run at the fast clock
frequency. When the Hyper-Speed PMU
mode is enabled, the slow clock
frequency will be the High-Speed mode
clock frequency. When the Hyper-Speed
PMU mode is disabled, the slow clock will
equal the Low-Speed mode clock
frequency. See the FAST_PERIOD field
for further explanation.
When Auto Slowdown is enabled, these
bits define how long the CPU clock runs
at the clock frequency that is currently
configured for Low-Speed PMU mode
before switching up to run at the clock
frequency that is currently configured for
High-Speed PMU mode. See the
FAST_PERIOD field for further
explanation.
Auto slowdown
is not supported
in Hyper-Speed
mode.
CPU Clock Auto
Slowdown Register,
Index 81h; bits 1–0
description
When Auto Slowdown is enabled,
these bits define how long the CPU
clock runs at the fast clock frequency
before switching down to run at the
slow clock frequency. When the
Hyper-Speed PMU mode is enabled,
the fast clock frequency will be the
Hyper-Speed mode clock frequency.
When the Hyper-Speed PMU mode
is disabled, the fast clock will equal
the High-Speed mode clock
frequency. See the SLOW_PERIOD
field for further explanation.
When Auto Slowdown is enabled,
these bits define how long the CPU
clock runs at the clock frequency that
is currently configured for HighSpeed PMU mode before switching
down to run at the clock frequency
that is currently configured for LowSpeed PMU mode. See the
SLOW_PERIOD field for further
explanation.
Auto slowdown
is not supported
in Hyper-Speed
mode.
x0100001
“x” = nondeterministic.
3-90 Clock Control Register, 0 0 1 0 0 0 0 1
Index 82h; default bit
values in diagram
Clock Control Register, R/W
Index 82h; diagram (bit
7 R/W status)
Bit 7 R/W status
is undefined.
3-91 CLK_IO Pin Output
Clock Select Register,
Index 83h; bits 3–0
description
CLI_IO Pin Select
CLK_IO Pin Select
...
...
0 0 0 0 = UART clock (18.432 MHz)
0 0 0 0 = UART clock (1.8431 MHz)
3-94 Miscellaneous SMI/
NMI Enable Register,
Index 90h; bit 2
description
Rising Edge on SUS_RES Pin XMI Falling Edge on SUS_RES Pin XMI Correction.
Enable
Enable
12
Élan™SC400 Microcontroller Register Set Reference Manual Amendment
Correct pin
name and UART
clock frequency.
A M E N D M E N T
Table 1.
Corrections to the Élan™SC400 Microcontroller Register Set Reference Manual (Continued)
Page Item
Original Text
Change To
Comment
3-94 Miscellaneous SMI/
NMI Enable Register,
Index 90h;
Programming Notes
Programming Notes
Programming Notes
Bits 6–2: If, when an XMI is
enabled... to XMI on a falling edge,
the SMI will occur immediately...
Bits 6–2: If, when an XMI is
enabled... to XMI on a falling edge,
the XMI will occur immediately...
1. Disable the SMI at its master
control.
1. Disable the XMI at its master
control.
Replace “SMI”
with “XMI” (three
places) and
replace “master
source” with
“master control”
(one place).
...
...
4. Re-enable the SMI at its master
source...
4. Re-enable the XMI at its master
control...
ACN_RISE_WAS_XMI
ACN_RISE_WILL_XMI
ACN_FALL_WAS_XMI
ACN_FALL_WILL_XMI
BL2_RISE_WAS_XMI
BL2_RISE_WILL_XMI
BL2_FALL_WAS_XMI
BL2_FALL_WILL_XMI
BL1_RISE_WAS_XMI
BL1_RISE_WILL_XMI
BL1_FALL_WAS_XMI
BL1_FALL_WILL_XMI
BL0_RISE_WAS_XMI
BL0_RISE_WILL_XMI
BL0_FALL_WAS_XMI
BL0_FALL_WILL_XMI
0 = Did not cause SMI/NMI
0 = Do not cause SMI/NMI
1 = Caused SMI/NMI
1 = Cause SMI/NMI
3-97 Battery Low and ACIN
SMI/NMI Enable
Register, Index 93h;
diagram and
description
(all bits)
Battery Low and ACIN
SMI/NMI Enable
Register, Index 93h;
description
(all bits)
Change “was” to
“will” in all bit
names.
This is an
enable register,
not a status
register.
Change state
definitions for all
bits.
This is an enable
register, not a
status register.
3-103 Battery Low and ACIN Re-enable the XMI at its master
control (CSC index 9Dh[2] for
SMI/NMI Status
NMIs...
Register, Index 97h;
Programming Notes,
step 4 (last paragraph)
Re-enable the XMI at its master
control (port 70h[7] for NMIs...
3-104 SMI/NMI Select
...Each of these can have individual
Register, Index 98h; bit enables. See the keyboard index
3 description
registers for more detail.
...Each of these can be individually Clarify.
enabled. See the PC Card and
Keyboard SMI/NMI Enable Register,
CSC Index 91h, for more detail.
Élan™SC400 Microcontroller Register Set Reference Manual Amendment
The NMI_GATE
function has not
moved to CSC
index 9Dh[2] in
the ÉlanSC400
or ÉlanSC410
microcontrollers.
13
A M E N D M E N T
Table 1.
Page Item
Corrections to the Élan™SC400 Microcontroller Register Set Reference Manual (Continued)
Original Text
3-105 I/O Access SMI Enable 1 = Cause an SMI due to....
Register A, Index 99h;
descriptions for
bits 4–0
I/O Access SMI Enable Programming Notes
Register A, Index 99h;
Programming Notes
Change To
1 = Cause an SMI due to.... Requires For all five bits,
special handling; see Programming add reference to
Notes section.
programming
notes.
Programming Notes
Special handling for SMI to emulate
I/O accesses:
If the system requires the use of
emulating and/or restarting I/O
accesses, then the software must
select the 80486 cache policy as
write through via CSC index 14h,
bit 0. Do not use the I/O Trap
address in SMBASE offset 0FF06h
to determine which I/O address to
emulate. Instead, to determine the
I/O address to emulate, the software
should examine the saved values of
the EIP and CS at SMBASE offsets
0FFF0h and 0FFACh, respectively.
The software then examines the
instruction that caused the SMI by
decrementing the EIP value,
determining the opcode, and using
the DX and AX registers in the SMM
save state or opcode operands to
determine the correct I/O address.
The I/O restart (writing 0FFh to
SMBASE offset 0FF00h) will work
correctly with the write through
policy.
14
Comment
Élan™SC400 Microcontroller Register Set Reference Manual Amendment
The ÉlanSC400
microcontroller
only supports
I/O trapping with
the write through
cache policy and
requires special
handling.
A M E N D M E N T
Table 1.
Corrections to the Élan™SC400 Microcontroller Register Set Reference Manual (Continued)
Page Item
Original Text
Change To
3-106 I/O Access SMI Enable 1 = Cause an SMI due to....
Register B, Index 9Ah;
descriptions for
bits 6–0
I/O Access SMI Enable Programming Notes
Register B, Index 9Ah;
Programming Notes
1 = Cause an SMI due to.... Requires For all seven
special handling; see Programming bits, add
Notes section.
reference to
programming
notes.
Programming Notes
Special handling for SMI to emulate
I/O accesses:
If the system requires the use of
emulating and/or restarting I/O
accesses, then the software must
select the 80486 cache policy as
write through via CSC index 14h,
bit 0. Do not use the I/O Trap
address in SMBASE offset 0FF06h
to determine which I/O address to
emulate. Instead, to determine the
I/O address to emulate, the software
should examine the saved values of
the EIP and CS at SMBASE offsets
0FFF0h and 0FFACh, respectively.
The software then examines the
instruction that caused the SMI by
decrementing the EIP value,
determining the opcode, and using
the DX and AX registers in the SMM
save state or opcode operands to
determine the correct I/O address.
The I/O restart (writing 0FFh to
SMBASE offset 0FF00h) will work
correctly with the write through
policy.
3-109 XMI Control Register,
Index 9Dh; diagram,
bits 7–3 and bit 2
functions
Reserved
NMI_GATE
Comment
The ÉlanSC400
microcontroller
only supports
I/O trapping with
the write through
cache policy and
requires special
handling.
Reserved
Add bit 2 to
Reserved field
bits 7–3. Delete
bit 2 description.
7–2 Reserved...
The NMI_GATE
function is
performed by
direct-mapped
Port 70h[7] in
the ÉlanSC400
and ÉlanSC410
microcontrollers.
3-116 GPIO Read-Back/Write x x x x x x x x
Register A–D, Index
A6h, A7h, A8h, A9h;
default bit values in
diagram
????????
“?” = depends
on input state.
3-122 GPIO_PMUB Mode
Change Register,
Index ABh; bit 4
description
Drive GPIO_PMUB Signal with
Correction.
Programmed Value in High-Speed
Mode
XMI Control Register,
Index 9Dh; bits 7–3
description
7–3 Reserved...
XMI Control Register,
Index 9Dh; bit 2
description
2 NMI_GATE Master NMI Enable...
(entire description)
Drive GPIO_PMUB Signal with
Programmed Value in HyperSpeed Mode
Élan™SC400 Microcontroller Register Set Reference Manual Amendment
15
A M E N D M E N T
Table 1.
Corrections to the Élan™SC400 Microcontroller Register Set Reference Manual (Continued)
Page Item
Original Text
Change To
3-124 GPIO_PMUC Mode
Change Register,
Index ACh; bit 4
description
Drive GPIO_PMUC Signal with
Programmed Value in HyperSpeed Mode
Drive GPIO_PMUC Signal with
Correction.
Programmed Value in High-Speed
Mode
3-126 GPIO_PMUD Mode
Change Register,
Index ADh; bit 4
description
Drive GPIO_PMUD Signal with
Programmed Value in HyperSpeed Mode
Drive GPIO_PMUD Signal with
Correction.
Programmed Value in High-Speed
Mode
3-130 GPIO_XMI to
GPIO_CS Map
Register, Index B0h;
bits 3–0 description,
step 1 of procedure
1. Disable XMIs to the CPU core...
For NMIs, this is done via CSC
index 9Dh[2].
1. Disable XMIs to the CPU core...
For NMIs, this is done via port
70h[7].
The NMI_GATE
function has not
moved to CSC
index 9Dh[2] in
the ÉlanSC400
or ÉlanSC410
microcontrollers.
R/W
Field is R/W.
3-135 GP_CSA I/O Address
Decode and Mask
Register, Index B5h;
diagram (bits 1–0 R/W
status)
Comment
3-137 GP_CSB I/O Address
Decode and Mask
Register, Index B7h;
diagram (bits 1–0)
CSB_SA0_MASK
CSB_ADDR[9–8]
Correction. Bit 2
name was
repeated in bits
1–0 field.
3-147 Keyboard
Configuration Register
A, Index C0h; bit 2
description
...
...
Addition.
1 = Disabled
1 = Disabled
3-150 Keyboard
Configuration Register
B, Index C1h; bit 1
description, fourth line
... transmit date, this bit...
3-164 Internal I/O Device
Disable/Echo Z-Bus
Configuration
Register, Index D0h;
bit 5 description
... During ECHO_ZBUS cycles, AEN ... During echoed cycles, AEN is also
asserted so that ISA I/O devices will
is also asserted so that ISA I/O
devices will not decode the
not decode the echoed cycles.
ECHO_ZBUS cycles.
Use more
meaningful
references to
internal I/O
cycles.
3-165 Internal I/O Device
Disable/Echo Z-Bus
Configuration
Register, Index D0h;
bit 2 description
DMA 0 Slave Controller Disable
DMA 0 Master Controller Disable
Correction.
1 = Internal PC Card controller...
1 = Internal PC Card controller...
Correction.
...If the last value written to port 3E0h
was greater than 80h, the write to
3E1h will generate an external bus
cycle.
...If the last value written to port 3E0h
was equal to or greater than 80h, the
write to 3E1h will generate an
external bus cycle.
Internal I/O Device
Disable/Echo Z-Bus
Configuration
Register, Index D0h;
bit 1 description
16
This bit may not be set if XT mode is
enabled via CSC register C1h[4].
... transmit data, this bit...
Élan™SC400 Microcontroller Register Set Reference Manual Amendment
Correction.
A M E N D M E N T
Table 1.
Corrections to the Élan™SC400 Microcontroller Register Set Reference Manual (Continued)
Page Item
Original Text
Change To
3-168 Parallel Port
Configuration
Register, Index D2h;
bits 1–0 description
0 0 = Set/reset DMA Channel 4 DMA 0 0 = Unidirectional mode
request per the REQDMA bit
(PC/AT compatible)
Comment
Correction.
0 1 = Set/reset DMA Channel 5 DMA 0 1 = EPP mode
request per the REQDMA bit
1 0 = Bidirectional mode
1 0 = Set/reset DMA Channel 6 DMA
(PS/2 compatible)
request per the REQDMA bit
11= Reserved
11= Set/reset DMA Channel 7 DMA
request per the REQDMA bit
3-169 UART FIFO Control
Shadow Register,
Index D3h; diagram
(bits 7–6 R/W status)
UART FIFO Control
Shadow Register,
Index D3h; diagram
(bits 5–4 and bit 3
function)
Reserved Reserved
UART FIFO Control
Shadow Register,
Index D3h; diagram
(bit 3 R/W status)
R
Reserved
Combine fields
for bits 5–3.
5–3 Reserved Reserved
During read/modify/
write operations,
software must
preserve these bits.
Reserved
Reserved
000
xxx
Combine
descriptions for
bits 5–3 and
correct.
Correction.
R/W
Interrupt Configuration Reserved
Register E, Index D8h;
bits 2–0 description
3-184 Suspend Pin State
Register A, Index E3h;
diagram, (bit 4 column)
Bits 7–6 R/W
status is R.
Bit 3 R/W status
is undefined.
UART FIFO Control
(entire description text)
Shadow Register,
Index D3h; bits 5–4 and
bit 3 descriptions
3-174 Interrupt Configuration
Register E, Index D8h;
diagram, (bits 2–0
column)
R
Reserved
Correct
During read/modify/write operations, omission.
software must preserve this bit.
Reserved
Reserved
0
x
Correction.
R/W
Suspend Pin State
Reserved
Register A, Index E3h;
bit 4 description
Reserved
Correct
During read/modify/write operations, omission.
software must preserve this bit.
Élan™SC400 Microcontroller Register Set Reference Manual Amendment
17
A M E N D M E N T
Table 1.
Corrections to the Élan™SC400 Microcontroller Register Set Reference Manual (Continued)
Page Item
Original Text
Change To
3-189 IrDA Control Register,
Index EAh; bit 0
description
0 = UART mode
0 = UART mode. When UART mode Rewrite.
is selected, the IrDA interface
and all associated control and
status bits have no meaning
except this bit. Serial data
transfer is via the SIN and SOUT
pins.
1 = IrDA mode
When UART mode is selected, the
IrDA interface and all associated
control and status bits have no
meaning except this bit. When IrDA
mode is selected and is operated in
Slow-Speed IrDA mode by clearing
this bit, use all of the normal 16550
UART control and status bits to
transmit and receive data over the
IrDA interface.
Comment
1 = IrDA mode. When IrDA mode is
selected, the IrDA interface is
enabled, and data transfer will
occur over the dedicated
SIROUT and SIRIN pins.
Note: Software can switch between
UART and IrDA modes at any time.
IrDA Control Register,
Index EAh;
Programming Notes
The use of either Low- or HighSpeed IrDA requires that the onboard UART be enabled by setting
CSC index D1h[0].
The use of either Slow- or HighSpeed IrDA requires that the onboard UART be enabled by setting
CSC index D1h[0].
Rewrite.
If CSC index EAh[3] = ‘0b,’ the
interrupt status bits in this register
are undefined. Thus, they cannot be
used for polled status unless the
High-Speed IrDA interrupt is
enabled. To use these bits in a
polled-only fashion, simply set CSC
index D8h[6–5] = ‘00b’ while CSC
index EAh[3] = ‘1b.’
3-192 IrDA CRC Status
Register, Index ECh;
default bit values in
diagram
18
x0000000
00000000
Élan™SC400 Microcontroller Register Set Reference Manual Amendment
Bit 7 default is
zero.
A M E N D M E N T
Table 1.
Page Item
Corrections to the Élan™SC400 Microcontroller Register Set Reference Manual (Continued)
Original Text
3-194 IrDA Frame Length
Bits 7–0 of the 11-bit IrDA Data
Register A, Index EEh; Frame Length Register. See CSC
bits 7–0 description
index EFh for bits 10–8. The 11-bit
value...
(entire description)
Change To
Comment
Bits 7–0 of the 12-bit IrDA Data
Frame Length Register. See CSC
index EFh for bits 11–8. The 12-bit
value written across these two
registers controls the length of a
transmitted IrDA data frame. This
12-bit internal register should be
programmed with the total number of
frame bytes (address, control, and
information fields) plus two for the
2-byte CRC/FCS field. The
programmed value must not include
the two required BOF bytes or the
STO flag byte.
Modify for frame
length of 12 bits
rather than 11.
Expand
description.
For example, consider a frame to be
transmitted that contains the
following bytes, which must be
written into the frame's (DRAMbased) DMA transmit buffer prior to
starting the transmit process.
Assuming that the DMA memory
address will increment after each
transfer (see the direct-mapped
DMA Mode Registers), the frame will
appear in the buffer as follows:
(lower addresses)
BOF/STA
ADDR
Control
Information
CRC/FCS
EOF/STO
=
=
=
=
=
=
2 bytes
1 byte
1 byte
19 bytes
2 bytes
1 byte
(higher addresses)
Total number of bytes in the transmit
buffer = 26
Subtracting three (for the two
required BOF bytes plus the one
required STO byte) from the total
results in 23d (17h). Thus, the value
of 17h should be programmed into
the 12-bit Frame Length Register via
CSC Index EEh–EFh.
Élan™SC400 Microcontroller Register Set Reference Manual Amendment
19
A M E N D M E N T
Table 1.
Corrections to the Élan™SC400 Microcontroller Register Set Reference Manual (Continued)
Page Item
Original Text
3-195 IrDA Frame Length
Bits 7–3: Reserved
Register B, Index EFh; Bits 2–0: FRAME_LEN[10–8]
bit names in diagram
Comment
Bits 7–4: Reserved
Bits 3–0: FRAME_LEN[11–8]
Modify for frame
length of 12 bits
rather than 11.
IrDA Frame Length
xxxxx000
Register B, Index EFh;
bit default values in
diagram
xxxx0000
IrDA Frame Length
Bits 7–3: Reserved
Register B, Index EFh; Bits 2–0: FRAME_LEN[10–8]
bit name text
Bits 7–4: Reserved
Bits 3–0: FRAME_LEN[11–8]
IrDA Frame Length
IrDA Data Frame Length... Bits 10–8
Register B, Index EFh; Bits 10–8 of the 11-bit IrDA Data
bit descriptions
Frame Length Register. See CSC
index EFh for bits 7–0. The 11-bit
value... the number programmed in
this 11-bit register will be data size
plus 3... the length of each of these
frames must conform to
FRAME_LEN10–FRAME_LEN0.
IrDA Data Frame Length... Bits 11–8 Modify for frame
length of 12 bits
Bits 11–8 of the 12-bit IrDA Data
rather than 11.
Frame Length Register. See CSC
3-201 ÉlanSC400
Microcontroller
Revision ID Register,
Index FFh; default bit
values in diagram
ÉlanSC400
Microcontroller
Revision ID Register,
Index FFh;
Programming notes
20
Change To
index EEh for bits 7–0. The 12-bit
value... the number programmed in
this 12-bit register will be data size
plus three... the length of each of
these frames must conform to
FRAME_LEN11–FRAME_LEN0.
Also index value
referred to
should be EEh,
not EFh.
00000000
————————
Default values
depend on the
microcontroller
version.
Programming Notes
Programming Notes
Addition.
The value read back depends on the The value read back depends on the
current major.minor versions of a
current major.minor versions of a
specific ÉlanSC400 microcontroller. specific ÉlanSC400 microcontroller.
Contact your AMD representative for
current version information.
Élan™SC400 Microcontroller Register Set Reference Manual Amendment
A M E N D M E N T
Table 1.
Corrections to the Élan™SC400 Microcontroller Register Set Reference Manual (Continued)
Page Item
Original Text
Change To
Comment
Chapter 4: RTC and CMOS RAM Indexed Registers
4-3
RTC/CMOS RAM
Index Register,
Address 0070h;
diagram (bit 7 column)
RTC/CMOS RAM
Index Register,
Address 0070h; bit 7
description
Reserved
NMI_GATE
–
0
W
7 Reserved
Reserved
7 NMI_GATE Master NMI Enable
1 = NMI events are
gated off from
reaching the core
The NMI_GATE
function has not
moved to CSC
index 9Dh[2] in
the ÉlanSC400
or ÉlanSC410
microcontrollers.
0 = NMI events will
propagate to the CPU
core
RTC/CMOS RAM
Index Register,
Address 0070h;
Programming Notes
Programming Notes
Programming Notes
Bit 7 of this register is the master NMI
gate control in a typical PC/AT
Compatible system. For various
reason, this bit has been made to
reside at CSC index 9Dh[2]...
(entire paragraph)
4-15 General Purpose
CMOS RAM, Indexes
0E–7Fh
—
4-16 Register A, Index 0Ah; This bit is provided for use by
bit 7 description
software that needs to modify the
time, calendar or alarm registers in
the real time clock. When this bit
reads back ‘1b’, these internal
registers are unavailable for access
by software since internal RTC logic
is using them. When this bit reads
back ‘0b’, software will have a
guaranteed minimum window of
244 µs in which modifications to
these registers are allowed...
—
Move section to
end of chapter.
This bit is provided for use by
software that needs to either read or
write the time, calendar, or alarm
registers in the real time clock. When
this bit reads back ‘1b’, these internal
registers are unavailable for access
by software because internal RTC
logic is using them. When this bit
reads back ‘0b’, software will have a
guaranteed minimum window of
244 µs in which reads or writes to
these registers are guaranteed to be
valid...
Rewrite to clarify
meaning.
0 1 0 = ...
Clarify.
The terms
“modify” and
“modifications”
are misleading.
Both reads and
writes are
affected.
The time, calendar, and alarm
information in RAM is fully available The time, calendar, and alarm
to the program when the UIP bit is 0, information in RAM is fully available
it is not in transition...
to the program when the UIP bit is 0
because an update cycle is not in
progress...
Register A, Index 0Ah; 0 1 0 = ...
bits 6–4 description
1 1 X = ...
1 1 X = ...
All other values = Programming
All other values = Programming
DV2-DV0 to any value except ‘010b’ DV2–DV0 to any value except ‘010b’
or ‘11Xb’ turns the oscillator off.
or ‘11Xb’ disables the input clock
from the oscillator circuit.
Élan™SC400 Microcontroller Register Set Reference Manual Amendment
21
A M E N D M E N T
Table 1.
Corrections to the Élan™SC400 Microcontroller Register Set Reference Manual (Continued)
Page Item
Original Text
Change To
Comment
Note: The following chapters in the register set manual apply only to the ÉlanSC400 microcontroller.
Chapter 5: Graphics Controller Indexed Registers
5-4
CGA/MDA Index
Register, Address
03x4h; diagram, R/W
designation
W
R/W
Register is read/
write.
5-5
CGA/MDA Data Port,
Address 03x5h;
diagram, R/W
designation
W
R/W
Register is read/
write.
5-7
Cursor End Register,
Index 0Ah; bits 7–5 in
diagram
CUR_END[4–0]
Reserved
Cursor End Register,
Index 0Ah; bits 4–0 in
diagram
Reserved
CUR_END[4–0]
Bit name
designators are
reversed in the
diagram.
5-18 Non-display Lines
Register, Index 34h;
bits 1–0 description
These bits allow 2 or 4 additional
non-display lines to be added...
These bits allow 1, 2, or 4 additional Correction.
non-display lines to be added...
5-20 Overflow Register,
Index 36h; bit 1
description
Vertical Display Enable End Bit 8
This is the eighth bit of the Vertical
Display Enable End Register. See
graphics index 37h for more detail.
Vertical Display End Bit 8
This is the eighth bit of the Vertical
Display End Register. See graphics
index 37h for more detail.
Correction.
Delete “Enable”
(two places).
5-21 Vertical Display End
Register, Index 37h;
bits 7–0 description
Determines the number of the last
character line to be output from the
frame buffer... Value = (number of
horizontal displayed character lines
from memory) - 1.
Determines the number of the last
character line to be output from the
frame buffer... Value = (number of
vertical displayed character lines
from memory) – 1.
Correction.
Formula is for
vertical lines.
5-22 Vertical Border End
Register, Index 38h;
bits 7–0 description
Determines the last character line to
be output to the panel at the bottom
of the display. Value = (number of
horizontal displayed character
lines) - 1...
Determines the last character line to Correction.
be output to the panel at the bottom Formula is for
of the display. Value = (number of
vertical lines.
vertical displayed character
lines) – 1...
5-36 Pixel Clock Control
Register, Index 4Ch;
bits 4–3 description
Divides the base dot clock (as
controlled by bits 2–0 above)...
Divides the base dot clock (as
controlled by bits 2–0)...
22
Élan™SC400 Microcontroller Register Set Reference Manual Amendment
Correction.
A M E N D M E N T
Table 1.
Corrections to the Élan™SC400 Microcontroller Register Set Reference Manual (Continued)
Page Item
Original Text
Change To
Comment
00??????
“x” = nondeterministic.
Chapter 6: PC Card Controller Indexed Registers
6-8
Interface Status
Register, Index 01h/
41h; default bit values
in diagram
00xxxxxx
Interface Status
Register, Index 01h/
41h; descriptions for
bits 5, 4, and 1–0
RDY_x pin
RDY_x pin
WP_x pin
WP_x pin
BVD2_x pin (2 places)
BVD2_x pin
BVD1_x pin (2 places)
BVD1_x pin
“?” = depends
on input state.
6-11 Interrupt and General 0 1 1 0 = IRQ6 enabled
Control Register, Index
03h/43h; bits 3–0
description, IRQ6
6-15 Address Window
(All text before table in programming
Enable Register, Index notes section.)
06h/46h;
Programming Notes
text
Address Window
Enable Register, Index
06h/46h;
Programming Notes
table, center column
6-56 Command Timing 0
Register, Index 3Bh;
default value for
bits 3–1 in diagram
These pins are
active high.
0 1 1 0 = IRQ6 enabled
Added for PC Card based floppy disk
drives that support PC/ATCompatible IRQs and DMA. An IRQ6
driven from the PCMCIA controller
will not cause any PMU events
(activity).
When the ÉlanSC400
Rewrite of
microcontroller is operating in
programming
Enhanced mode (see CSC index
notes text.
F1h[0], the five memory windows
that belong to PC Card Socket B
have the same meaning and controls
as they do on a standard 82356
controller. When operating in
Standard mode, PC Card controller
Socket B memory windows 1–5 are
redefined to be MMS Windows C–F.
In this mode, the MMS Windows
C–F base addresses and offsets are
configured using the same PC Card
controller registers that would have
been used if the windows were
configured to be PC Card windows.
However, the destination devices
(and other attributes that apply only
to MMS Windows) are now
controlled by CSC index 30h and
31h.
MMS Window
MMS Window
None
None
MMS 0
MMS C
MMS 1
MMS D
MMS 2
MMS E
MMS 3
MMS F
00001111
Clarification.
00000001
Élan™SC400 Microcontroller Register Set Reference Manual Amendment
Correction.
Correction.
23
A M E N D M E N T
Table 1.
Corrections to the Élan™SC400 Microcontroller Register Set Reference Manual (Continued)
Page Item
Original Text
Change To
Comment
6-59 Command Timing 1
Register, Index 3Eh;
default value for
bits 3–0 in diagram
00002222
00000010
Correction.
6-62 Command Timing 2
Register, Index 7Bh;
default value for
bits 3–0 in diagram
00003333
00000011
Correction.
24
Élan™SC400 Microcontroller Register Set Reference Manual Amendment
A M E N D M E N T
CHANGES FOR THE ÉlanSC410
MICROCONTROLLER
This section gives an overview of differences between
the ÉlanSC400 microcontroller and the ÉlanSC410 microcontroller.
TheÉlanSC410 microcontroller is identical to the
ÉlanSC400 microcontroller, except that the following
on-chip peripheral functions are not supported in the
ÉlanSC410 microcontroller:
■ PC Card Controller
■ LCD Graphics Controller
These functions are highlighted in grey in the block diagram shown in Figure 1 on the following page.
Table 2 on page 27 lists all affected register bit fields
and describes how those fields differ in the ÉlanSC410
microcontroller from the function described in the
Élan™SC400 Microcontroller Register Set Reference
Manual, order #21032A).
In general, register bits or bit field values that apply to
the PC Card controller or LCD Graphics controller are
reserved in the ÉlanSC410 microcontroller. The state
of reserved bits must be preserved by software during
read/modify/write operations.
Two PC Card controller register bits are shared by
MMS Windows C–F, which is supported by the
ÉlanSC410 microcontroller. Before MMS Windows
C–F can be configured, software must set CSC Index
bit D0h[1] = 1 and bit F1h[0] = 0.
Élan™SC400 Microcontroller Register Set Reference Manual Amendment
25
A M E N D M E N T
ÉlanSC400 or ÉlanSC410 Microcontroller
Addr
Data
Am486
CPU
Memory
Management
Unit
SA Bus
Address
Decoder
Addr
Dual DMA
Controllers
8237
Data
Steering
Power
GPIOs
Management
Unit
Clock I/O
32-KHz Crystal
Clock
Generation
LCD
Graphics
Controller
Real-Time
Clock
Graphics or
Internal
Bus
VL-Bus Controller
VL-Bus
Controller
Boundary
Scan
AT Port
Logic
System
Arbiter
Timer
8254
GPIOs
Dual Interrupt
Controllers
8259
Socket A Ctrl
GPIOs or
Parallel Port or
PC Card Socket B
Serial Port
Infrared
Data Bus
DRAM Control
Memory
Controller
PC Card
Controller
GPIOs
DRAM Control or
Keyboard Rows
GPIOs
Keyboard
Interface:
Matrix/XT/SCP
EPP
Parallel
Port
UART
16550
Infrared
Port
ROM Control
ISA Bus
Controller
GPIOs
GPIOs or
Keyboard Rows
Columns or
XT Keyboard
ISA Control or
Keyboard Rows
ISA Control
ISA Control or
GPIOs
Not supported in the ÉlanSC410 microcontroller.
Figure 1. Block Diagram—ÉlanSC400 and ÉlanSC410 Microcontrollers
26
Élan™SC400 Microcontroller Register Set Reference Manual Amendment
A M E N D M E N T
Register Set Differences
The following table lists changes to the register descriptions found in the Élan™SC400 Microcontroller
Register Set Reference Manual, order #21032A, that
are required for the ÉlanSC410 microcontroller. Because the PC Card controller and LCD graphics controller are not supported on the ÉlanSC410
microcontroller, most register bit fields that control
those functions are reserved. A few register bits are
shared between unsupported and supported functions.
These shared bit functions are also explained in the table.
Note:
The state of reserved register bits must be preserved
by software during read/modify/write operations.
Page numbers in the following table refer to the
Élan™SC400 Microcontroller Register Set Reference
Manual, order #21032A.
Table 2. Register Set Manual Differences for ÉlanSC410 Microcontroller
Register
I/O Address
Bits
Comment
Page
MDA/HGA Index Register
03B4h
7–0
Reserved on the ÉlanSC410 microcontroller
2-130
MDA/HGA Data Register
03B5
7–0
Reserved on the ÉlanSC410 microcontroller
2-131
MDA/HGA Mode Control
Register
03B8h
7–0
Reserved on the ÉlanSC410 microcontroller
2-132
MDA/HGA Status Register
03BAh
7–0
Reserved on the ÉlanSC410 microcontroller
2-133
HGA Configuration Register
03BFh
7–0
Reserved on the ÉlanSC410 microcontroller
2-134
CGA Index Register
03D4h
7–0
Reserved on the ÉlanSC410 microcontroller
2-135
CGA Data Port
03D5h
7–0
Reserved on the ÉlanSC410 microcontroller
2-136
CGA Mode Control Register
03D8h
7–0
Reserved on the ÉlanSC410 microcontroller
2-137
CGA Color Select Register
03D9h
7–0
Reserved on the ÉlanSC410 microcontroller
2-138
CGA Status Register
03DAh
7–0
Reserved on the ÉlanSC410 microcontroller
2-139
Primary 82365-Compatible
PC Card Controller Index
Register
03E0h
7–0
Reserved on the ÉlanSC410 microcontroller
2-140
Primary 82365-Compatible
PC Card Controller Data Port
03E1h
7–0
Reserved on the ÉlanSC410 microcontroller
2-141
Direct-Mapped Registers
Chip Setup and Control (CSC) Index Registers
Cache and VL Miscellaneous
Register
22h/23h
Index 14h
7
Reserved on the ÉlanSC410 microcontroller
3-23
Pin Strap Status Register
22h/23h
Index 20h
2
1 = Reserved on the ÉlanSC410 microcontroller
3-25
Linear ROMCS0/Shadow
Register
22h/23h
Index 21h
6
1 = Reserved on the ÉlanSC410 microcontroller
3-26
MMS Window C–F Attributes
Register
22h/23h
Index 30h
7–0
3-38
MMS Window C–F Device
Select Register
22h/23h
Index 31h
7–0
On the ÉlanSC410 microcontroller, the PC Card
functions referred to on these pages are not valid.
However, the Enable and Mode bits referred to are
shared by MMS Windows and must be configured as
described (CSC Index D0h[1] = 1 and F1h[0] = 0) to
enable the configuration of MMS Windows C–F.
3-39
Pin Mux Register B
22h/23h
Index 39h
6, 5
1 = Reserved on the ÉlanSC410 microcontroller
3-45
1, 0
0 1 = Reserved on the ÉlanSC410 microcontroller
22h/23h
Index 3Ah
0
Pin Mux Register C
1 = Reserved on the ÉlanSC410 microcontroller
Élan™SC400 Microcontroller Register Set Reference Manual Amendment
3-46
27
A M E N D M E N T
Table 2.
Register Set Manual Differences for ÉlanSC410 Microcontroller (Continued)
Register
I/O Address
Bits
Comment
Page
PMU Force Mode Register
22h/23h
Index 40h
5
Reserved on the ÉlanSC410 microcontroller
3-51
Wake-Up Source Enable
Register D
22h/23h
Index 55h
7–0
Reserved on the ÉlanSC410 microcontroller
3-62
Wake-Up Source Status
Register D
22h/23h
Index 59h
7–0
Reserved on the ÉlanSC410 microcontroller
3-66
Activity Source Enable
Register A
22h/23h
Index 62h
3–2
Reserved on the ÉlanSC410 microcontroller
3-71
Activity Source Enable
Register D
22h/23h
Index 65h
6–1
Reserved on the ÉlanSC410 microcontroller
3-74
Activity Source Status
Register A
22h/23h
Index 66h
3–2
Reserved on the ÉlanSC410 microcontroller
3-75
Activity Source Status
Register D
22h/23h
Index 69h
6–1
Reserved on the ÉlanSC410 microcontroller
3-78
Activity Classification
Register A
22h/23h
Index 6Ah
3–2
Reserved on the ÉlanSC410 microcontroller
3-79
Activity Classification
Register D
22h/23h
Index 6Dh
6–1
Reserved on the ÉlanSC410 microcontroller
3-82
CLK_IO Pin Output Clock
Select Register
22h/23h
Index 83h
3–0
0 0 1 0 = Reserved on the ÉlanSC410 microcontroller
3-91
PC Card and Keyboard SMI/
NMI Enable Register
22h/23h
Index 91h
3–0
Reserved on the ÉlanSC410 microcontroller
3-95
PC Card and Keyboard SMI/
NMI Status Register
22h/23h
Index 95h
3–0
Reserved on the ÉlanSC410 microcontroller
3-100
SMI/NMI Select Register
22h/23h
Index 98h
5
Reserved on the ÉlanSC410 microcontroller
3-104
I/O Access SMI Enable
Register A
22h/23h
Index 99h
3
Reserved on the ÉlanSC410 microcontroller
3-105
I/O Access SMI Enable
Register B
22h/23h
Index 9Ah
4, 3
Reserved on the ÉlanSC410 microcontroller
3-106
I/O Access SMI Status
Register A
22h/23h
Index 9Bh
3
Reserved on the ÉlanSC410 microcontroller
3-107
I/O Access SMI Status
Register B
22h/23h
Index 9Ch
4, 3
Reserved on the ÉlanSC410 microcontroller
3-108
Internal I/O Device Disable/
Echo Z-Bus Configuration
Register
22h/23h
Index D0h
1
This bit’s PC Card function is invalid on the ÉlanSC410
microcontroller. However, this bit is shared by MMS
Windows and must be set (= 1) to enable
MMS Windows C–F setup.
3-165
DMA Resource Channel Map
Register B
22h/23h
Index DCh
3–0
Reserved on the ÉlanSC410 microcontroller
3-178
Internal Graphics Control
Register A
22h/23h
Index DDh
7–0
Reserved on the ÉlanSC410 microcontroller
3-179
Internal Graphics Control
Register B
22h/23h
Index DEh
7–0
Reserved on the ÉlanSC410 microcontroller
3-180
Suspend Pin State Register A
22h/23h
Index E3h
7, 6
Reserved on the ÉlanSC410 microcontroller
3-184
28
Élan™SC400 Microcontroller Register Set Reference Manual Amendment
A M E N D M E N T
Table 2.
Register Set Manual Differences for ÉlanSC410 Microcontroller (Continued)
Register
I/O Address
Bits
Comment
Page
Suspend Mode Pin State
Override Register
22h/23h
Index E5h
7, 6
Reserved on the ÉlanSC410 microcontroller
3-186
PC Card Extended Features
Register
22h/23h
Index F0h
7–0
Reserved on the ÉlanSC410 microcontroller
3-196
PC Card Mode and DMA
Control Register
22h/23h
Index F1h
7–1
Reserved on the ÉlanSC410 microcontroller
3-198
PC Card Socket A/B Input
Pull-up Control Register
22h/23h
Index F2h
7–0
Reserved on the ÉlanSC410 microcontroller
3-200
0
This bit’s PC Card function is invalid on the ÉlanSC410
microcontroller. However, this bit is shared by MMS
Windows and must be cleared (= 0) to enable
MMS Windows C–F setup.
RTC Index Registers (No Changes)
Graphics Index Registers
Cursor Start Register
3x4h/3x5h
Index 0Ah
7–0
Reserved on the ÉlanSC410 microcontroller
5-6
Cursor End Register
3x4h/3x5h
Index 0Bh
7–0
Reserved on the ÉlanSC410 microcontroller
5-7
Start Address High Register
3x4h/3x5h
Index 0Ch
7–0
Reserved on the ÉlanSC410 microcontroller
5-8
Start Address Low Register
3x4h/3x5h
Index 0Dh
7–0
Reserved on the ÉlanSC410 microcontroller
5-9
Cursor Address High Register
3x4h/3x5h
Index 0Eh
7–0
Reserved on the ÉlanSC410 microcontroller
5-10
Cursor Address Low Register
3x4h/3x5h
Index 0Fh
7–0
Reserved on the ÉlanSC410 microcontroller
5-11
Light Pen High Register
(Read Only)
3x4h/3x5h
Index 10h
7–0
Reserved on the ÉlanSC410 microcontroller
5-12
Light Pen Low Register
(Read Only)
3x4h/3x5h
Index 11h
7–0
Reserved on the ÉlanSC410 microcontroller
5-13
Horizontal Total Register
3x4h/3x5h
Index 30h
7–0
Reserved on the ÉlanSC410 microcontroller
5-14
Horizontal Display End
Register
3x4h/3x5h
Index 31h
7–0
Reserved on the ÉlanSC410 microcontroller
5-15
Horizontal Line Pulse Start
Register
3x4/3x5
Index 32h
7–0
Reserved on the ÉlanSC410 microcontroller
5-16
Horizontal Border End
Register
3x4h/3x5h
Index 33h
7–0
Reserved on the ÉlanSC410 microcontroller
5-17
Non-display Lines Register
3x4h/3x5h
Index 34h
7–0
Reserved on the ÉlanSC410 microcontroller
5-18
Vertical Adjust Register
3x4h/3x5h
Index 35h
7–0
Reserved on the ÉlanSC410 microcontroller
5-19
Overflow Register
3x4h/3x5h
Index 36h
7–0
Reserved on the ÉlanSC410 microcontroller
5-20
Vertical Display End Register
3x4h/3x5h
Index 37h
7–0
Reserved on the ÉlanSC410 microcontroller
5-21
Élan™SC400 Microcontroller Register Set Reference Manual Amendment
29
A M E N D M E N T
Table 2.
Register Set Manual Differences for ÉlanSC410 Microcontroller (Continued)
Register
I/O Address
Bits
Comment
Page
Vertical Border End Register
3x4h/3x5h
Index 38h
7–0
Reserved on the ÉlanSC410 microcontroller
5-22
Frame Sync Delay Register
3x4h/3x5h
Index 39h
7–0
Reserved on the ÉlanSC410 microcontroller
5-23
Dual Scan Row Adjust
Register
3x4h/3x5h
Index 3Bh
7–0
Reserved on the ÉlanSC410 microcontroller
5-24
Dual Scan Offset Address
High Register
3x4h/3x5h
Index 3Ch
7–0
Reserved on the ÉlanSC410 microcontroller
5-25
Dual Scan Offset Address
Low Register
3x4h/3x5h
Index 3Dh
7–0
Reserved on the ÉlanSC410 microcontroller
5-26
Offset Register
3x4h/3x5h
Index 3Eh
7–0
Reserved on the ÉlanSC410 microcontroller
5-27
Underline Location Register
3x4h/3x5h
Index 3Fh
7–0
Reserved on the ÉlanSC410 microcontroller
5-28
Maximum Scan Line Register
3x4h/3x5h
Index 40h
7–0
Reserved on the ÉlanSC410 microcontroller
5-29
LCD Panel AC Modulation
Clock Control Register
3x4h/3x5h
Index 41h
7–0
Reserved on the ÉlanSC410 microcontroller
5-30
Font Table Register
3x4h/3x5h
Index 42h
7–0
Reserved on the ÉlanSC410 microcontroller
5-31
Graphics Controller
Grayscale Mode Register
3x4h/3x5h
Index 43h
7–0
Reserved on the ÉlanSC410 microcontroller
5-32
3x4h/3x5h
Index 44–4Bh
7–0
Reserved on the ÉlanSC410 microcontroller
5-34
Pixel Clock Control Register
3x4h/3x5h
Index 4Ch
7–0
Reserved on the ÉlanSC410 microcontroller
5-36
Frame Buffer Base Address
Register
3x4h/3x5h
Index 4Dh
7–0
Reserved on the ÉlanSC410 microcontroller
5-37
Font Buffer Base Address
High Byte Register
3x4h/3x5h
Index 4Eh
7–0
Reserved on the ÉlanSC410 microcontroller
5-38
Frame/Font Buffer Base
Address Register Low
3x4h/3x5h
Index 4Fh
7–0
Reserved on the ÉlanSC410 microcontroller
5-39
PMU Control Register 1
3x4h/3x5h
Index 50h
7–0
Reserved on the ÉlanSC410 microcontroller
5-40
PMU Control Register 2
3x4h/3x5h
Index 51h
7–0
Reserved on the ÉlanSC410 microcontroller
5-41
Extended Feature Control
Register
3x4h/3x5h
Index 52h
7–0
Reserved on the ÉlanSC410 microcontroller
5-42
Graphics Controller
Grayscale Remapping
Registers
PC Card Controller Indexed Registers
Identification and Revision
Register
3E0h/3E1h
Index 00, 40h
7–0
Reserved on the ÉlanSC410 microcontroller
6-7
Interface Status Register
3E0h/3E1h
Index 01, 41h
7–0
Reserved on the ÉlanSC410 microcontroller
6-8
Power and RESETDRV
Control Register
3E0h/3E1h
Index 02, 42h
7–0
Reserved on the ÉlanSC410 microcontroller
6-9
30
Élan™SC400 Microcontroller Register Set Reference Manual Amendment
A M E N D M E N T
Table 2.
Register Set Manual Differences for ÉlanSC410 Microcontroller (Continued)
Register
I/O Address
Bits
Comment
Page
Interrupt and General Control
Register
3E0h/3E1h
Index 03, 43h
7–0
Reserved on the ÉlanSC410 microcontroller
6-11
Card Status Change Register
3E0h/3E1h
Index 04, 44h
7–0
Reserved on the ÉlanSC410 microcontroller
6-12
Card Status Change Interrupt
Configuration Register
3E0h/3E1h
Index 05, 45h
7–0
Reserved on the ÉlanSC410 microcontroller
6-13
Address Window Enable
Register
3E0h/3E1h
Index 06, 46h
7–0
Reserved on the ÉlanSC410 microcontroller
6-15
I/O Window Control Register
3E0h/3E1h
Index 07, 47h
7–0
Reserved on the ÉlanSC410 microcontroller
6-16
I/O Window 0 Start Address
Low Register
3E0h/3E1h
Index 08h, 48h
7–0
Reserved on the ÉlanSC410 microcontroller
6-17
I/O Window 0 Start Address
High Register
3E0h/3E1h
Index 09h, 49h
7–0
Reserved on the ÉlanSC410 microcontroller
6-18
I/O Window 0 Stop Address
Low Register
3E0h/3E1h
Index 0Ah, 4Ah
7–0
Reserved on the ÉlanSC410 microcontroller
6-19
I/O Window 0 Stop Address
High Register
3E0h/3E1h
Index 0Bh, 4Bh
7–0
Reserved on the ÉlanSC410 microcontroller
6-20
I/O Window 1 Start Address
Low Register
3E0h/3E1h
Index 0Ch, 4Ch
7–0
Reserved on the ÉlanSC410 microcontroller
6-21
I/O Window 1 Start Address
High Register
3E0h/3E1h
Index 0Dh, 4Dh
7–0
Reserved on the ÉlanSC410 microcontroller
6-22
I/O Window 1 Stop Address
Low Register
3E0h/3E1h
Index 0Eh, 4Eh
7–0
Reserved on the ÉlanSC410 microcontroller
6-23
I/O Window 1 Stop Address
High Register
3E0h/3E1h
Index 0Fh, 4Fh
7–0
Reserved on the ÉlanSC410 microcontroller
6-24
Memory Window 0 Start
Address Low Register
3E0h/3E1h
Index 10h, 50h
7–0
Reserved on the ÉlanSC410 microcontroller
6-25
Memory Window 0 Start
Address High Register
3E0h/3E1h
Index 11h, 51h
7–0
Reserved on the ÉlanSC410 microcontroller
6-26
Memory Window 0 Stop
Address Low Register
3E0h/3E1h
Index 12h, 52h
7–0
Reserved on the ÉlanSC410 microcontroller
6-27
Memory Window 0 Stop
Address High Register
3E0h/3E1h
Index 13h, 53h
7–0
Reserved on the ÉlanSC410 microcontroller
6-28
Memory Window 0 Address
Offset Low Register
3E0h/3E1h
Index 14h, 54h
7–0
Reserved on the ÉlanSC410 microcontroller
6-29
Memory Window 0 Address
Offset High Register
3E0h/3E1h
Index 15h, 55h
7–0
Reserved on the ÉlanSC410 microcontroller
6-30
Memory Window 1 Start
Address Low Register
3E0h/3E1h
Index 18h, 58h
7–0
Reserved on the ÉlanSC410 microcontroller
6-31
Memory Window 1 Start
Address High Register
3E0h/3E1h
Index 19h, 59h
7–0
Reserved on the ÉlanSC410 microcontroller
6-32
Memory Window 1 Stop
Address Low Register
3E0h/3E1h
Index 1Ah, 5Ah
7–0
Reserved on the ÉlanSC410 microcontroller
6-33
Memory Window 1 Stop
Address High Register
3E0h/3E1h
Index 1Bh, 5Bh
7–0
Reserved on the ÉlanSC410 microcontroller
6-34
Élan™SC400 Microcontroller Register Set Reference Manual Amendment
31
A M E N D M E N T
Table 2.
Register Set Manual Differences for ÉlanSC410 Microcontroller (Continued)
Register
I/O Address
Bits
Comment
Page
Memory Window 1 Address
Offset Low Register
3E0h/3E1h
Index 1Ch, 5Ch
7–0
Reserved on the ÉlanSC410 microcontroller
6-35
Memory Window 1 Address
Offset High Register
3E0h/3E1h
Index 1Dh, 5Dh
7–0
Reserved on the ÉlanSC410 microcontroller
6-36
Memory Window 2 Start
Address Low Register
3E0h/3E1h
Index 20h, 60h
7–0
Reserved on the ÉlanSC410 microcontroller
6-37
Memory Window 2 Start
Address High Register
3E0h/3E1h
Index 21h, 61h
7–0
Reserved on the ÉlanSC410 microcontroller
6-38
Memory Window 2 Stop
Address Low Register
3E0h/3E1h
Index 22h, 62h
7–0
Reserved on the ÉlanSC410 microcontroller
6-39
Memory Window 2 Stop
Address High Register
3E0h/3E1h
Index 23h, 63h
7–0
Reserved on the ÉlanSC410 microcontroller
6-40
Memory Window 2 Address
Offset Low Register
3E0h/3E1h
Index 24h, 64h
7–0
Reserved on the ÉlanSC410 microcontroller
6-41
Memory Window 2 Address
Offset High Register
3E0h/3E1h
Index 25h, 65h
7–0
Reserved on the ÉlanSC410 microcontroller
6-42
Memory Window 3 Start
Address Low Register
3E0h/3E1h
Index 28h, 68h
7–0
Reserved on the ÉlanSC410 microcontroller
6-43
Memory Window 3 Start
Address High Register
3E0h/3E1h
Index 29h, 69h
7–0
Reserved on the ÉlanSC410 microcontroller
6-44
Memory Window 3 Stop
Address Low Register
3E0h/3E1h
Index 2Ah, 6Ah
7–0
Reserved on the ÉlanSC410 microcontroller
6-45
Memory Window 3 Stop
Address High Register
3E0h/3E1h
Index 2Bh, 6Bh
7–0
Reserved on the ÉlanSC410 microcontroller
6-46
Memory Window 3 Address
Offset Low Register
3E0h/3E1h
Index 2Ch, 6Ch
7–0
Reserved on the ÉlanSC410 microcontroller
6-47
Memory Window 3 Address
Offset High Register
3E0h/3E1h
Index 2Dh, 6Dh
7–0
Reserved on the ÉlanSC410 microcontroller
6-48
Memory Window 4 Start
Address Low Register
3E0h/3E1h
Index 30h, 70h
7–0
Reserved on the ÉlanSC410 microcontroller
6-49
Memory Window 4 Start
Address High Register
3E0h/3E1h
Index 31h, 71h
7–0
Reserved on the ÉlanSC410 microcontroller
6-50
Memory Window 4 Stop
Address Low Register
3E0h/3E1h
Index 32h, 72h
7–0
Reserved on the ÉlanSC410 microcontroller
6-51
Memory Window 4 Stop
Address High Register
3E0h/3E1h
Index 33h, 73h
7–0
Reserved on the ÉlanSC410 microcontroller
6-52
Memory Window 4 Address
Offset Low Register
3E0h/3E1h
Index 34h, 74h
7–0
Reserved on the ÉlanSC410 microcontroller
6-53
Memory Window 4 Address
Offset High Register
3E0h/3E1h
Index 35h, 75h
7–0
Reserved on the ÉlanSC410 microcontroller
6-54
Setup Timing 0 Register
3E0h/3E1h
Index 3Ah
7–0
Reserved on the ÉlanSC410 microcontroller
6-55
Command Timing 0 Register
3E0h/3E1h
Index 3Bh
7–0
Reserved on the ÉlanSC410 microcontroller
6-56
Recovery Timing 0 Register
3E0h/3E1h
Index 3Ch
7–0
Reserved on the ÉlanSC410 microcontroller
6-57
32
Élan™SC400 Microcontroller Register Set Reference Manual Amendment
A M E N D M E N T
Table 2.
Register Set Manual Differences for ÉlanSC410 Microcontroller (Continued)
Register
I/O Address
Bits
Comment
Page
Setup Timing 1 Register
3E0h/3E1h
Index 3Dh
7–0
Reserved on the ÉlanSC410 microcontroller
6-58
Command Timing 1 Register
3E0h/3E1h
Index 3Eh
7–0
Reserved on the ÉlanSC410 microcontroller
6-59
Recovery Timing 1 Register
3E0h/3E1h
Index 3Fh
7–0
Reserved on the ÉlanSC410 microcontroller
6-60
Setup Timing 2 Register
3E0h/3E1h
Index 7Ah
7–0
Reserved on the ÉlanSC410 microcontroller
6-61
Command Timing 2 Register
3E0h/3E1h
Index 7Bh
7–0
Reserved on the ÉlanSC410 microcontroller
6-62
Recovery Timing 2 Register
3E0h/3E1h
Index 7Ch
7–0
Reserved on the ÉlanSC410 microcontroller
6-63
Setup Timing 3 Register
3E0h/3E1h
Index 7Dh
7–0
Reserved on the ÉlanSC410 microcontroller
6-64
Command Timing 3 Register
3E0h/3E1h
Index 7Eh
7–0
Reserved on the ÉlanSC410 microcontroller
6-65
Recovery Timing 3 Register
3E0h/3E1h
Index 7Fh
7–0
Reserved on the ÉlanSC410 microcontroller
6-66
Élan™SC400 Microcontroller Register Set Reference Manual Amendment
33
A M E N D M E N T
34
Élan™SC400 Microcontroller Register Set Reference Manual Amendment
A M E N D M E N T
INDEX
A
Activity Classification Register A, 28
Activity Classification Register C, 11
Activity Classification Register D, 28
Activity Source Enable Register A, 28
Activity Source Enable Register C, 10
Activity Source Enable Register D, 10, 28
Activity Source Status Register A, 28
Activity Source Status Register C, 11
Activity Source Status Register D, 28
Address Window Enable Register, 23, 31
B
Battery Low and ACIN SMI/NMI Enable Register, 13
Battery Low and ACIN SMI/NMI Status Register, 13
Battery/AC Pin Configuration Register B, 11
Battery/AC Pin State Register, 11
Block diagram, 26
C
Cache and VL Miscellaneous Register, 7, 27
Card Status Change Interrupt Configuration Register,
31
Card Status Change Register, 31
CGA Color Select Register, 27
CGA Data Port, 27
CGA Index Register, 27
CGA Mode Control Register, 27
CGA Status Register, 27
CGA/MDA Data Port, 22
CGA/MDA Index Register, 22
Chip Setup and Control (CSC) Indexed Registers, 7,
27
CLK_IO Pin Output Clock Select Register, 12, 28
Clock Control Register, 12
COM1 Baud Clock Divisor Latch LSB, 6
COM1 Baud Clock Divisor Latch MSB, 6
COM1 Interrupt ID Register, 6
COM1 Modem Control Register, 6
COM1 Modem Status Register, 6
COM2 Baud Clock Divisor Latch LSB, 4
COM2 Baud Clock Divisor Latch MSB, 4
COM2 Interrupt ID Register, 4
COM2 Modem Status Register, 4
Command Timing 0 Register, 23, 32
Command Timing 1 Register, 24, 33
Command Timing 2 Register, 24, 33
Command Timing 3 Register, 33
CPU Clock Auto Slowdown Register, 12
CPU Clock Speed Register, 11
CSC Index 04h, 7
CSC Index 05h, 7
CSC Index 11h, 7
CSC Index 14h, 7, 27
CSC Index 20h, 27
CSC Index 21h, 7, 27
CSC Index 24h, 7
CSC Index 25h, 7
CSC Index 26h, 8
CSC Index 27h, 8
CSC Index 28h, 8
CSC Index 30h, 27
CSC Index 31h, 27
CSC Index 38h, 8
CSC Index 39h, 27
CSC Index 3Ah, 27
CSC Index 40h, 28
CSC Index 41h, 9
CSC Index 45h, 9
CSC Index 52h, 9
CSC Index 54h, 9
CSC Index 55h, 28
CSC Index 56h, 10
CSC Index 58h, 10
CSC Index 59h, 28
CSC Index 62h, 28
CSC Index 64h, 10
CSC Index 65h, 10, 28
CSC Index 66h, 28
CSC Index 68h, 11
CSC Index 69h, 28
CSC Index 6Ah, 28
CSC Index 6Ch, 11
CSC Index 6Dh, 28
CSC Index 71h, 11
CSC Index 72h, 11
CSC Index 80h, 11
CSC Index 81h, 12
CSC Index 82h, 12
CSC Index 83h, 12, 28
CSC Index 90h, 12, 13
CSC Index 91h, 28
CSC Index 93h, 13
CSC Index 95h, 28
CSC Index 97h, 13
CSC Index 98h, 13, 28
CSC Index 99h, 14, 28
CSC Index 9Ah, 15, 28
CSC Index 9Bh, 28
CSC Index 9Ch, 28
CSC Index 9Dh, 15
CSC Index A6h, 15
CSC Index A7h, 15
CSC Index A8h, 15
CSC Index A9h, 15
CSC Index ABh, 15
CSC Index ACh, 16
CSC Index ADh, 16
CSC Index B5h, 16
CSC Index B7h, 16
CSC Index BOh, 16
Élan™SC400 Microcontroller Register Set Reference Manual Amendment
35
A M E N D M E N T
CSC Index C0h, 16
CSC Index C1h, 16
CSC Index D0h, 16, 28
CSC Index D2h, 17
CSC Index D3h, 17
CSC Index D8h, 17
CSC Index DCh, 28
CSC Index DDh, 28
CSC Index DEh, 28
CSC Index E3h, 17, 28
CSC Index E5h, 29
CSC Index EAh, 18
CSC Index ECh, 18
CSC Index EEh, 19
CSC Index EFh, 20
CSC Index F0h, 29
CSC Index F1h, 29
CSC Index F2h, 29
CSC Index FFh, 20
Cursor Address High Register, 29
Cursor Address Low Register, 29
Cursor End Register, 22, 29
Cursor Start Register, 29
D
Direct-Mapped Register 0040h, 1
Direct-Mapped Register 0041h, 1
Direct-Mapped Register 0042h, 1
Direct-Mapped Register 0064h, 2
Direct-Mapped Register 0070h, 2, 21
Direct-Mapped Register 00D2h, 2
Direct-Mapped Register 00D4h, 2
Direct-Mapped Register 00D6h, 2
Direct-Mapped Register 00D8h, 2
Direct-Mapped Register 00DAh, 3
Direct-Mapped Register 00DCh, 3
Direct-Mapped Register 0279h, 3
Direct-Mapped Register 02F8h, 4
Direct-Mapped Register 02F9h, 4
Direct-Mapped Register 02FAh, 4
Direct-Mapped Register 02FEh, 4
Direct-Mapped Register 0379h, 5
Direct-Mapped Register 03B4h, 27
Direct-Mapped Register 03B5Ah, 27
Direct-Mapped Register 03B8h, 27
Direct-Mapped Register 03BAh, 27
Direct-Mapped Register 03BFh, 27
Direct-Mapped Register 03D4h, 27
Direct-Mapped Register 03D5h, 27
Direct-Mapped Register 03D8h, 27
Direct-Mapped Register 03D9h, 27
Direct-Mapped Register 03DAh, 27
Direct-Mapped Register 03E0h, 27
Direct-Mapped Register 03E1h, 27
Direct-Mapped Register 03F8h, 6
Direct-Mapped Register 03F9h, 6
Direct-Mapped Register 03FAh, 6
36
Direct-Mapped Register 03FCh, 6
Direct-Mapped Register 03FEh, 6
Direct-Mapped Register 03x4h, 22
Direct-Mapped Register 03x5h, 22
Direct-Mapped Registers, 1, 27
DMA Resource Channel Map Register B, 28
DRAM Control Register, 7
DRAM Refresh Control Register, 7
Dual Scan Offset Address High Register, 30
Dual Scan Offset Address Low Register, 30
Dual Scan Row Adjust Register, 30
E
ÉlanSC400 Microcontroller Revision ID Register, 20
Extended Feature Control Register, 30
F
Font Buffer Base Address High Byte Register, 30
Font Table Register, 30
Frame Buffer Base Address Register, 30
Frame Sync Delay Register, 30
Frame/Font Buffer Base Address Register Low, 30
G
General Purpose CMOS RAM, 21
GP_CSA I/O Address Decode and Mask Register, 16
GP_CSB Address Decode and Mask Register, 16
GPIO Read-Back/Write Register A–D, 15
GPIO_PMUB Mode Change Register, 15
GPIO_PMUC Mode Change Register, 16
GPIO_PMUD Mode Change Register, 16
GPIO_XMI to GPIO_CS Map, 16
Graphics Controller, 25
Graphics Controller Grayscale Mode Register, 30
Graphics Controller Grayscale Remapping Registers,
30
Graphics Controller Indexed Registers, 22, 29
Graphics Index 0Ah, 22, 29
Graphics Index 0Bh, 29
Graphics Index 0Ch, 29
Graphics Index 0Dh, 29
Graphics Index 0Eh, 29
Graphics Index 0Fh, 29
Graphics Index 10h, 29
Graphics Index 11h, 29
Graphics Index 30h, 29
Graphics Index 31h, 29
Graphics Index 32h, 29
Graphics Index 33h, 29
Graphics Index 34h, 22, 29
Graphics Index 35h, 29
Graphics Index 36h, 22, 29
Graphics Index 37h, 22, 29
Graphics Index 38h, 22, 30
Graphics Index 39h, 30
Graphics Index 3Bh, 30
Graphics Index 3Ch, 30
Graphics Index 3Dh, 30
Élan™SC400 Microcontroller Register Set Reference Manual Amendment
A M E N D M E N T
Graphics Index 3Eh, 30
Graphics Index 3Fh, 30
Graphics Index 40h, 30
Graphics Index 41h, 30
Graphics Index 42h, 30
Graphics Index 43h, 30
Graphics Index 44–4Bh, 30
Graphics Index 4Ch, 22, 30
Graphics Index 4Dh, 30
Graphics Index 4Eh, 30
Graphics Index 4Fh, 30
Graphics Index 50h, 30
Graphics Index 51h, 30
Graphics Index 52h, 30
H
HGA Configuration Register, 27
Horizontal Border End Register, 29
Horizontal Display End Register, 29
Horizontal Line Pulse Start Register, 29
Horizontal Total Register, 29
I
I/O Access SMI Enable Register A, 14, 28
I/O Access SMI Enable Register B, 15, 28
I/O Access SMI Status Register A, 28
I/O Access SMI Status Register B, 28
I/O Window 0 Start Address High Register, 31
I/O Window 0 Start Address Low Register, 31
I/O Window 0 Stop Address High Register, 31
I/O Window 0 Stop Address Low Register, 31
I/O Window 1 Start Address High Register, 31
I/O Window 1 Start Address Low Register, 31
I/O Window 1 Stop Address High Register, 31
I/O Window 1 Stop Address Low Register, 31
I/O Window Control Register, 31
Identification and Revision Register, 30
Interface Status Register, 23, 30
Internal Graphics Control Register A, 28
Internal Graphics Control Register B, 28
Internal I/O Device Disable/Echo Z-Bus Configuration
Register, 28
Internal I/O Device Disable/Internal Cycle Echo Configuration Register, 16
Interrupt and General Control Register, 23, 31
Interrupt Configuration Register E, 17
IrDA Control Register, 18
IrDA CRC Status Register, 18
IrDA Frame Length Register A, 19
IrDA Frame Length Register B, 20
K
Keyboard Configuration Register A, 16
Keyboard Configuration Register B, 16
L
LCD Graphics Controller. See Graphics Controller
LCD Panel AC Modulation Clock Register, 30
Light Pen High Register, 29
Light Pen Low Register, 29
Linear ROMCS0/Shadow Register, 7, 27
M
Master DMA Clear Byte Pointer Register, 2
Master DMA Controller Reset Register, 3
Master DMA Controller Temporary Register, 3
Master DMA Mask Register Channels 4–7, 2
Master DMA Mode Register Channels 4–7, 2
Master DMA Reset Mask Register, 3
Master Software DRQ(n) Request Register, 2
Maximum Scan Line Register, 30
MDA/HGA Data Register, 27
MDA/HGA Index Register, 27
MDA/HGA Mode Control Register, 27
MDA/HGA Status Register, 27
Memory Window 0 Address Offset High Register, 31
Memory Window 0 Address Offset Low Register, 31
Memory Window 0 Start Address High Register, 31
Memory Window 0 Start Address Low Register, 31
Memory Window 0 Stop Address High Register, 31
Memory Window 0 Stop Address Low Register, 31
Memory Window 1 Address Offset High Register, 32
Memory Window 1 Address Offset Low Register, 32
Memory Window 1 Start Address High Register, 31
Memory Window 1 Start Address Low Register, 31
Memory Window 1 Stop Address High Register, 31
Memory Window 1 Stop Address Low Register, 31
Memory Window 2 Address Offset High Register, 32
Memory Window 2 Address Offset Low Register, 32
Memory Window 2 Start Address High Register, 32
Memory Window 2 Start Address Low Register, 32
Memory Window 2 Stop Address High Register, 32
Memory Window 2 Stop Address Low Register, 32
Memory Window 3 Address Offset High Register, 32
Memory Window 3 Address Offset Low Register, 32
Memory Window 3 Start Address High Register, 32
Memory Window 3 Start Address Low Register, 32
Memory Window 3 Stop Address High Register, 32
Memory Window 3 Stop Address Low Register, 32
Memory Window 4 Address Offset High Register, 32
Memory Window 4 Address Offset Low Register, 32
Memory Window 4 Start Address High Register, 32
Memory Window 4 Start Address Low Register, 32
Memory Window 4 Stop Address High Register, 32
Memory Window 4 Stop Address Low Register, 32
Miscellaneous SMI/NMI Enable Register, 12, 13
MMS Window C–F Attributes Register, 27
MMS Window C–F Device Select Register, 27
MMS Window C–F setup, 27, 28, 29
Élan™SC400 Microcontroller Register Set Reference Manual Amendment
37
A M E N D M E N T
N
Non-Cacheable Window 0 Address/Attributes/SMM
Register, 7
Non-Display Lines Register, 22, 29
O
Offset Register, 30
Overflow Register, 22, 29
P
Parallel Port 1 Status Register, 5
Parallel Port 2 Status Register, 3
Parallel Port Configuration Register, 17
PC Card and Keyboard SMI/NMI Enable Register, 28
PC Card and Keyboard SMI/NMI Status Register, 28
PC Card Controller, 25
PC Card Controller Data Port, 27
PC Card Controller Index Register, 27
PC Card Controller Indexed Registers, 23, 30
PC Card Extended Features Register, 29
PC Card Index 00h/40h, 30
PC Card Index 01h/41h, 23, 30
PC Card Index 02h/42h, 30
PC Card Index 03h/43h, 23, 31
PC Card Index 04h/44h, 31
PC Card Index 05h/45h, 31
PC Card Index 06h/46h, 23, 31
PC Card Index 07h/47h, 31
PC Card Index 08h/48h, 31
PC Card Index 09h/49h, 31
PC Card Index 0Ah/4Ah, 31
PC Card Index 0Bh/4Bh, 31
PC Card Index 0Ch/4Ch, 31
PC Card Index 0Dh/4Dh, 31
PC Card Index 0Eh/4Eh, 31
PC Card Index 0Fh/4Fh, 31
PC Card Index 10h/50h, 31
PC Card Index 11h/51h, 31
PC Card Index 12h/52h, 31
PC Card Index 13h/53h, 31
PC Card Index 14h/54h, 31
PC Card Index 15h/55h, 31
PC Card Index 18h/58h, 31
PC Card Index 19h/59h, 31
PC Card Index 1Ah/5Ah, 31
PC Card Index 1Bh/5Bh, 31
PC Card Index 1Ch/5Ch, 32
PC Card Index 1Dh/5Dh, 32
PC Card Index 20h/60h, 32
PC Card Index 21h/61h, 32
PC Card Index 22h/62h, 32
PC Card Index 23h/63h, 32
PC Card Index 24h/64h, 32
PC Card Index 25h/65h, 32
PC Card Index 28h/68h, 32
PC Card Index 29h/69h, 32
PC Card Index 2Ah/6Ah, 32
38
PC Card Index 2Bh/6Bh, 32
PC Card Index 2Ch/6Ch, 32
PC Card Index 2Dh/6Dh, 32
PC Card Index 30h/70h, 32
PC Card Index 31h/71h, 32
PC Card Index 32h/72h, 32
PC Card Index 33h/73h, 32
PC Card Index 34h/74h, 32
PC Card Index 35h/75h, 32
PC Card Index 3Ah, 32
PC Card Index 3Bh, 23, 32
PC Card Index 3Ch, 32
PC Card Index 3Dh, 33
PC Card Index 3Eh, 24, 33
PC Card Index 3Fh, 33
PC Card Index 7Ah, 33
PC Card Index 7Bh, 24, 33
PC Card Index 7Ch, 33
PC Card Index 7Dh, 33
PC Card Index 7Eh, 33
PC Card Index 7Fh, 33
PC Card Mode and DMA Control Register, 29
PC Card Socket A/B Input Pull-up Control Register, 29
PC/AT Keyboard Mouse Interface Status Register, 2
Pin Mux Register A, 8
Pin Mux Register B, 27
Pin Mux Register C, 27
Pin Strap Status Register, 27
Pixel Clock Control Register, 22, 30
PMU Control Register 1, 30
PMU Control Register 2, 30
PMU Force Mode Register, 28
PMU Present and Last Mode Register, 9
Power and RESETDRV Control Register, 30
Primary 82365-Compatible PC Card Controller Data
Port, 27
Primary 82365-Compatible PC Card Controller Index
Register, 27
Programmable Interval Timer #1 Channel 0 Count
Register, 1
Programmable Interval Timer #1 Channel 1 Count
Register, 1
Programmable Interval Timer #1 Channel 2 Count
Register, 1
R
Recovery Timing 0 Register, 32
Recovery Timing 1 Register, 33
Recovery Timing 2 Register, 33
Recovery Timing 3 Register, 33
Register A, 21
ROMCS0 Configuration Register B, 7
ROMCS1 Configuration Register A, 7
ROMCS1 Configuration Register B, 8
ROMCS2 Configuration Register A, 8
ROMCS2 Configuration Register B, 8
RTC and CMOS RAM Indexed Registers, 21
Élan™SC400 Microcontroller Register Set Reference Manual Amendment
A M E N D M E N T
RTC Index 0Ah, 21
RTC Index 0E-7Fh, 21
RTC Index Registers, 29
RTC Register A, 21
RTC/CMOS RAM Index Register, 2, 21
S
Setup Timing 0 Register, 32
Setup Timing 1 Register, 33
Setup Timing 2 Register, 33
Setup Timing 3 Register, 33
SMI/NMI Select Register, 13, 28
Start Address High Register, 29
Start Address Low Register, 29
Suspend Mode Pin State Override Register, 29
Suspend Pin State Register A, 17, 28
U
UART FIFO Control Shadow Register, 17
Underline Location Register, 30
V
Vertical Adjust Register, 29
Vertical Border End Register, 22, 30
Vertical Display End Register, 22, 29
VL_RST signal, 7
W
Wake-Up Pause/High-Speed Clock Timers Register, 9
Wake-Up Source Enable Register A, 9
Wake-Up Source Enable Register C, 9
Wake-Up Source Enable Register D, 28
Wake-Up Source Status Register A, 10
Wake-Up Source Status Register C, 10
Wake-Up Source Status Register D, 28
X
XMI Control Register, 15
 1997 Advanced Micro Devices, Inc. All rights reserved.
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Product names used in this publication are for identification purposes and may be trademarks of their respective companies.
Élan™SC400 Microcontroller Register Set Reference Manual Amendment
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A M E N D M E N T
40
Élan™SC400 Microcontroller Register Set Reference Manual Amendment