Z9305/Z9309 3.3V 150 MHz Multi-Output Zero Delay Buffer Features • • • • • Zero input-output propagation delay Output-output skew less than 250 ps Device-device skew less than 700 ps One input drives nine outputs, grouped as 4/4/1 (Z9309) 10 MHz to 150 MHz operating range, compatible with CPU and PCI bus frequencies • Less than 200 ps cycle-cycle jitter, compatible with Pentium® and Pentium Pro®–based systems • Spread Spectrum Compatible • Test Mode to bypass PLL (Z9309) • Available in space-saving 16-pin 150-mil SOIC and TSSOP package (Z9309), and 8-pin 150-Mil SOIC package (Z9305) Block Diagram (Z9305) REF PLL CLKOUT CLK1 CLK2 CLK3 CLK4 Block Diagram (Z9309) PLL REF CLKOUT CLKA1 CLKA2 CLKA3 S2 S1 CLKA4 Select Input Decoding CLKB1 CLKB2 CLKB3 CLKB4 Cypress Semiconductor Corporation Document #: 38-07196 Rev. ** • 3901 North First Street • San Jose • CA 95134 • 408-943-2600 Revised December 5, 2001 Z9305/Z9309 The Z9309 has two banks of four outputs each, which can be controlled by the Select inputs as shown in the Table 1. If all output clocks are not required, Bank B can be tri-stated. The select inputs also allow the input clock to be directly applied to the output for chip and system testing purposes. The Z9305 and Z9309 PLLs enter a Power Down mode when there are no rising edges on the REF input. In this state, the outputs are tri-stated and the PLL is turned off, resulting in less than 50 uA of current draw. The Z9309 PLL shuts down in one additional case as shown in Table 1. All outputs have less than 200 ps of cycle-cycle jitter. The input to output propagation delay is guaranteed to be less than 350 ps, and the output to output skew is guaranteed to be less than 250 ps. Connection Diagram REF LKA1 LKA2 VDD GND LKB1 LKB2 S2 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 CLKOUT CLKA4 CLKA3 VDD GND CLKB4 CLKB3 S1 REF CLK2 CLK1 GND 1 2 3 4 Z9305 The Z9309 is a low cost 3.3V zero delay buffer designed to distribute high speed clocks in PC system devices and SDRAM modules and is available in a 16-pin SOIC or TSSOP package. The Z9305 is an 8-pin version of the Z9309 and it accepts one reference input and drives out five low skew clocks. The devices have an on-chip PLL which locks to an input clock on the REF pin. The PLL feedback is on-chip and is obtained from the CLKOUT pad. Multiple Z9305 and Z9309 devices can accept the same input clock and distribute it. In this case, the skew between the outputs of two devices is guaranteed to be less than 700 ps. Z9309 Product Description 8 7 6 5 CLKOU CLK4 VDD CLK3 Pin Description (Z9305) PIN No. 1 2 3 4 5 6 7 8 Pin Name REF[1] CLK2[1] CLK1[1] GND CLK3[1] VDD CLK4[1] CLKOUT[1] I/O I O O I O O O Description Input reference frequency, 5.0 V tolerant input Buffered clock output Buffered clock output Ground Buffered clock output 3.3V supply Buffered clock output Buffered clock output, internal feedback on this pin Pin Description (9309) PIN No. Pin Name I/O Description 1 REF[1] 2 3 CLKA2 4 VDD 5 GND I Ground 6 CLKB1[1] O Clock output, bank B 7 CLKB2[1] O Clock output, bank B I Select input pin, bit 2 8 I Input reference frequency, 5.0 V tolerant input CLKA1[1] O Clock output, bank A [1] O Clock output, bank A I 3.3V supply [2] S2 [2] 9 S1 I Select input pin, bit 1 10 CLKB3[1] O Clock output, bank B 11 CLKB4[1] O 12 GND Clock output, bank B Ground 3.3V supply 13 VDD 14 CLKA3[1] O Clock output, bank A 15 CLKA4[1] O Clock output, bank A 16 CLKOUT[1] O Buffered output, internal feedback on this pin. Notes: 1. Includes weak pull-down. 2. Includes weak pull-up. Document #: 38-07196 Rev. ** Page 2 of 7 Z9305/Z9309 Z9309 Select Input Functionality S2 S1 CLKA1-A4 CLKB1-B4 CLK-OUT[3] Output Source PLL Shut-down 0 0 3-state 3-state Driven PLL N 0 1 Driven 3-state Driven PLL N 1 0 Driven Driven Driven REF Y 1 1 Driven Driven Driven PLL N Ref - Input to CLKA/CLKB Delay (ps) 1500 1000 500 0 -30 -25 -20 -15 -10 -5 0 5 10 15 20 25 30 -500 -1000 -1500 Output Load Difference: CLKOUT Load - CLKA/CLKB Load (PF) REF, Input T0 CLKA/CLKB Delay versus Loading Difference Between CLKOUT and CLKA/CLKB Pins Zero Delay and Skew Control All outputs should be uniformly loaded to achieve sero delay between input and output. Since the CLKOUT pin is the internal feedback to the PLL, its relative loading can adjust the input-output delay. This is shown in the above graph. For applications requiring zero I/O delay, all outputs including CLKOUT must be equally loaded. Even if CLKOUT is not used, it must have a load capacity equal to that of other outputs. If input-to-output delay adjustments are required, use the above graph to calculate loading differences between the CLKOUT pin and other outputs. For zero output-output skew, be sure to load all outputs equally. Note: 3. This output is driven and has an internal feedback for the PLL. The load on this output can be adjusted to change the skew between the reference and outputs. Document #: 38-07196 Rev. ** Page 3 of 7 Z9305/Z9309 Maximum Ratings Voltage Relative to VSS .................................................–0.3V Voltage Relative to VDD ..................................................0.3V Storage Temperature ................................. –65°C to + 150°C Operating Temperature ................................. –40°C to +85°C Maximum Power Supply ....................................................7V This device contains circuitry to protect input against damage from high static voltages or electric fields. Precautions should be taken, however, to avoid applications to this circuit of any voltage higher than the maximum rated voltages. For proper operation, VIN and VOUT should be constrained to the range: VSS < (VIN or VOUT) < VDD . Unused inputs must always be tied to an appropriate logic voltage level (either VSS or VDD). Reference Input Voltage ........................................–0.5 to 7V DC Electrical Characteristics (Z9305/Z9309) (VDD = 3.0 – 3.6V, TA = –40°C to 85°C) Parameter Description Test Conditions Min. Typ. Max. Units – – 0.8 Vdc 2.0 – VIL Input LOW Voltage4 VIH Input HIGH Voltage4 – IIL Input LOW Current VIN = 0V 50.0 µA IIH Input HIGH Current VIN = VDD ±100 µA VOL Output LOW Voltage5 IOL = 8 mA 0.4 V VOH Output HIGH Voltage5 IOH = –8mA Ioz 3-state Leakage Current S1 = S2 = GND – – 10 µA Idd Power-Down Supply Current Ref = 0 MHz – – 50 µA Idd Dynamic Supply Current Unload outputs, 66.66 MHz, select inputs at VDD or GND. – – 40 mA Max. Units 150 MHz 50 55 % – 1.5 nSec 1.5 nSec Vdc 2.4 V Switching Characteristics (Z9305/Z9309) (VDD = 3.0 – 3.6V, TA = –40°C to 85°C) Parameter Fin – Description Test Conditions Min. Frequency 30 pF load 10 Duty Cycle (T2/T1)[6] Measured @ 1.4V 45 [6] Typ. t3 Rise Time t4 Fall Time[6] Measured between 0.8V and 2.0V 15 pF Load t5 Output-to-Output Skew[6] All output equally loaded – – 250 pSec t6 Delay, REF Rising Edge to CLKOUT Rising Edge[6] Measured at VDD/2 – 0 + 350 pSec t7 Device-to-Device Skew[6] Measured at VDD/2 on FBK pins of devices - 0 700 pSec tj Cycle-to-Cycle Jitter[6] Measured at 66.67 MHz, loaded outputs, input Trise/Fall < 1 nS – – 200 pSec Maximum PLL Lock Time[6] Stable power supply, valid clocks presented on REF pin. 1.0 ms tLOCK Measured between 0.8V and 2.0V 15 pF Load Notes: 4. REF and FBK inputs have a threshold voltage of VDD/2. 5. Parameter is guaranteed by design and characterization. Not 100% tested in production. All parameters specified with loaded outputs. 6. Parameter is guaranteed by design and characterization. Not 100% tested in production. All parameters specified with loaded outputs. Document #: 38-07196 Rev. ** Page 4 of 7 Z9305/Z9309 Test Circuit Diagram Package Drawing and Dimensions (16-pin 150-mil SOIC) VDD C 0.1 uF Outputs L CLK out H E CLOAD VDD 0.1 uF GND GND a D Test Circuit A2 A Package Drawing and Dimensions A1 B C L Parameter A A1 A2 B C D E e H L a a D A2 A A1 e B 8-pin SOIC Outline Dimensions Inches Min. Nom. Max. Min. Nom. Max. A 0.053 - 0.069 1.35 - 1.75 A1 0.004 - 0.010 0.10 - 0.25 A2 0.047 - 0.059 1.20 - 1.50 B 0.013 - 0.020 0.33 - 0.51 C 0.007 - 0.010 0.19 - 0.25 D 0.189 - 0.197 4.80 - 5.00 E 0.150 - 0.157 3.80 - 4.00 0.050 BSC 1.27 BSC H 0.228 - 0.244 5.80 - 6.20 L 0.016 - 0.050 0.40 - 1.27 a 0º - 8º 0º - 8º Document #: 38-07196 Rev. ** Inches Nom. Max. 0.069 0.010 0.059 0.020 0.010 0.394 0.157 0.050 BSC 0.228 0.244 0.016 0.050 0º 8º Min. 0.053 0.004 0.047 0.013 0.007 0.366 0.150 Millimeters Min. Nom. Max. 1.35 1.75 0.10 0.25 1.20 1.50 0.33 0.51 0.19 0.25 9.80 10.00 3.80 4.00 1.27 BSC 5.80 6.20 0.40 1.27 0º 8º Millimeters Parameter e 16-pin SOIC Outline Dimensions (150 mil) H E e 16-pin TSSOP Outline Dimensions Parameter A A1 A2 B C D E e H L a Inches Nom. Max. 0.047 0.006 0.039 0.041 0.012 0.008 0.197 0.201 0.173 0.177 0.026 BSC 0.244 0.252 0.260 0.018 0.024 0.030 0º 8º Min. 0.002 0.031 0.007 0.004 0.193 0.169 Millimeters Min. Nom. Max. 1.20 0.05 0.15 0.80 1.00 1.05 0.19 0.30 0.09 0.20 4.90 5.00 5.10 4.30 4.40 4.50 0.65 BSC 6.20 6.40 6.60 0.45 0.60 0.75 0º 8º Page 5 of 7 Z9305/Z9309 Ordering Information Part Number Package Type Production Flow Z9305DZ 8-pin SOIC Commercial, –40°C to +85°C Z9309CZ 16-pin SOIC Commercial, –40°C to +85°C Z9309CT 16-pin TSSOP Commercial, –40°C to +85°C The ordering part number is formed by a combination of device number, device revision, package style, and screening as shown below. Marking: Example: Date Code Z9305DZ Lot # Marking: Example: Date Code Z9309CZ Lot # Z9309CZ Z9305DZ Package Z = SOIC, 150 Mil. T = TSSOP Package Z = SOIC, 150 Mil. T = TSSOP Revision Revision Cypress Device Number Cypress Device Number Pentium® and Pentium Pro® are registered trademarks of Intel Corporation. All product and company names mentioned in this document are the trademarks of their respective holders. Document #: 38-07196 Rev. ** Page 6 of 7 © Cypress Semiconductor Corporation, 2001. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. Z9305/Z9309 Document Title: Z9305/Z9309 3.3V 150 MHz Multi-Output Zero Delay Buffer Document Number:38-07196 REV. ECN NO. Issue Date Orig. of Change ** 111328 12/17/01 DMG Document #: 38-07196 Rev. ** Description of Change New Data Sheet Page 7 of 7