ICS671-06 3.3 VOLT ZERO DELAY, LOW SKEW BUFFER Description Features The ICS671-06 is a low phase noise, high-speed PLL-based, 8 output, low skew zero delay buffer. Based on ICS’ proprietary low jitter Phase-Locked Loop (PLL) techniques, the device provides eight low skew outputs at speeds up to 133 MHz at 3.3 V. The outputs can be generated from the PLL (for zero delay), or directly from the input (for testing), and can be set to tri-state mode or to stop at a low level. For normal operation as a zero delay buffer, any output clock is tied to the FBIN pin. • • • • • • Clock outputs from 10 to 133 MHz • • • • • • • 5 V tolerant FBIN and CLKIN pins ICS manufactures the largest variety of clock generators and buffers and is the largest clock supplier in the world. Zero input-output delay Eight low skew (<200 ps) outputs Device-to-device skew <700 ps Low jitter (<200 ps) Full CMOS outputs with 25 mA output drive capability at TTL levels Tri-state mode for board-level testing Advanced, low power, sub-micron CMOS process Operating voltage of 3.3 V Industrial temperature range available Packaged in 16-pin SOIC Available in Pb (lead) free package Not recommended for new designs. See the MK2308-1H for new designs. Block Diagram VDD 2 S2, S1 Control Logic 2 CLKA1 CLKA2 CLKA3 CLKIN CLKA4 1 Clock Synthesis PLL FBIN 0 CLKB1 CLKB2 CLKB3 CLKB4 GND Feedback is shown from CLKB4 for illustration, but may come from any output. 1 MDS 671-06 D In te grated Circui t Systems 2 l 5 25 Race Stre et, San Jose, CA 9 5126 Revision 050405 l te l (4 08) 297 -1201 l w w w. i c s t . c o m ICS671-06 3.3 VOLT ZERO DELAY, LOW SKEW BUFFER Pin Assignment C L K IN 1 16 F B IN C LKA1 2 15 CLKA4 C LKA2 3 14 CLKA3 VDD 4 13 VDD GND 5 12 GND C LKB1 6 11 CLKB4 C LKB2 7 10 CLKB3 S2 8 9 S1 1 6 p in n a rro w (1 5 0 m il) S O IC a n d 1 6 p in (1 7 3 m il ) T S S O P Output Clock Mode Select Table S2 S1 CLKA1:A4 CLKB1:B4 A & B Source PLL Status 0 0 Tri-state (note 1) Tri-state (note 1) PLL OFF 0 1 Running Tri-state (note 1) PLL ON 1 0 Running Running CLKIN (note 2) OFF 1 1 Running Running PLL ON Note 1. Outputs are in high impedance state. Note 2. Buffer mode only; not zero delay between input and output. Pin Descriptions Pin Number Pin Name Pin Type 1 CLKIN Input 2 - 3, 14 - 15 CLKA1:A4 Output Clock outputs A1:A4. See table above. 4 VDD Power Power supply. Connect to 3.3 V. 5 GND Power Connect to ground. 6 - 7, 10 - 11 CLKB1:B4 Output Clock outputs B1:B4. See table above. 8 S2 Input Select input 2. See table above. Internal pull-up. 9 S1 Input Select input 1. See table above. Internal pull-up. 12 GND Power Connect to ground. 13 VDD Power Power supply. Connect to 3.3 V. 16 FBIN Input Clock input. Feedback input. Connect to any output under normal operation. 2 MDS 671-06 D Integrated Ci rcu it Systems Pin Description l 525 Ra ce St reet, San Jose , CA 9512 6 Revision 050405 l tel (408 ) 29 7-120 1 l w w w. i c s t . c o m ICS671-06 3.3 VOLT ZERO DELAY, LOW SKEW BUFFER External Components The ICS671-06 requires a minimum number of external components for proper operation. Decoupling capacitors of 0.01µF should be connected between VDD and GND on pins 4 and 5, and VDD and GND on pins 13 and 12, as close to the device as possible. A series termination resistor of 33Ω may be used to each clock output pin to reduce reflections. Absolute Maximum Ratings Stresses above the ratings listed below can cause permanent damage to the ICS671-06. These ratings, which are standard values for ICS commercially rated parts, are stress ratings only. Functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over the recommended operating temperature range. Item Rating Supply Voltage, VDD 7V All Inputs and Outputs -0.5 V to VDD+0.5 V CLKIN and FBIN inputs -0.5 V to 5.5 V Electrostatic Discharge 2000 V Ambient Operating Temperature -40 to +85°C Storage Temperature -65 to +150°C Junction Temperature 150°C Soldering Temperature 260°C Recommended Operation Conditions Parameter Min. Typ. Max. Units Ambient Operating Temperature -40 +85 °C Power Supply Voltage (measured in respect to GND) +3.0 +3.6 V DC Electrical Characteristics VDD=3.3 V ±5%, Ambient temperature -40 to +85°C, unless stated otherwis Parameter Symbol Conditions Min. Operating Voltage VDD 3.0 Input High Voltage VIH 2 Input Low Voltage VIL Input Low Current IIL Input High Current IIH l Max. Units 3.6 V V 0.8 V VIN = 0V 50 mA VIN = VDD 100 uA 3 MDS 671-06 D Integrated Ci rcu it Systems Typ. 525 Ra ce St reet, San Jose , CA 9512 6 Revision 050405 l tel (408 ) 29 7-120 1 l w w w. i c s t . c o m ICS671-06 3.3 VOLT ZERO DELAY, LOW SKEW BUFFER Parameter Symbol Conditions Min. Typ. Max. Units Output High Voltage VOH IOH = -12 mA Output Low Voltage VOL IOL = 12 mA Output High Voltage, CMOS level VOH IOH = -12 mA Operating Supply Current IDD No Load, S2 = 1, S1 = 1, Note 1 Power Down Supply Current IDD CLKIN = 0, S2 = 0, S1 = 1 12 µA CLKIN = 0, Note 2 12 µA Short Circuit Current IOS Each output ±50 mA Input Capacitance CIN S2, S1, FBIN 5 pF 2.4 V 0.4 VDD-0.4 V V 35 mA AC Electrical Characteristics VDD = 3.3 V ±5%, Ambient Temperature -40 to +85°C, CLOAD at CLK = 15 pF, unless stated otherwise Parameter Symbol Input Clock Frequency fIN Output Clock Frequency Conditions Min. Typ. Max. Units See table on page 2 10 133 MHz See table on page 2 10 133 MHz Output Rise Time tOR 0.8 to 2.0 V, CL = 30 pF 2.5 ns Output Fall Time tOF 2.0 to 0.8 V, CL = 30 pF 2.5 ns Output Clock Duty Cycle tDC Measured at VDD/2 55 % 45 50 Device to Device Skew Rising edges at VDD/2 700 ps Output to Output Skew Rising edges at VDD/2 200 ps Input to Output Skew Rising edges at VDD/2, FBIN to CLKA4, S1 = 1, S0 = 1, Note 1 ±250 ps 200 ps 30 pF, measured at 66.67M 200 ps 15 pF, measured at 66.67M 200 ps 15 pF, measured at 133.33M 100 ps Note 3 1.0 ms Maximum Absolute JItter Cycle to Cycle Jitter PLL Lock Time 130 Note 1: With CLKIN = 100MHz, FBIN to CLKA4, all outputs at 100 MHz. Note 2: When there is no clock signal present at CLKIN, the ICS671-06 will enter power down mode. The PLL is stopped and the outputs are tri-state. Note 3: With VDD at a steady rate and valid clocks at CLKIN and FBIN. 4 MDS 671-06 D Integrated Ci rcu it Systems l 525 Ra ce St reet, San Jose , CA 9512 6 Revision 050405 l tel (408 ) 29 7-120 1 l w w w. i c s t . c o m ICS671-06 3.3 VOLT ZERO DELAY, LOW SKEW BUFFER Thermal Characteristics (16 pin SOIC) Parameter Thermal Resistance Junction to Ambient Thermal Resistance Junction to Case Conditions Min. Typ. Max. Units θJA Still air 120 °C/W θJA 1 m/s air flow 115 °C/W θJA 3 m/s air flow 105 °C/W 58 °C/W θJC 5 MDS 671-06 D Integrated Ci rcu it Systems Symbol l 525 Ra ce St reet, San Jose , CA 9512 6 Revision 050405 l tel (408 ) 29 7-120 1 l w w w. i c s t . c o m ICS671-06 3.3 VOLT ZERO DELAY, LOW SKEW BUFFER Package Outline and Package Dimensions (16-pin SOIC, 150 Mil. Narrow Body) Package dimensions are kept current with JEDEC Publication No. 95 Millimeters 16 Symbol E Min A A1 B C D E e H h L α H INDEX AREA 1 2 D A Inches Max Min 1.35 1.75 0.10 0.25 0.33 0.51 0.19 0.25 9.80 10.00 3.80 4.00 1.27 BASIC 5.80 6.20 0.25 0.50 0.40 1.27 0° 8° Max .0532 .0688 .0040 .0098 .013 .020 .0075 .0098 .3859 .3937 .1497 .1574 0.050 BASIC .2284 .2440 .010 .020 .016 .050 0° 8° h x 45 A1 C -Ce SEATING PLANE B L .10 (.004) C Ordering Information Part / Order Number Marking Shipping Packaging Package Temperature ICS671M-06I ICS671M-06IT ICS671M-06ILF ICS671M-06ILFT ICS671M-06I ICS671M-06I ICS671M-06IL ICS671M-06IL Tubes Tape and Reel Tubes Tape and Reel 16-pin SOIC 16-pin SOIC 16-pin SOIC 16-pin SOIC -40 to +85° C -40 to +85° C -40 to +85° C -40 to +85° C Parts that are ordered with a "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant. While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems (ICS) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 6 MDS 671-06 D Integrated Ci rcu it Systems l 525 Ra ce St reet, San Jose , CA 9512 6 Revision 050405 l tel (408 ) 29 7-120 1 l w w w. i c s t . c o m