a FEATURES All-In-One Synchronous Buck Driver One PWM Signal Generates Both Drives Anticross-Conduction Protection Circuitry Programmable Transition Delay Synchronous Override Control Undervoltage Lockout Programmable Overvoltage Shutdown V CC Good Signal Drives Auxiliary Circuits Shutdown Quiescent Current < 10 A Dual MOSFET Driver with Bootstrapping ADP3410 FUNCTIONAL BLOCK DIAGRAM VCC ADP3410 VCCGD 4.4V GND BST DRVH SD IN APPLICATIONS Mobile Computing CPU Core Power Converters Multiphase Desktop CPU Supplies Single-Supply Synchronous Buck Converters Standard-to-Synchronous Converter Adaptations DLY CONTROL AND OVERLAP PROTECTION CIRCUIT VCC SW VCC OVPSET DRVL 1.2V SRMON DRVLSD PGND The ADP3410 is a dual MOSFET driver optimized for driving two N-channel FETs that are the two switches in the nonisolated synchronous buck power converter topology. Each of the drivers is capable of driving a 3000␣ pF load with a 20␣ ns propagation delay and a 30␣ ns transition time. One of the drivers can be bootstrapped, and is designed to handle the high-voltage slew rate associated with “floating” high-side gate drivers. The ADP3410 has several protection features: overlapping drive prevention (ODP), undervoltage lockout (UVLO) with performance specified at very low VCC levels, and overvoltage protection (OVP) that can be used to monitor either the input or output. Additional features include: programmable transition delay, a synchronous drive override control pin, a synchronous drive status monitor and, in conjunction with exiting from the UVLO mode, a VCC Good (VCCGD) signal capable of driving a 10␣ mA load. The quiescent current, when the device is disabled, is less than 10 µA. VBATT 5V GENERAL DESCRIPTION SD TO PWM CONTROLLER VCC VCCGD ADP3410 BST IN DRVLSD SRMON OVPSET DRVH VOUT SW DRVL DLY GND PGND Figure 1. Typical Application Circuit REV. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 1999 (TA = 0ⴗC to 85ⴗC, VCC = 5 V, VBST = 4 V to 26 V, SD > 2 V, unless otherwise ADP3410–SPECIFICATIONS1 noted) Parameter SUPPLY Supply Voltage Range Quiescent Current Shutdown Mode Operating Mode VCCGD OUTPUT Output Voltage High Output Voltage Low VCCGD Propagation Delay2, 3 (See Figure 4) SYNCHRONOUS RECTIFIER MONITOR Output Voltage High Output Voltage Low Transition Time2 Propagation Delay2, 3 Symbol VCC ICCQ OVERVOLTAGE PROTECTION Trip Threshold Hysteresis Bias Current OVP2, 3, 4 Propagation Delay SYNCHRONOUS RECTIFIER ENABLE DRVLSD Input Voltage High5 Input Voltage Low5 Propagation Delay2, 3 (See Figure 3) Min Typ Max Unit 4.15 5.0 6.0 V 1 10 2 µA mA 0.2 10 10 V V µs µs 50 20 15 V mV ns ns 15 ns 4.6 V V V µs µs VSD < 0.8 V VSD > 2.0 V, No Switching tpdhVCCGD , tpdlVCCGD VCC = 4.6 V, ILOAD = 10 mA VCC < UVLO, I LOAD = 10 µA SD Goes High SD Goes Low 4.5 trSRMON, tfSRMON tpdhSRMON VCC = 4.6 V, C LOAD = 100 pF VCC = 4.6 V, C LOAD = 100 pF DRVLSD Is High and DRVL Goes High, or DRVLSD Goes Low DRVLSD Is High and DRVL Goes Low 4.2 tpdhUVLO tpdlUVLO 4.4 0.05 1.5 10 10 VCC Goes High VCC Goes Low 1.145 1.2 0.8 0.2 tpdhOVP VCC = 4.6 V, OVPSET Goes High 1.255 1.0 0.5 2.0 0.8 tpdlDRVLSD, tpdhDRVLSD VCC = 4.6 V, CLOAD (DRVL) = 3 nF 30 SD INPUT Input Voltage High5 Input Voltage Low5 2.0 PWM INPUT (IN) Input Voltage High5 Input Voltage Low5 2.0 THERMAL SHUTDOWN Overtemperature Trip Point OTP Hysteresis HIGH-SIDE DRIVER Output Resistance, Sourcing Current Output Resistance, Sinking Current DRVH Transition Times2 (See Figure 6) DRVH Propagation Delay2, 3 (See Figure 6) 4.55 0.1 4.15 tpdlSRMON UNDERVOLTAGE LOCKOUT UVLO Threshold UVLO Hysteresis UVLO Logic Active Threshold UVLO2, 3 Propagation Delay (See Figure 5) Conditions trDRVH, tfDRVH tpdhDRVH, tpdlDRVH VBST – VSW = 4.6 V –2– 10 V V ns 0.8 V V 0.8 V V °C °C 165 10 VBST – VSW = 4.6 V VBST – VSW = 4.6 V VBST – VSW = 4.6 V, CLOAD = 3 nF V V µA µs 2.5 2.5 20 5 5 35 Ω Ω ns 20 Note 6 25 ns ns REV. 0 ADP3410 Parameter LOW-SIDE DRIVER Output Resistance, Sourcing Current Output Resistance, Sinking Current DRVL Transition Times2 (See Figure 6) DRVL Propagation Delay2, 3 (See Figure 6) Symbol trDRVL, tfDRVL tpdhDRVL tpdlDRVL Conditions Min VCC = 4.6 V VCC = 4.6 V VCC = 4.6 V, C LOAD = 3 nF VCC = 4.6 V Typ Max Unit 2.5 2.5 20 5 5 35 Ω Ω ns 30 25 ns ns 5 NOTES 1 All limits at temperature extremes are guaranteed via correlation using standard Statistical Quality Control (SQC) methods. 2 AC specifications are guaranteed by characterization, but not production tested. 3 For propagation delays, tpdh refers to the specified signal going high, tpdl refers to it going low. 4 Propagation delay measured until DRVL begins its transition. 5 Logic inputs meet typical CMOS I/O conditions for source/sink current (~1 mA). 6 Maximum propagation delay = 40 ns max + (1 ns/pF × CDLY). Specifications subject to change without notice. ABSOLUTE MAXIMUM RATINGS* ORDERING GUIDE VCC to PGND . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V BST to PGND . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +30 V BST to SW . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V SW to PGND . . . . . . . . . . . . . . . . . . . . . . . . –2.0 V to +25 V OVPSET to PGND . . . . . . . . . . . . . . . . . . . . –0.3 V to +10 V SD, IN, DRVLSD to GND . . . . . . . . . . . . . . –0.3 V to +7.3 V GND to PGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 0.3 V Operating Ambient Temperature Range . . . . . . . 0°C to 85°C Operating Junction Temperature Range . . . . . . 0°C to 125°C θJA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155°C/W θJC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40°C/W Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . . 300°C Model Temperature Range Package Description Package Option ADP3410KRU 0°C to 85°C Thin Shrink Small RU-14 Outline Package (TSSOP-14) *This is a stress rating only; operation beyond these limits can cause the device to be permanently damaged. CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the ADP3410 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. REV. 0 –3– WARNING! ESD SENSITIVE DEVICE ADP3410 PIN FUNCTION DESCRIPTIONS Pin Mnemonic Function 1 OVPSET 2 SD 3 4 5 GND IN DRVLSD 6 DLY 7 VCCGD 8 9 10 11 VCC DRVL PGND SRMON 12 SW 13 14 DRVH BST Overvoltage Shutdown Sense Input. Shutdown occurs when this pin is driven above the specified threshold. It is a high-impedance comparator input, so an external resistor divider can be used to scale the controlling voltage for OVP. Shutdown. When high, this pin enables normal operation. When low, VCCGD, DRVH, and DRVL are forced low and the supply current (ICCQ) is minimized as specified. Signal Ground. The input signal and the capacitor at DLY should be closely referenced to this ground. TTL-level input signal which has primary control of the drive outputs. Synchronous Rectifier Enable. When low, this signal forces DRVL low. The propagation delay time is on the order of that for the main input signal, so it can be used for real time modulation control of DRVL. When DRVLSD is high, DRVL is enabled and controlled by IN. Low-High-Transition Delay. A capacitor from this pin to ground programs the propagation delay from turn-off of the lower FET to turn-on of the upper FET. The formula for the low-high-transition delay is DLY = CDLY × (1␣ ns/pF) + 20␣ ns. The rise time for turn-on of the upper FET is not included in the formula. VCC Good. This pin indicates the status of the undervoltage lockout. When VCC is high enough for the device to exit UVLO mode, the VCCGD pin is pulled up to VCC with the specified low impedance. This signal is capable of acting as a switched power rail for external circuitry, since it can source 10␣ mA and sink 10 µA. Input Supply. This pin should be bypassed to PGND with ~1 µF ceramic capacitor. Synchronous Rectifier Drive. Output drive for the lower (synchronous rectifier) FET. Power Ground. Should be closely connected to the source of the lower FET. Synchronous Rectifier Monitor. When DRVLSD is high, SRMON follows DRVL. When DRVLSD is low, SRMON is high. TTL-type output. This pin is connected to the buck switching node, close to the upper FET’s source. It is the floating return for the upper FET drive signal. Also, it is used to monitor the switched voltage to prevent turn-on of the lower FET until the voltage is below ~1 V. Thus, the high-low-transition delay is determined at this pin according to operating conditions. This pin can be subjected to voltages as low as 2 V below PGND. Buck Drive. Output drive for the upper (buck) FET. Floating Bootstrap Supply for the upper FET. A capacitor connected between BST and SW pins holds this bootstrapped voltage for the high-side FET as it is switched. The capacitor should be chosen between 0.1 µF and 1 µF. PIN CONFIGURATION OVPSET SD GND IN DRVLSD DLY VCCGD 14 13 12 11 10 9 8 1 2 3 4 5 6 7 BST DRVH SW SRMON PGND DRVL VCC ADP3410 –4– REV. 0 ADP3410 5V VBATT D1 VCC SD ADP3410 BIAS ENABLE VCC VCC VCCGD UVLO 4.4V BST DLY CDLY CBST DRVL DELAY 10% VCC DRVH Q1 IN SW VOUT Ra OVPSET Rb 1.2V VCC DRVL Q2 PGND 1V SRMON DRVLSD GND Figure 2. Functional Block Diagram IN 2.0V DRVLSD 0.8V tpdlDRVLSD DRVL Figure 3. DRVLSD Propagation Delay REV. 0 –5– tpdhDRVLSD ADP3410 2V SD 0.8V tpdhVCCGD tpdIVCCGD 3.5V VCCGD 10% VCC Figure 4. VCCGD Propagation Delay UVLO THRESHOLD UVLO THRESHOLD–HYSTERESIS VCC tpdIUVLO tpdhUVLO 90% VCC VCCGD 10% VCC Figure 5. UVLO Propagation Delay IN tpdlDRVL tfDRVL trDRVL tpdlDRVH 90% 90% DRVL 10% 10% tpdhDRVH tfDRVH trDRVH 90% DRVH-SW 90% VTH VTH 10% 10% tpdhDRVL SW 1V Figure 6. Nonoverlap Timing Diagram –6– REV. 0 Typical Performance Characteristics–ADP3410 2V/DIV 30 2V/DIV DRVH DRVL VCC = 5V CLOAD = 3nF 25 DRVL TIME – ns VOLTAGE DRVH IN IN VCC = 5V CLOAD = 3nF VSW = 0V 20ns/DIV 30 FALL TIME 85 VCC = 5V TA = 258C 30 25 RISE TIME 15 25 50 75 JUNCTION TEMPERATURE – 8C 35 VCC = 5V TA = 258C 20 0 Figure 9. DRVH Rise and Fall Times vs. Temperature 40 TIME – ns TIME – ns 0 Figure 8. DRVL Fall and DRVH Rise Times VCC = 5V CLOAD = 3nF 25 20 DRVH 10 DRVH 20 DRVL 15 10 DRVL 10 5 5 0 0 0 0 50 75 25 AMBIENT TEMPERATURE – 8C 85 Figure 10. DRVL Rise and Fall Times vs. Temperature 0 1 2 3 4 CAPACITANCE – nF 5 0 6 Figure 11. DRVH and DRVL Rise Times vs. Load Capacitance 30 35 SUPPLY CURRENT – mA tpdlDRVH 20 15 tpdlDRVL 10 2 3 4 CAPACITANCE – nF 5 6 11.0 VCC = 5V TA = 258C CLOAD = 3nF SUPPLY CURRENT – mA 25 1 Figure 12. DRVH and DRVL Fall Times vs. Load Capacitance 40 VCC = 5V CLOAD = 3nF TIME – ns FALL TIME 5 TIME – ns Figure 7. DRVH Fall and DRVL Rise Times 30 VCC = 5V CLOAD = 3nF CDLY = 20pF 20ns/DIV TIME – ns 35 15 10 TIME – ns VOLTAGE RISE TIME 20 30 25 20 15 10 VCC = 5V fIN = 250kHz CLOAD = 3nF 10.5 10.0 9.5 5 5 0 9.0 0 0 25 50 75 100 JUNCTION TEMPERATURE – 8C 125 Figure 13. Propagation Delay vs. Temperature REV. 0 0 200 400 600 800 1000 IN FREQUENCY – kHz Figure 14. Supply Current vs. Frequency –7– 1200 0 25 50 75 100 JUNCTION TEMPERATURE – 8C Figure 15. Supply Current vs. Temperature 125 ADP3410 SW pin has fallen to 1 V, Q2 will begin turn ON. By waiting for the voltage on the SW pin to reach 1 V, the overlap protection circuit ensures that Q1 is OFF before Q2 turns on, regardless of variations in temperature, supply voltage, gate charge, and drive current. THEORY OF OPERATION The ADP3410 is a dual MOSFET driver optimized for driving two N-channel FETs in a synchronous buck converter topology. A single PWM input signal is all that is required to properly drive the high-side and the low-side FETs. Each driver is capable of driving a 3 nF load with only a 20 ns transition time. To prevent the overlap of the gate drives during Q2’s turn OFF and Q1’s turn ON, the overlap circuit provides a programmable delay that is set by a capacitor on the DLY pin. When the PWM input signal goes high, Q2 will begin to turn OFF (after a propagation delay), but before Q1 can turn ON, the overlap protection circuit waits for the voltage at DRVL to drop to around 10% of VCC. Once the voltage at DRVL has reached the 10% point, the overlap protection circuit will wait for a 20 ns typical propagation delay plus an additional delay based on the external capacitor, CDLY. The delay capacitor adds an additional 1 ns/pF of delay. Once the programmable delay period has expired, Q1 will begin turn ON. The delay allows time for current to commutate from the body diode of Q2 to an external Schottky diode, which allows turn-off losses to be reduced. Although not as foolproof as the adaptive delay, the programmable delay adds a safety margin to account for variations in size, gate charge, and internal delay of the external power MOSFETs. A more detailed description of the ADP3410 and its features follows. Refer to the functional block diagram. Low-Side Driver The low-side driver is designed to drive low-RDS(ON) N-channel MOSFETs. The maximum output resistance for the driver is 5 Ωs for both sourcing and sinking gate current. The low-output resistance allows the driver to have 20 ns rise and fall times into a 3 nF load. The bias to the low-side driver is internally connected to the VCC supply and PGND. When the driver is enabled, the driver’s output is 180° out of phase with the PWM input. When the driver is shut down or the entire ADP3410 is in shutdown or in under voltage lockout, the low-side gate is held low. High-Side Driver The high-side driver is designed to drive a floating low RDS(ON) N-channel MOSFET. The maximum output resistance for the driver is 5 Ωs for both sourcing and sinking gate current. The low output resistance allows the driver to have 20 ns rise and fall times into a 3 nF load. The bias voltage for the high-side driver is developed by an external bootstrap supply circuit, which is connected between the BST and SW pins. Overvoltage Protection An overvoltage protection circuit monitors the output voltage for an overvoltage condition. This condition is possible if Q1 should fail. If this should occur, the output voltage would begin to rise up to the battery voltage where it would pose the threat of damage to the devices connected to the output. By adding a resistor divider, Ra and Rb, to the OVPSET pin, the output voltage can be monitored for this fault condition. The bootstrap circuit comprises a Schottky diode, D1, and bootstrap capacitor, CBST. When the ADP3410 is starting up, the SW pin is at ground, so the bootstrap capacitor will charge up to VCC through D1. As the input voltage ramps up and exceeds the UVLO threshold, the high-side driver is enabled. When the PWM input goes high, the high-side driver will begin to turn the high-side FET, Q1, ON by pulling charge out of CBST. As Q1 turns ON, the SW pin will rise up to V BATT, forcing the BST pin to VBATT + VC(BST), which is enough gateto-source voltage to hold Q1 ON. To complete the cycle, Q1 is switched OFF by pulling the gate down to the voltage at the SW pin. When the low-side FET, Q2, turns ON, the SW pin is pulled to ground. This allows the bootstrap capacitor to charge up to VCC again. If the voltage on the OVPSET pin exceeds the 1.2 V threshold, this indicates a fault condition and Q1 is turned OFF and the low-side FET (synchronous rectifier) is turned ON. The power switches will remain in this state until the voltage on the OVPSET pin falls below 400 mV. The turn-on of Q2 is not delayed by monitoring the SW voltage, but the triggering of OVP is intentionally slow to avoid false triggering. Low-Side Driver Enable The low-side driver enable (DRVLSD) allows external control of the synchronous rectifier. This is particularly useful for maintaining efficiency under light load conditions. At light loads, the PWM duty cycle becomes small, meaning the high-side switch is ON for a very short time and the synchronous rectifier is ON for the remainder of the period. Under these conditions, the inductor current ramps up during the short high-side switch ON time, and then ramps down during the synchronous rectifier’s ON time. If the inductor current reaches zero and there is still time left in the period, the inductor current will begin to go negative. Negative current indicates that current is being drawn out of the output capacitor through the inductor and low-side FET to ground, incurring extra losses in the process. If the DRVLSD is used to shut down the low-side driver when the inductor current reaches zero, the light load efficiency can be dramatically improved. If inductor current information is not available, but a microprocessor is performing a power management function, it can shut down the synchronous rectifier when in a sleep or stand-by mode. The high-side driver’s output is in phase with the PWM input. When the driver is in under-voltage lockout, the high-side gate is held low. Overlap Protection Circuit The Overlap Protection Circuit (OPC) prevents both of the main power switches, Q1 and Q2, from being ON at the same time. This is done to prevent shoot-through currents from flowing through both power switches and the associated losses that can occur during their ON-OFF transitions. The overlap protection circuit accomplishes this by adaptively controlling the delay from Q1’s turn OFF to Q2’s turn ON, and by programming the delay from Q2’s turn OFF to Q1’s turn ON. To prevent the overlap of the gate drives during Q1’s turn OFF and Q2’s turn ON, the overlap circuit monitors the voltage at the SW pin. When the PWM input signal goes low, Q1 will begin to turn OFF (after a propagation delay), but before Q2 can turn ON, the overlap protection circuit waits for the voltage at the SW pin to fall from VBATT to 1 V. Once the voltage on the When the DRVLSD input is low, the low-side driver output goes low. When the DRVLSD input is high the low-side driver is enabled and controlled by the PWM input. The propagation –8– REV. 0 ADP3410 delay from the DRVLSD input to the DRVL output is about 30 ns. Bootstrap Circuit The bootstrap circuit requires a charge storage capacitor, CBST, and a Schottky diode, D1, as shown in Figure 2. Selecting these components can be done after the high-side FET has been chosen. Synchronous Rectifier Monitor The synchronous rectifier monitor provides a TTL output signal for use by the PWM controller. The SRMON output follows the DRVL signal when the low-side driver is enabled and goes high when the low-side driver is shut down. The bootstrap capacitor must have a voltage rating that is able to handle the maximum battery voltage plus 5 V. A minimum 50 V rating is recommended. The capacitance is determined using the following equation: Shutdown The shutdown input is used for power management. If the circuits running off of the buck converter are not needed, the ADP3410 can be shut down to conserve power. CBST = When the SD pin is high, the ADP3410 is enabled for normal operation. Pulling the SD pin low forces the VCCGD, DRVH and DRVL outputs low turning the buck converter OFF and reducing the VCC supply current to less than 10 µA. QGATE ∆VBST (1) where QGATE is the total gate charge of the high-side FET, and ∆VBST is the voltage droop allowed on the high-side FET drive. For example, the IRF7811 has a total gate charge of about 20 nC. For an allowed droop of 200 mV, the required bootstrap capacitance is 100 nF. Look for a good quality ceramic capacitor. Undervoltage Lockout The undervoltage lockout (UVLO) circuit holds both FET driver outputs low during VCC supply ramp up. The UVLO logic becomes active and in control of the driver outputs at a supply voltage of 1.5 V. The UVLO circuit will wait until the VCC supply has reached a voltage high enough to bias logic level FETs fully ON, around 4.4 V, before releasing control of the drivers to the PWM input. A Schottky diode is recommended for the bootstrap diode due to its low forward drop, which maximizes the drive available for the high-side FET. The bootstrap diode must have a minimum 40 V rating to withstand the maximum battery voltage plus 5 V. The average forward current can be estimated by: VCC Good where fMAX is the maximum switching frequency of the controller. The peak surge current rating should be checked in circuit since this is dependent on the source impedance of the 5 V supply, and the ESR of CBST. I F ( AVG ) ≈ QGATE × f MAX The power ready signal, VCCGD, indicates the status of the VCC supply. When the device is in UVLO, the VCCGD output is pulled low by an NMOS transistor. Upon exiting UVLO mode, the VCCGD pin is pulled up to VCC with a 5 Ω PMOS transistor capable of sourcing current to external load circuits. As can be seen from the block diagram, the UVLO comparator output and the SD signal are ANDed together to become the VCCGD output, so when the device is put into shutdown the VCCGD output will be low regardless of the VCC voltage. Setting the OVP Threshold The ADP3410 can shut down the high-side FET drive when the OVPSET input exceeds the threshold voltage. The voltage at which V OUT trips the overvoltage protection is set by selecting the values for Ra and Rb shown in Figure 2. The threshold for the OVP is calculated using: Thermal Shutdown Ra VOVP = 1.2 V × 1 + Rb The thermal shutdown circuit protects the ADP3410 against damage due to excessive power dissipation. Under extreme conditions, high ambient temperature and high-power dissipation, the die temperature can rise up to the over-temperature trip point of 165°C. If the die temperature exceeds 165°C, the thermal shutdown circuit will turn the output drivers OFF. The drivers will remain disabled until the junction temperature has decreased by 10°C, at which point the drivers are enabled again. (3) where VOVP is the desired OVP threshold voltage at VOUT. In order to minimize the bias current error, Rb should be less than or equal to 24 kΩ. By selecting a value for Rb ≤ 24 kΩ and solving for Ra gives the following formula: V Ra = OVP − 1 × Rb 1.2 V APPLICATION INFORMATION Supply Capacitor Selection For the supply input (VCC) of the ADP3410, a local bypass capacitor is recommended to reduce the noise and to supply some of the peak currents drawn. Use a 5 µF to 10 µF, low ESR capacitor. Multilayer ceramic chip (MLCC) capacitors provide the best combination of low ESR and small size and can be obtained from the following vendors: (4) Note that the minimum the OVP threshold can be is 1.2 V when Ra is zero. Delay Capacitor Selection The delay capacitor, CDLY , is used to add an additional delay when the low-side FET drive turns off and when the high-side drive starts to turn on. The delay capacitor adds 1 ns/pF of additional time to the 20 ns of fixed delay. Murata GRM235Y5V106Z16 http://www.murata.com Taiyo-Yuden EMK325F106ZF http://www.t-yuden.com Tokin C23Y5V1C106ZP http://www.tokin.com If a delay capacitor is required, a good quality ceramic capacitor with an NPO or COG dielectric or a good quality mica capacitor should be used. Both types of capacitors are available in the 1 pF to 100 pF range and have excellent temperature and leakage characteristics. A lower cost alternative may be to use a 5 µF to 10 µF tantalum capacitor with a small (1 µF) ceramic in parallel. Keep the ceramic capacitor as close as possible to the ADP3410. REV. 0 (2) –9– ADP3410 Printed Circuit Board Layout Considerations Typical Application Circuit Use the following general guidelines when designing printed circuit boards: The circuit in Figure 16 shows how the ADP3410 can be combined with the ADP3421 to form a total power conversion solution for a microprocessor. The combination provides the supply voltages for the core processor, the I/O interface, and the clock. 1. Trace out the high-current paths and use short, wide traces to make these connections. 2. Split the ground connections. Use separate planes for the signal and power grounds, and tie them together at a single point near the ADP3410. 3. The VCC bypass capacitor should be located as close as possible to VCC and PGND pins. 5V VIN 3.3V U1 R1 51.1kV R2 160kV C2 100nF 2 CLSET CS+ 27 3 LTO REG 26 4 LTI Q2 2N3906 Q1 MJD210 C3 68mF VCC 24 C14 100mF 6 VID4 OUT 23 7 VID3 GND 22 8 VID2 DACOUT 21 9 VID1 CORE 20 10 VID0 SSC 19 11 CLKDRV SSL 18 12 CLKFB UVLO 17 13 IODRV PWRGD 16 14 IOFB C25 1pF 22nF R21,10kV RAMP 25 5 LTB FROM CPU C31 C1 100nF C41 1pF C29 100pF R11 220kV C21 1.5nF C10 10mF R17 75kV R18 576kV R6 7.5kV C18 10pF C15 10mF C16 10mF D2 10BQ040 ADP3410 R19 2kV C23 1nF C22 1nF R22 100kV U2 CS– 28 1 VHYS R10 10kV R15 332V R16 3.3kV ADP3421 1 OVPSET 2 SD BST 14 3 GND 4 IN 5 DRVLSD PGND 10 6 DLY DRVL 9 7 VCCGD VCC 8 DRVH 13 C17 100nF M1 IRF7811 SW 12 C32 15nF L1 1mH R20 10V VCC CPU CORE RCS 5mV SRMON 11 R5 10kV M2 IRF7811 R8 2.2V M3 IRF7811 R9 2.2V D1 10BQ040 C4–C6, C11, C12, C26, C27 220mF 3 7 GND C28 10mF R12 470kV SD 15 VCC ON CORE SENSE V GATE VCC CPU IO VCC CPU CLK C20 10mF VRON Figure 16. Typical Application Circuit –10– REV. 0 ADP3410 OUTLINE DIMENSIONS Dimensions shown in inches and (mm). C3698–8–10/99 14-Lead Thin Shrink Small Outline Package (TSSOP) (RU-14) 0.201 (5.10) 0.193 (4.90) 14 8 0.177 (4.50) 0.169 (4.30) 0.256 (6.50) 0.246 (6.25) 1 7 PIN 1 0.006 (0.15) 0.002 (0.05) 0.0256 (0.65) BSC 0.0118 (0.30) 0.0075 (0.19) 0.0079 (0.20) 0.0035 (0.090) 88 08 0.028 (0.70) 0.020 (0.50) PRINTED IN U.S.A. SEATING PLANE 0.0433 (1.10) MAX REV. 0 –11–