IXYS IXS839 / IXS839A / IXS839B Synchronous Buck MOSFET Driver Features: General Description • Logic Level Gate Drive Compatible The IXS839/IXS839A/IXS839B are 2A Source / 4A Sink Synchronous Buck MOSFET Drivers. These Synchronous Buck MOSFET Drivers are specifically designed to drive two N-channel power MOSFETs in a synchronous buck converter. The High-Side driver is powered via a bootstrapped power connection. The driver is capable of 20ns High-Side output, and 18ns Low-Side output transition times driving a 3000pF load. • 2A Source, 4A Sink Peak Drive Current • Programmable High-Side Driver Turn-on Delay • Supports Floating Voltage for Top Driver Up to 24V • IXS839/839B: Undervoltage Lockout • IXS839A/B: Output Shutdown, Low Side Shutdown Inputs The IXS839 and IXS839B incorporate an undervoltage lockout to prevent unintentional gate drive output during low voltage conditions. The IXS83A/B include External Shutdown and Low-Side Drive Shutdown features. Simultaneous shutdown of both outputs prevents rapid output capacitor discharge. The high-side turn-on delay is adjustable with an external capacitor added at the DLY pin. • 10µA Shut Down Current • 2mA Quiescent Current (Non- Switching) • Bootstrapped High Side Driver • Cross-Conduction Protection Applications: • Multiphase Desktop CPU Supplies • High Current / Low Voltage DC/DC Synchronous Buck Converters The IXS839/839A/839B are designed to operate over a temperature range of -40°C to +85°C. The IXS839 is available in an 8-Lead SOIC, the IXS839A and the IXS839B in a 10-pin QFN. Figure 1. IXS839 Functional Block Diagram and General Application Circuit Figure 2. IXS839A Functional Block Diagram and General Application Circuit • Mobile CPU Core Voltage supplies 5V 4 5V VIN VDD 8 DBST DBST UVLO 1 8 PWM 2 BST Q1 HGD OVERLAP 7 SW CBST PWM 5 VOUT CIRCUIT DLY 2 SD Q1 BST 4 OVERLAP PROTECTION 3 HGD VIN VDD 3 5 CDLY 6 SW CBST VOUT 7 9 Q2 LGD CDLY PGND 10 LSD Copyright © IXYS CORPORATION 2004 1 CIRCUIT DLY LGD PROTECTION 6 PGND Q2 IXYS IXS839 / IXS839A / IXS839B Figure 3. IXS839B Functional Block Diagram and General Application Circuit 5V VIN VDD 5 DBST UVLO 10 9 SD BST Q1 HGD 1 OVERLAP PWM 2 PROTECTION 8 SW CBST VOUT CIRCUIT DLY 4 6 LGD Q2 CDLY 7 LSD PGND 3 Ordering Information Part No. IXS839S1 IXS839S1T/R IXS839AQ2 IXS839AQ2T/R IXS839BQ2 IXS839BQ2T/R Description Under Voltage Lockout Under Voltage Lockout Driver Shutdown, Low Side Shutdown Driver Shutdown, Low Side Shutdown Under Voltage Lockout , Driver Shutdown, Low Side Shutdown Under Voltage Lockout , Driver Shutdown, Low Side Shutdown Package 8-Pin SOIC 8-Pin SOIC 10-Pin QFN 10-Pin QFN 10-Pin QFN 10-Pin QFN Pack Quantity 98 (Tube) 2500 (Tape & Reel) 121 (Tube) 2000 (Tape & Reel) 121 (Tube) 2000 (Tape & Reel) Absolute Maximum Ratings Parameter Rating VDD BST BST to SW SW PWM Operating Ambient Temp Range -0.3V to +7V -0.3V to +30V -0.3V to +7V -0.2V to +24V -0.3V to +7V -40°C to +85°C Operating Junction Temp Range θJA θJC Storage Temp Range Lead Temperature (Soldering, 10 sec) -40°C to +125°C 150°C/W 40°C/W -65°C to +150°C +300°C Absolute Maximum Ratings are stress ratings. Stresses in excess of these ratings can cause permanent damage to the device. Functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this data sheet is not implied. Exposure of the device to the absolute maximum ratings for an extended period may degrade the device and affect its reliability. ESD Warning ESD (electrostatic discharge) sensitive device. Electrostatic charges can readily accumulate on test equipment and the human body in excess of 4000 Volts. This energy can discharge without detection. Although the IXS839/839A/839B feature proprietary ESD protection circuitry, permanent damage may be sustained if subjected to high energy electrostatic discharges. Proper ESD precautions are recommended to avoid performance degradation or loss of functionality. 2 IXYS IXS839 / IXS839A / IXS839B Pin Description and Configurations IXS839 IXS839A IXS839B Name 1 3 10 BST 2 5 2 PWM 3 7 4 DLY 4 8 5 VDD 5 9 6 LGD 6 10 7 PGND 7 1 8 SW 8 2 9 HGD N/A 4 1 __ SD 3 ___ LSD N/A 6 Description Upper Gate Driver Floating DC Power Terminal for Bootstrap Capacitor Connection. TTL-level Input Signal with active pull-down. PWM input to the Gate Drivers. Terminal for External Delay Capacitor Connection. Capacitor to Ground at this pin adds propagation delay from Lower Gate Driver going Low to the Upper Gate Driver going High. tDLY (nS) = CDLY (pF) x (0.5nS/pF) Positive Supply Terminal for Logic and Lower Gate Driver. A ceramic bypass capacitor of 1uF should be connected from VDD to PGND. Lower Gate Driver Output Terminal Lower Gate Driver DC Power Return Terminal, Logic and Analog Ground Upper Gate Driver Floating DC Power Return Terminal Upper Gate Driver Output Terminal TTL-level Shut Down Input Signal with active pull-up. SD enables normal operation when high. When SD is low, the driver outputs are forced low and IDD is at its minimum. TTL-level Low Side Shut Down Input Signal with active pullup. LSD, when low forces the Lower Gate Driver output low. When LSD is high, the lower Gate Driver output is enabled. SOIC and QFN Top View Pin Configurations 8 HGD BST 1 PWM 2 IXS839S1 7 SW DLY 3 6 PGND VDD 4 5 LGD SW 1 10 PGND HGD 2 IXS839AQ2 9 LGD BST 3 8 4 PWM 5 SD 3 SD 1 PWM 10 BST HGD 2 IXS839BQ2 9 VDD LSD 3 8 SW 7 DLY DLY 4 7 PGND 6 LSD VDD 5 6 LGD IXYS IXS839 / IXS839A / IXS839B Electrical Characteristics TA = -40°C to 85°C, VDD = 5V, 4V < VBST < 26V Power Supply Terminals Parameter Symbol Analog Supply Voltage Range High Gate Driver Supply Voltage Range Low Gate Driver Supply Voltage Range Floating Supply Voltage Range Analog Supply Current High Gate Driver Supply Current VDD IBST Analog Supply Current IDD_Shutdown High Gate Driver Supply Current IBST_Shutdown Min V VBST - VSW 4.5 5.5 V VDD - VPGND 4.5 5.5 V VSW - VPGDN 0.0 24.0 V 2 4 mA 0.5 1 1.5 mA Shut Down Mode, LSD = VDD, SD = PWM = VPGND IXS839/839B IXS839A IXS839/839B IXS839A Conditions Min µA Max Unit 1 µA 10 100 µA -2 -10 -100 µA -2 -10 -100 µA Input pull-up Current __ SD = VPGND Input pull-up Current ___ LSD = VPGND IIN Typ 2.0 VIH V VIL 0.8 V TA = -40°C to 85°C, VDD = 5V, 4V < VBST < 26V Symbol Conditions UVOLRISE UVOLFALL Min Typ Max Unit 4.2 3.9 4.4 4.25 4.5 4.5 V V TA = -40°C to 85°C, VDD = 5V, 4V < VBST < 26V Delay Circuit Upper Gate-Driver Turn on Delay Time with respect to external delay capacitor 10 TA = -40°C to 85°C, VDD = 5V, 4V < VBST < 26V Symbol 2 Parameter µA <1 PWM = VDD VDD Rising Threshold VDD Falling Threshold 10 50 Shut Down Mode LSD = PWM = VPGND Input pull-down Current UVLO Circuit Parameter Unit 5.5 -1 Minimum High Level Input Voltage Maximum Low Level Input Voltage Max 4.5 PWM = VPGND LSD = SD = VDD Input Leakage Current Typ VDD Normal Mode PWM = VPGND Normal Mode PWM = VPGND IDD Digital Input Terminals Parameter Conditions Symbol tDLY Conditions Capacitor CDLY(pF) from DLY pin to PGND 4 Min Typ 0.5 Max Unit nS/pF IXYS IXS839 / IXS839A / IXS839B Electrical Characteristics High Side Gate Driver Circuit Parameter Symbol High Side Gate-Driver On-Resistance, Sourcing Current High Side Gate-Driver On-Resistance, Sinking Current Typ Max Unit VBST – VSW = 4.6V 2.2 Ω RHGD_SNK VBST – VSW = 4.6V 1.2 Ω 20 nS 15 nS 35 50 nS nS tR_HGD High Side Gate-Driver(1) Fall-Time tF_HGD Propagation Delay(1) tPD_HGD1 tPD_HGD2 Low Side Gate Driver Circuit Parameter Symbol CLOAD = 3nF TR_HGD measured from 10% to 90% of (VHGD - VSW) CLOAD = 3nF TF_HGD measured from 90% to 10% of (VHGD - VSW) CLOAD_HGD = CLOAD_LGD = 3nF CDLY = 0pF TA = -40°C to 85°C, VDD = 5V, 4V < VBST < 26V Conditions Min Typ Max Unit RLGD_SRC VDD – VPGND = 4.6V 2 Ω RLGD_SNK VDD – VPGND = 4.6V 1 Ω 18 nS 12 nS 60 20 nS nS Low Side Gate-Driver(1) Rise-Time tR_LGD Low Side Gate-Driver(1) Fall-Time tF_LGD Propagation Delay(1) tPD_LGD1 tPD_LGD2 Shut Down Circuit Characteristics Parameter Symbol Propagation Delay(2) Propagation Delay(2) Propagation Delay(3) Propagation Delay(3) Min RHGD_SRC High Side Gate-Driver(1) Rise-Time Low Side Gate-Driver On-Resistance, Sourcing Current Low Side Gate-Driver On-Resistance, Sinking Current TA = -40°C to 85°C, VDD = 5V, 4V < VBST < 26V Conditions CLOAD = 3nF TR_LGD measured from 10% to 90% of (VLGD – VPGND) CLOAD = 3nF TF_LGD measured from 90% to 10% of (VLGD - VSW) CLOAD_HGD = CLOAD_LGD = 3nF CDLY = 0pF TA = -40°C to 85°C, VDD = 5V, 4V < VBST < 26V Conditions tPD_LGDSD1 tPD_LGDSD2 tPD_GDSD1 tPD_GDSD2 *Notes: (1) See Timing Diagram in Figure 4 (2) See Timing Diagram in Figure 5 (3) See Timing Diagram in Figure 6 5 Min Typ Max Unit 25 10 400 800 50 20 800 1200 nS nS nS nS IXYS IXS839 / IXS839A / IXS839B Figure 4. Non-Overlap Timing Diagram for IXS839/839A/839B PWM tpd_lgd2 tf_lgd tpd_hgd2 tr_lgd 90% 10% LGD tpd_lgd1 tr_hgd tf_hgd 90% HGD-SW tpd_hgd1 10% ___ Figure 5. LSD Propagation Delay Timing for IXS839A/B __ Figure 6. SD Propagation Delay Timing for IXS839A/B LSD SD 10% 10% tpd_lgdsd2 tpd_gdsd2 tpd_lgdsd1 LGD tpd_gdsd1 90% LGD/HGD 6 90% IXYS IXS839 / IXS839A / IXS839B Typical Performance Characteristics Fig 7. HGD Fall and LGD Rise Times Fig 8. LGD Fall and HGD Rise Times 20 20 15 Time (nS) 25 Time (nS) 25 HGD 10 LGD 10 HGD LGD 5 5 Vdd=5V Cl=3nF 0 -40 -15 10 35 Ta (°C) 60 20 20 Time (nS) HGD LGD 5 1.0 2.0 3.0 4.0 Capacitance (nF) 10 35 Ta (°C) 60 85 15 HGD 10 LGD 5 Vdd=5V Ta=25C 0 -15 Fig 10. HGD & LGD Fall Time vs. Temperature 25 10 Cl=3nF -40 85 25 15 Vdd=5V 0 Fig 9. HGD & LGD Rise Time vs. Temperature Time (nS) 15 0 1.0 5.0 Fig 11. HGD and LGD Rise Time vs. Load Capacitance Vdd=5V Ta=25C 2.0 3.0 4.0 Capacitance (nF) 5.0 Fig 12. HGD and LGD Fall Time vs. Load Capacitance 7 IXYS IXS839 / IXS839A / IXS839B Typical Performance Characteristics 50 50 40 Tpd_hgd2 30 20 Time (nS) Time (nS) 40 Tpd_hgd1 Tpd_lgd1 30 20 10 10 Vdd=5V Cl=3nF 0 -40 -15 10 35 Ta (°C) 60 Tpd_lgd2 0 -40 85 Fig 13. HGD Propagation Delay vs. Temperature 90 15 Idd (mA) 20 60 Ta=25C 1000 1500 Frequency (kHz) 85 Vdd=5V 250kHz Cl=3nF 0 0 500 60 10 5 Vdd=5V Cl=3nF 0 10 35 Ta (°C) Fig 14. LGD Propagation Delay vs. Temperature 120 30 -15 Vdd=5V Cl=3nF -40 2000 Fig 15. Supply Current vs. Frequency -15 10 35 Ta (°C) 60 85 Fig 16. Supply Current vs. Temperature 8 IXYS IXS839 / IXS839A / IXS839B Package Outlines 8-PIN SOIC QFN - 10 (REF.) TOP VIEW SIDE VIEW 9 IXYS IXS839 / IXS839A / IXS839B Theory of Operation The IXS839/839A/839B are dual MOSFET drivers, designed to drive two external N-channel power MOSFETs. The low-side driver is designed to drive a non-floating N-channel power MOSFET and its output is out of phase with the PWM input. The high-side driver is designed to drive a floating Nchannel power MOSFET and its output is in phase with the PWM input. An external bootstrap circuit provides the floating power supply to the high-side driver. The bootstrap circuit consists of a Schottky diode and a boost capacitor. When the PWM input transitions to a logic low, the low-side power MOSFET turns ON, the SW node is pulled to ground, and the bootstrap capacitor is charged to VDD through the Schottky diode. When the PWM transitions to a logic high, the high side power MOSFET begins to turn on and the SW node rises up to the input supply, VIN. In turn the boost capacitor raises the BST node voltage to a level equal to the input supply plus the boost capacitor voltage, providing sufficient voltage to the BST node to turn on the High-Side Power MOSFET. An internal cross-conduction prevention circuit monitors both gate driver outputs and allows each driver output to turn ON only when the other output driver turns OFF and falls below 1V. The IXS839A is a cost reduced Driver, differentiated by the absence of the undervoltage lockout protection circuit featured in the IXS839 and IXS839B. IXS839A/B must be enabled using the SD terminal when the driver supply reaches the operating range. SD can be used to turn off both driver outputs to prevent the rapid discharge of the buck converter output capacitors. An additional terminal, LSD can be used to turn off the Low-Side Gate Driver Output. The High-Side Gate Driver remains active in this mode. Detailed Circuit Description (Refer to the Application Diagrams) The PMW input signal controls both the High Side and Low Side power MOSFET drivers. The Power MOSFETs are driven so that the SW node follows the polarity of the PWM signal. 10 Low-Side Gate Driver The Low-Side Gate Driver is designed to drive a ground referenced N-Channel Power MOSFET. In a synchronous buck converter application, it drives the gate of the synchronous rectifier FET, (Q2). When the driver is enabled, (IXS839A/B SD=LSD=VDD), the driver output is 180˚ out of phase with the PWM input. The internal overlap protection circuit monitors the High-Side Gate Driver, and allows the Low-Side Gate Driver to turn on only when the High-Side Gate Driver output falls below 1.0 Volt. The supply rails for the Low-Side Gate Driver are VDD and PGND. High-Side Gate Driver The High-Side Gate Driver is designed to drive a floating N-Channel Power MOSFET referenced to SW. In a synchronous buck converter application, it drives the gate of the high side power MOSFET, (Q1). When the driver is enabled (IXS839A/B SD=VDD), the driver output is in phase with the PWM input. The bootstrap supply rails for the HighSide Gate Driver are BST and SW, and are generated by an external bootstrap circuit. The bootstrap circuit consists of a Schottky diode DBST, and a bootstrap capacitor CBST. During start up, the SW pin is at ground and the bootstrap capacitor CBST charges up to VDD through the Schottky diode DBST. When the PWM input transitions high the High-Side Gate Driver begins to turn Q1 ON by transferring charge from the bootstrap capacitor CBST to the gate of Q1. As Q1 turns on the SW pin will rise up to VIN, forcing the BST pin to VIN + VBOOSTCAP. This supplies the required gate to source voltage to Q1. When PWM transitions low the High-Side Driver and in turn Q1 switch off. When SW falls below 1 Volt the LowSide Gate Driver turns on and recharges the bootstrap capacitor which completes the cycle. Overlap Protection Circuit The overlap protection circuit (OPC) monitors the High Side and Low Side Gate Driver Outputs and prevents both main power switches, Q1 and Q2, from being ON at the same time. This inhibits excessive shoot-through currents and minimizes the associated losses. When the PWM input transitions low, Q1 begins to turn OFF, and Q2 turns ON only when the HighSide Gate Driver output falls below 1 volt. By IXYS IXS839 / IXS839A / IXS839B waiting for the voltage on the High Side Gate Driver Output pin to reach 1 volt, the overlap protection circuit ensures that Q1 is OFF before Q2 turns on. Similarly, when the PWM input transitions high, Q2 begins to turn OFF, and Q1 turns ON after the overlap protection circuit detects that the voltage at the Low-Side Gate Driver output has dropped below 1 volt. Once the driver output voltage falls below 1 volt, the overlap protection circuit initiates a delay timer that adds additional delay set by the external capacitor connected to the DLY pin. This programmable delay circuit allows adjustments to optimize performance based on the switching characteristics of the external power MOSFET. Low-Side Driver Shutdown The IXS839A/B include a Low-Side Gate Driver shutdown feature. A logic low signal at the LSD input shuts down the Low Side Gate Driver, and in turn the synchronous rectifier FET. This signal can be used to achieve maximum battery life under light load conditions and maximum efficiency under heavy load conditions. Under heavy load conditions, LSD should be high so that the synchronous switch is controlled by the PWM signal for maximum efficiency. Under light load conditions the LSD can be low to disable the Low Side Gate Driver so the switching current can be minimized. Shutdown For optimal system power management, the IXS839A/B drivers can be shut down to conserve power. When the SD pin is high, the IXS839A/B are enabled for normal operation. Pulling the SD pin low forces the HGD and LGD outputs low, and reduces the supply current by disabling the internal reference. Under Voltage Lockout (IXS839 and IXS839B) The Under Voltage Lockout (UVLO) circuit holds both driver outputs low during VDD supply rampup. The UVLO logic becomes active and in control of the driver outputs at a supply voltage of no greater than 1.5 V. When the supply voltage rises above the UVLO upper threshold the circuit allows the PWM input to control the drivers. 11 Application Information Supply Capacitor Selection A 1 uF ceramic bypass capacitor is recommended for the VDD input to provide noise suppression. The bypass capacitor should be located as close as possible to the IXS939/A/B. Bootstrap Circuit The bootstrap circuit requires a charge storage capacitor CBST and a Schottky diode DBST, as shown in Figure 1. Selecting these components should be done with consideration of the electrical characteristics of the high-side FET chosen. The bootstrap capacitor voltage rating must exceed the maximum input voltage, (VIN) + the maximum VDD voltage. The capacitance is determined using the following equation: Q CBST = GATE ∆VBST Where, QGATE is the total gate charge of Q1, and ∆VBST is the allowable Q1 voltage droop. To maximize the available drive for Q1 in the bootstrap circuit a Schottky diode is recommended. The bootstrap diode voltage rating must exceed the maximum input voltage, (VIN) + the maximum VDD voltage. The average forward current can be estimated by: IF(AVG) = QGATE X FMAX where FMAX is the maximum PWM input switching frequency. Peak surge current is dependent on the source impedance of the 5V supply and the ESR of CBST, and should be checked in-circuit. Delay Capacitor Selection A ceramic capacitor is recommended for the DLY input, and should be located as close a possible to the DLY pin. Printed Circuit Board Layout Considerations Use the following general guidelines when designing printed circuit boards: 1. Trace out the high current paths and use short, wide traces to make these connections. 2. Locate the VDD bypass capacitor as close as possible to the VDD and PGND pins. 3. Connect the source of the Lower MOSFET, (Q2) as close as possible the PGND.