UTRON Preliminary Rev. 0.1 UT62L51316(I) 512K X 16 BIT LOW POWER CMOS SRAM REVISION HISTORY REVISION Preliminary Rev. 0.1 Original. DESCRIPTION UTRON TECHNOLOGY INC. 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919 1 Draft Date Apr. 15, 2003 P80086 UTRON UT62L51316(I) 512K X 16 BIT LOW POWER CMOS SRAM Preliminary Rev. 0.1 FEATURES GENERAL DESCRIPTION Fast access time : 55/70/100ns CMOS low power operating Operating current : 30/20/16 (Icc) (TYP.) Standby current : 20uA (TYP.) L-version 2uA (TYP.) LL-version Single 2.7V~3.6V power supply Operation temperature: Industrial : -40℃~85℃ All TTL compatible inputs and outputs Fully static operation Three state outputs Data retention voltage:1.5V (min.) Data byte control : LB (I/O1~I/O8) UB (I/O9~I/O16) Package : 48-pin 12mmX20mm TSOP-I 48-ball 6mm × 8mm TFBGA The UT62L51316(I) is a 8,388,608-bit low power CMOS static random access memory organized as 524,288 words by 16 bits. The UT62L51316(I) operates from a single 2.7V ~ 3.6V power supply and all inputs and outputs are fully TTL compatible. The UT62L51316(I) is designed for low power system applications. It is particularly well suited for use in high-density low power system applications. FUNCTIONAL BLOCK DIAGRAM A0-A18 DECODER 512K × 16 MEMORY ARRAY I/O DATA CIRCUIT COLUMN I/O Vcc Vss I/O1-I/O8 Lower Byte I/O9-I/O16 Upper Byte CE2 CE OE WE CONTROL CIRCUIT LB UB UTRON TECHNOLOGY INC. 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919 2 P80086 UTRON UT62L51316(I) 512K X 16 BIT LOW POWER CMOS SRAM Preliminary Rev. 0.1 PIN CONFIGURATION A15 A14 A13 1 2 3 48 47 46 A12 A11 A10 A9 A8 NC NC WE CE2 NC 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 UB LB A18 A17 A7 A6 A5 A4 A3 A2 A1 UT62L51316(I) A16 NC Vss I/O16 I/O8 I/O15 I/O7 I/O14 I/O6 I/O13 I/O5 Vcc I/O12 I/O4 I/O11 I/O3 I/O10 I/O2 I/O9 I/O1 OE Vss A B C D E F G H CE A0 LB OE A0 A1 A2 CE2 I/O 9 UB A3 A4 CE I/O 1 I/O 1 0 I/O 1 1 A5 A6 I/O 2 I/O 3 V ss I/O 1 2 A17 A7 I/O 4 V cc V cc I/O 1 3 NC A16 I/O 5 V ss I/O 1 5 I/O 1 4 A14 A15 I/O 6 I/O 7 I/O 1 6 NC A12 A13 WE I/O 8 A18 A8 A9 A10 A11 NC 1 2 3 4 5 6 TFBGA TSOP-I PIN DESCRIPTION SYMBOL A0 - A18 I/O1 - I/O16 CE , CE2 DESCRIPTION Address Inputs Data Inputs/Outputs Chip Enable Input WE OE Write Enable Input LB UB VCC VSS NC Lower-byte Control Output Enable Input Upper-byte Control Power Supply Ground No Connection TRUTH TABLE MODE Standby Output Disable Read Write Note: CE CE2 OE WE LB UB H X X L L L L L L L L X L X H H H H H H H H X X X H H L L L X X X X X X H H H H H L L L X X H L X L H L L H L X X H X L H L L H L L I/O OPERATION I/O1-I/O8 I/O9-I/O16 High – Z High – Z High – Z High – Z High – Z High – Z High – Z High – Z High – Z High – Z DOUT High – Z DOUT High – Z DOUT DOUT High – Z DIN High – Z DIN DIN DIN SUPPLY CURRENT ISB, ISB1 ICC,ICC1, ICC2 ICC,ICC1, ICC2 ICC,ICC1, ICC2 H = VIH, L=VIL, X = Don't care. UTRON TECHNOLOGY INC. 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919 3 P80086 UTRON Preliminary Rev. 0.1 UT62L51316(I) 512K X 16 BIT LOW POWER CMOS SRAM ABSOLUTE MAXIMUM RATINGS* PARAMETER Terminal Voltage with Respect to VSS Operating Temperature Industrial Storage Temperature Power Dissipation DC Output Current Soldering Temperature (under 10 secs) SYMBOL VTERM TA TSTG PD IOUT Tsolder RATING -0.5 to 4.6 -40 to 85 -65 to 150 1 50 260 UNIT V ℃ ℃ W mA ℃ *Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to the absolute maximum rating conditions for extended period may affect device reliability. DC ELECTRICAL CHARACTERISTICS (Vcc = 2.7V~3.6V, TA = -40℃ to 85℃(I)) PARAMETER SYMBOL TEST CONDITION Power Voltage VCC *1 Input High Voltage VIH *2 Input Low Voltage VIL Input Leakage Current ILI VSS ≦VIN ≦VCC Output Leakage Current ILO VSS ≦VI/O ≦VCC; Output Disable Output High Voltage VOH IOH= -1mA Output Low Voltage VOL IOL= 2.1mA Cycle time=min, 100%duty 55 Operating Power 70 I/O=0mA, CE =VIL, CE2=VIH, ICC Supply Current 100 LB or UB =VIL Cycle time=1µs, 100% duty, II/O=0mA, ICC1 CE ≦0.2V,CE2≧VCC-0.2V, LB or UB ≦0.2V, Average Operation other pins at 0.2V or Vcc-0.2V Current Cycle time=500ns, 100% duty, II/O=0mA, ICC2 CE ≦0.2V,CE2≧VCC-0.2V, LB or UB ≦0.2V, other pins at 0.2V or Vcc-0.2V Standby Current (TTL) ISB CE =VIH, or CE2=VIL, or LB = UB =VIH -L CE ≧VCC-0.2V, or CE2≦0.2V, Standby Current (CMOS) ISB1 -LL or LB = UB =VCC-0.2V, MIN. TYP. MAX. 2.7 3.0 3.6 2.2 VCC+0.3 -0.2 0.6 -1 1 -1 1 2.2 2.7 0.4 30 40 20 30 16 25 UNIT V V V µA µA V V mA mA mA - 4 5 mA - 8 10 mA - 0.3 20 0.5 80 mA µA - 2 20 µA Notes: 1. Overshoot : Vcc+2.0v for pulse width less than 10ns. 2. Undershoot : Vss-2.0v for pulse width less than 10ns. 3. Overshoot and Undershoot are sampled, not 100% tested. UTRON TECHNOLOGY INC. 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919 4 P80086 UTRON UT62L51316(I) 512K X 16 BIT LOW POWER CMOS SRAM Preliminary Rev. 0.1 CAPACITANCE (TA=25℃, f=1.0MHz) PARAMETER Input Capacitance Input/Output Capacitance SYMBOL CIN CI/O MIN. MAX 6 8 - UNIT pF pF Note : These parameters are guaranteed by device characterization, but not production tested. AC TEST CONDITIONS 0.1VCC to 0.9VCC 5ns 1.5V CL = 30pF+1 TTL, IOH/IOL = -1mA/2.1mA Input Pulse Levels Input Rise and Fall Times Input and Output Timing Reference Levels Output Load AC ELECTRICAL CHARACTERISTICS (VCC = 2.7V~3.6V , TA = -40℃ to 85℃(I)) (1) READ CYCLE PARAMETER SYMBOL Read Cycle Time Address Access Time Chip Enable Access Time Output Enable Access Time Chip Enable to Output in Low Z Output Enable to Output in Low Z Chip Disable to Output in High Z Output Disable to Output in High Z Output Hold from Address Change tRC tAA tACE tOE tCLZ* tOLZ* tCHZ* tOHZ* tOH tBA tBHZ* tBLZ* LB , UB Access Time LB , UB to High-Z Output LB , UB to Low-Z Output UT62L51316(I)-55 MIN. MAX. 55 10 5 10 10 UT62L51316(I)-70 MIN. MAX. 55 55 30 20 20 55 20 - 70 10 5 10 10 70 70 35 25 25 70 25 - UT62L51316(I)-100 MIN. MAX. 100 10 5 10 10 100 100 50 30 30 100 30 - UNIT ns ns ns ns ns ns ns ns ns ns ns ns (2) WRITE CYCLE PARAMETER SYMBOL Write Cycle Time Address Valid to End of Write Chip Enable to End of Write Address Set-up Time Write Pulse Width Write Recovery Time Data to Write Time Overlap Data Hold from End of Write Time Output Active from End of Write Write to Output in High Z tWC tAW tCW tAS tWP tWR tDW tDH tOW* tWHZ* tBW UT62L51316(I)-55 MIN. MAX. 55 50 50 0 45 0 25 0 5 50 UT62L51316(I)-70 MIN. MAX. 20 - 70 60 60 0 55 0 30 0 5 60 LB , UB Valid to End of Write * These parameters are guaranteed by device characterization, but not production tested. UTRON TECHNOLOGY INC. 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919 5 25 - UT62L51316(I)-100 UNIT MIN. MAX. 100 80 80 0 70 0 40 0 5 80 30 - P80086 ns ns ns ns ns ns ns ns ns ns ns UTRON UT62L51316(I) 512K X 16 BIT LOW POWER CMOS SRAM Preliminary Rev. 0.1 TIMING WAVEFORMS READ CYCLE 1 (Address Controlled) (1,2) tRC Address tAA tOH Dout tOH Previous data valid Data Valid READ CYCLE 2 ( CE and CE2 and OE Controlled) (1,3,4,5) t RC Address tAA CE tACE CE2 tBA LB , UB t BHZ t BLZ OE t OE t CHZ t CLZ t OLZ Dout t OHZ t OH High-Z Data Valid High-Z Notes : 1. WE is high for read cycle. 2.Device is continuously selected OE =low, CE =low, CE2=high, LB or UB =low. 3.Address must be valid prior to or coincident with CE =low, CE2=high, LB or UB =low transition; otherwise tAA is the limiting parameter. 4.tCLZ, tBLZ, tOLZ, tCHZ, tBHZ and tOHZ are specified with CL=5pF. Transition is measured±500mV from steady state. 5.At any given temperature and voltage condition, tCHZ is less than tCLZ, tBHZ is less than tBLZ, tOHZ is less than tOLZ. UTRON TECHNOLOGY INC. 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919 6 P80086 UTRON UT62L51316(I) 512K X 16 BIT LOW POWER CMOS SRAM Preliminary Rev. 0.1 WRITE CYCLE 1 ( WE Controlled) (1,2,3,5,6) tW C Address t AW CE t CW CE2 t AS tW P tW R WE t BW LB , UB t W HZ t OW High-Z Dout (4) (4) t DW t DH Din Data Valid WRITE CYCLE 2 ( CE and CE2 Controlled) (1,2,5,6) tW C A ddress tA W CE tW R tA S tC W CE2 tW P WE tB W LB , U B tW H Z D out H igh-Z (4) tD W tD H D in D ata V alid UTRON TECHNOLOGY INC. 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919 7 P80086 UTRON UT62L51316(I) 512K X 16 BIT LOW POWER CMOS SRAM Preliminary Rev. 0.1 WRITE CYCLE 3 ( LB , UB Controlled) (1,2,5,6) tWC Address tAW CE tAS tCW tWR CE2 tWP WE tBW LB , UB tWHZ High-Z Dout tDW Din tDH Data Valid Notes : 1. WE , CE , LB , UB must be high or CE2 must be low during all address transitions. 2.A write occurs during the overlap of a low CE , high CE2, low WE , LB or UB =low. 3.During a WE controlled write cycle with OE low, tWP must be greater than tWHZ+tDW to allow the drivers to turn off and data to be placed on the bus. 4.During this period, I/O pins are in the output state, and input signals must not be applied. 5.If the CE , LB , UB low transition and CE2 high transition occurs simultaneously with or after WE low transition, the outputs remain in a high impedance state. 6.tOW and tWHZ are specified with CL = 5pF. Transition is measured ±500mV from steady state. UTRON TECHNOLOGY INC. 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919 8 P80086 UTRON UT62L51316(I) 512K X 16 BIT LOW POWER CMOS SRAM Preliminary Rev. 0.1 DATA RETENTION CHARACTERISTICS (TA = -40℃ to 85℃(I)) PARAMETER Vcc for Data Retention Data Retention Current Chip Disable to Data Retention Time Recovery Time SYMBOL TEST CONDITION VDR CE ≧VCC-0.2V or CE2≦0.2V or LB = UB ≧VCC-0.2V IDR Vcc=1.5V -L tCDR CE ≧VCC-0.2V, CE2≦0.2V, - LL LB = UB ≧VCC-0.2V See Data Retention Waveforms (below) tR MIN. 1.5 TYP. - MAX. 3.6 UNIT V - 10 80 - 1 8 µA µA 0 - - ns tRC* - - ns tRC* = Ready Cycle Time DATA RETENTION WAVEFORM Low Vcc Data Retention Waveform (1) ( CE controlled) VDR ≧ 1.5V VCC Vcc(min.) Vcc(min.) tCDR CE VIH tR CE ≧ VCC-0.2V VIH Low Vcc Data Retention Waveform (2) (CE2 controlled) VDR ≧ 1.5V VCC CE2 VCC(min.) VCC(min.) tCDR tR VIL CE2 ≦ 0.2V VIL Low Vcc Data Retention Waveform (3) ( LB , UB controlled) VDR ≧ 1.5V VCC Vcc(min.) Vcc(min.) tCDR LB,UB VIH tR LB,UB ≧ VCC-0.2V UTRON TECHNOLOGY INC. 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919 9 VIH P80086 UTRON Preliminary Rev. 0.1 UT62L51316(I) 512K X 16 BIT LOW POWER CMOS SRAM PACKAGE OUTLINE DIMENSION 48 pin 12mm x 20mm TSOP-I Package Outline Dimension UTRON TECHNOLOGY INC. 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919 10 P80086 UTRON Preliminary Rev. 0.1 UT62L51316(I) 512K X 16 BIT LOW POWER CMOS SRAM 48 ball 6.0mmX8.0mm TFBGA Package Outline Dimension UTRON TECHNOLOGY INC. 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919 11 P80086 UTRON UT62L51316(I) 512K X 16 BIT LOW POWER CMOS SRAM Preliminary Rev. 0.1 ORDERING INFORMATION INDUSTRIAL TEMPERATURE PART NO. UT62L51316BS-55LI UT62L51316BS-55LLI UT62L51316BS-70LI UT62L51316BS-70LLI UT62L51316BS-100LI UT62L51316BS-100LLI UT62L51316LC-55LI UT62L51316LC-55LLI UT62L51316LC-70LI UT62L51316LC-70LLI UT62L51316LC-100LI UT62L51316LC-100LLI ACCESS TIME ( ns ) 55 55 70 70 100 100 55 55 70 70 100 100 STANDBY CURRENT ( µA ) typ. 20 2 20 2 20 2 20 2 20 2 20 2 UTRON TECHNOLOGY INC. 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919 12 PACKAGE 48 BALL TFBGA 48 BALL TFBGA 48 BALL TFBGA 48 BALL TFBGA 48 BALL TFBGA 48 BALL TFBGA 48 PIN TSOP-I 48 PIN TSOP-I 48 PIN TSOP-I 48 PIN TSOP-I 48 PIN TSOP-I 48 PIN TSOP-I P80086 UTRON Preliminary Rev. 0.1 UT62L51316(I) 512K X 16 BIT LOW POWER CMOS SRAM THIS PAGE IS LEFT BLANK INTENTIONALLY. UTRON TECHNOLOGY INC. 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919 13 P80086