UTRON UT62256C(E) 32K X 8 BIT LOW POWER CMOS SRAM Rev. 1.0 REVISION HISTORY REVISION Rev. 1.0 DESCRIPTION Original. UTRON TECHNOLOGY INC. 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919 1 DATE Sep 3 ,2001 P80071 UTRON UT62256C(E) 32K X 8 BIT LOW POWER CMOS SRAM Rev. 1.0 FEATURES GENERAL DESCRIPTION The UT62256C(E) is a 262,144-bit low power CMOS static random access memory organized as 32,768 words by 8 bits. It is fabricated using high performance, high reliability CMOS technology. Access time : 35/70ns (max.) Low power consumption: Operating : 40/30 mA (typical.) Standby : 2uA (typ.) L-version 1uA (typ.) LL-version Single 5V power supply Extended temperature : -20℃~80℃ All inputs and outputs are TTL compatible Fully static operation Three state outputs Data retention voltage : 2V (min.) Package : 28-pin 600 mil PDIP 28-pin 330 mil SOP 28-pin 8mmx13.4mm STSOP The UT62256C(E) is designed for high-speed and low power application. It is particularly well suited for battery back-up nonvolatile memory application. The UT62256C(E) operates from a single 5V power supply and all inputs and outputs are fully TTL compatible PIN CONFIGURATION FUNCTIONAL BLOCK DIAGRAM A0-A14 DECODER Vcc Vss I/O1-I/O8 I/O DATA CIRCUIT COLUMN I/O CONTROL CIRCUIT OE PIN DESCRIPTION SYMBOL A0 - A14 I/O1 - I/O8 CE WE OE VCC VSS 28 Vcc 2 27 WE A7 3 26 A13 A6 4 25 A8 A5 5 24 A9 A4 6 23 A11 A3 7 A2 8 A1 9 A0 10 22 OE 21 A10 20 CE 19 I/O8 I/O1 11 18 I/O7 I/O2 12 17 I/O6 I/O3 13 16 I/O5 Vss 14 15 I/O4 PDIP/SOP CE WE 1 A12 UT62256C 32K × 8 MEMORY ARRAY A14 DESCRIPTION Address Inputs Data Inputs/Outputs Chip Enable Input Write Enable Input Output Enable Input Power Supply Ground 1 28 2 27 CE A9 3 26 I/O8 A8 4 25 I/O7 A13 5 24 I/O6 WE 6 23 I/O5 Vcc 7 22 I/O4 A14 8 21 Vss A12 9 20 I/O3 A7 10 19 I/O2 A6 11 18 I/O1 A5 12 17 A0 A4 13 16 A1 A3 14 15 A2 UT62256C STSOP UTRON TECHNOLOGY INC. 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919 2 A10 OE A11 P80071 UTRON UT62256C(E) 32K X 8 BIT LOW POWER CMOS SRAM Rev. 1.0 ABSOLUTE MAXIMUM RATINGS* PARAMETER Terminal Voltage with Respect to VSS Operating Temperature Storage Temperature Power Dissipation DC Output Current Soldering Temperature (under 10 secs) SYMBOL VTERM TA TSTG PD IOUT Tsolder RATING -0.5 to +7.0 0 to +70 -65 to +150 1 50 260 UNIT V ℃ ℃ W mA ℃ *Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to the absolute maximum rating conditions for extended period may affect device reliability. TRUTH TABLE MODE CE H L L L Standby Output Disable Read Write Note: OE X H L X WE X H H L I/O OPERATION SUPPLY CURRENT High - Z High - Z DOUT DIN ISB, ISB1 ICC, ICC1, ICC2 ICC, ICC1, ICC2 ICC, ICC1, ICC2 H = VIH, L=VIL, X = Don't care. DC ELECTRICAL CHARACTERISTICS (VCC = 5V±10%, TA = -20℃~80℃) PARAMETER Input High Voltage Input Low Voltage Input Leakage Current Output Leakage Current Output High Voltage Output Low Voltage Operating Power Supply Current SYMBOL TEST CONDITION VIH VIL ILI ILO VOH VOL ICC ICC1 ICC2 Standby Current(TTL) ISB Standby Current(CMOS) ISB1 VSS ≦VIN ≦VCC VSS ≦VI/O ≦VCC CE =VIH or OE = VIH or WE = VIL IOH= - 1mA IOL= 4mA Cycle time=Min - 35 - 70 CE = VIL ,II/O = 0mA ,. Cycle time=1µs, CE =0.2V; II/O=0mA, other pins at 0.2V or VCC-0.2V Cycle time=500ns, CE =0.2V;II/O=0mA, other pins at 0.2V or VCC-0.2V CE =VIH -L CE ≧VCC-0.2V -LL MIN. 2.2 - 0.5 -1 -1 TYP. MAX. VCC+0.5 0.8 1 1 UNIT V V µA µA 2.4 - 40 30 - 0.4 50 40 10 V V mA mA mA - - 20 mA - - 3 mA 2 100 1 50 µA µA - Notes: 1. Overshoot : Vcc+2.0v for pulse width less than 10ns. 2. Undershoot : Vss-2.0v for pulse width less than 10ns. 3. Overshoot and Undershoot are sampled, not 100% tested. UTRON TECHNOLOGY INC. 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919 3 P80071 UTRON UT62256C(E) 32K X 8 BIT LOW POWER CMOS SRAM Rev. 1.0 CAPACITANCE (TA=25℃, f=1.0MHz) PARAMETER Input Capacitance Input/Output Capacitance SYMBOL CIN CI/O MIN. MAX 8 10 - UNIT pF pF Note : These parameters are guaranteed by device characterization, but not production tested. AC TEST CONDITIONS Input Pulse Levels Input Rise and Fall Times Input and Output Timing Reference Levels Output Load 0V to 3.0V 5ns 1.5V CL = 100pF, IOH/IOL = -1mA/4mA AC ELECTRICAL CHARACTERISTICS (VCC = 5V±10% , TA = -20℃~80℃) (1) READ CYCLE PARAMETER Read Cycle Time Address Access Time Chip Enable Access Time Output Enable Access Time Chip Enable to Output in Low Z Output Enable to Output in Low Z Chip Disable to Output in High Z Output Disable to Output in High Z Output Hold from Address Change (2) WRITE CYCLE PARAMETER Write Cycle Time Address Valid to End of Write Chip Enable to End of Write Address Set-up Time Write Pulse Width Write Recovery Time Data to Write Time Overlap Data Hold from End of Write Time Output Active from End of Write Write to Output in High Z SYMBOL UT62256C(E)-35 tRC tAA tACE tOE tCLZ* tOLZ* tCHZ* tOHZ* tOH SYMBOL MAX. MIN. MAX. 35 10 5 5 35 35 25 25 25 - 70 10 5 5 70 70 35 35 35 - UT62256C(E)-35 tWC tAW tCW tAS tWP tWR tDW tDH tOW* tWHZ* UT62256C(E)-70 MIN. UT62256C(E)-70 MIN. MAX. MIN. MAX. 35 30 30 0 25 0 20 0 5 - 15 70 60 60 0 50 0 30 0 5 - 25 *These parameters are guaranteed by device characterization, but not production tested. UTRON TECHNOLOGY INC. 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919 4 P80071 UNIT ns ns ns ns ns ns ns ns ns UNIT ns ns ns ns ns ns ns ns ns ns UTRON UT62256C(E) 32K X 8 BIT LOW POWER CMOS SRAM Rev. 1.0 TIMING WAVEFORMS READ CYCLE 1 (Address Controlled) (1,2) tRC Address tAA tOH Dout tOH Previous data valid Data Valid READ CYCLE 2 ( CE and OE Controlled) (1,3,4,5) t RC Address tAA CE tACE OE tCHZ tOE tOHZ tCLZ tOLZ Dout t OH High-Z Data Valid High-Z Notes : 1. WE is high for read cycle. 2.Device is continuously selected OE =low, CE =low. 3.Address must be valid prior to or coincident with CE =low,; otherwise tAA is the limiting parameter. 4.tCLZ, tOLZ, tCHZ and tOHZ are specified with CL=5pF. Transition is measured±500mV from steady state. 5.At any given temperature and voltage condition, tCHZ is less than tCLZ is less than tOHZ is less than tOLZ. UTRON TECHNOLOGY INC. 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919 5 P80071 UTRON UT62256C(E) 32K X 8 BIT LOW POWER CMOS SRAM Rev. 1.0 WRITE CYCLE 1 ( WE Controlled) (1,2,3,5,6) tW C Address tAW CE t CW t AS tW P tW R WE t W HZ Dout tOW High-Z (4) (4) tDW Din t DH Data Valid WRITE CYCLE 2 ( CE Controlled) (1,2,5,6) tW C A ddress tA W CE tW R tA S tC W tW P WE tW H Z D out H igh-Z (4) tD W D in tD H D ata V alid UTRON TECHNOLOGY INC. 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919 6 P80071 UTRON UT62256C(E) 32K X 8 BIT LOW POWER CMOS SRAM Rev. 1.0 Notes : 1. WE , CE must be high during all address transitions. 2.A write occurs during the overlap of a low CE , low WE . 3. During a WE controlled write cycle with OE low, tWP must be greater than tWHZ+tDW to allow the drivers to turn off and data to be placed on the bus. 4.During this period, I/O pins are in the output state, and input signals must not be applied. 5. If the CE low transition occurs simultaneously with or after WE low transition, the outputs remain in a high impedance state. 6.tOW and tWHZ are specified with CL = 5pF. Transition is measured ±500mV from steady state. DATA RETENTION CHARACTERISTICS (TA = -20℃~80℃) PARAMETER Vcc for Data Retention SYMBOL VDR Data Retention Current IDR Chip Disable to Data Retention Time Recovery Time tCDR TEST CONDITION CE ≧ VCC-0.2V Vcc=3V CE ≧ VCC-0.2V See Data Retention Waveforms (below) -L - LL tR MIN. 2.0 TYP. - MAX. 5.5 UNIT V - 1 0.5 50 20 0 - - µA µA ns tRC* - - ns tRC* = Read Cycle Time DATA RETENTION WAVEFORM Low Vcc Data Retention Waveform ( CE controlled) V D R ≧ 2V VCC V cc(m in.) V cc(m in.) tC D R CE V IH tR C E ≧ V C C -0.2V UTRON TECHNOLOGY INC. 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919 7 V IH P80071 UTRON UT62256C(E) 32K X 8 BIT LOW POWER CMOS SRAM Rev. 1.0 PACKAGE OUTLINE DIMENSION 28 pin 600 mil PDIP PACKAGE OUTLINE DIMENSION UNIT SYMBOL A A1 D E E1 eB Θ INCH(MIN) 0.015 1.455 0.6 0.54 0.63 o 0 INCH(MAX) 0.220 1.47 0.6 0.54 0.67 o 15 UTRON TECHNOLOGY INC. 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919 8 P80071 UTRON UT62256C(E) 32K X 8 BIT LOW POWER CMOS SRAM Rev. 1.0 28 pin 330 mil SOP PACKAGE OUTLINE DIMENSION UNIT SYMBOL A A1 A2 b c D E E1 e L L1 S y Θ INCH(BASE) 0.120 (MAX) 0.002(MIN) 0.098±0.005 0.0016 (TYP) 0.010 (TYP) 0.728 (MAX) 0.340 (MAX) 0.465±0.012 0.050 (TYP) 0.05 (MAX) 0.067±0.008 0.047 (MAX) 0.003(MAX) o o 0 ∼10 MM(REF) 3.048 (MAX) 0.05(MIN) 2.489±0.127 0.406(TYP) 0.254(TYP) 18.491 (MAX) 8.636 (MAX) 11.811±0.305 1.270(TYP) 1.270 (MAX) 1.702 ±0.203 1.194 (MAX) 0.076(MAX) o o 0 ∼10 UTRON TECHNOLOGY INC. 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919 9 P80071 UTRON UT62256C(E) 32K X 8 BIT LOW POWER CMOS SRAM Rev. 1.0 28 pin 8x13.4mm STSOP PACKAGE OUTLINE DIMENSION HD cL 28 14 15 E e 1 "A" y Seating Plane D 14 A2 c A 15 A1 0 1 28 UNIT SYMBOL A A1 A2 D E e HD L1 y Θ SEATING PLANE "A" DATAIL VIEW L1 INCH(BASE) MM(REF) 0.047 (MAX) 0.004 ±0.002 0.039 ±0.002 0.465 ±0.004 0.315 ±0.004 0.022 (TYP) 0.528 ±0.008 0.0315 ±0.004 0.003 (MAX) o o 0 ∼5 1.20 (MAX) 0.10 ±0.05 1.00 ±0.05 11.800 ±0.100 8.000 ±0.100 0.55 (TYP) 13.40 ±0.20. 0.80 ±0.10 0.076 (MAX) o o 0 ∼5 UTRON TECHNOLOGY INC. 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919 10 P80071 UTRON UT62256C(E) 32K X 8 BIT LOW POWER CMOS SRAM Rev. 1.0 ORDERING INFORMATION PART NO. UT62256CPC-70E UT62256CPC-70LE UT62256CPC-70LLE UT62256CSC-35E UT62256CSC-35LE UT62256CSC-35LLE UT62256CSC-70E UT62256CSC-70LE UT62256CSC-70LLE UT62256CLS-35LE UT62256CLS-35LLE UT62256CLS-70LE UT62256CLS-70LLE ACCESS TIME (ns) 70 70 70 35 35 35 70 70 70 35 35 70 70 STANDBY CURRENT (µA) 5 mA 100 µA 40 µA 5 mA 100 µA 40 µA 5 mA 100 µA 40 µA 100 µA 50 µA 100 µA 40 µA UTRON TECHNOLOGY INC. 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919 11 PACKAGE 28PIN PDIP 28PIN PDIP 28PIN PDIP 28PIN SOP 28PIN SOP 28PIN SOP 28PIN SOP 28PIN SOP 28PIN SOP 28PIN STSOP 28PIN STSOP 28PIN STSOP 28PIN STSOP P80071 UTRON Rev. 1.0 UT62256C(E) 32K X 8 BIT LOW POWER CMOS SRAM THIS PAGE IS LEFT BLANK INTENTIONALLY. UTRON TECHNOLOGY INC. 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919 12 P80071