UTRON UT62L1024 128K X 8 BIT LOW POWER CMOS SRAM Rev. 1.7 FEATURES GENERAL DESCRIPTION Access time : 35/55/70ns (max.) Low power consumption : Operating : 40/35/30 mA (typical) Standby : 2.5µA (typical) L-version 0.5µA (typical) LL-version Power supply range : 2.7V to 3.6V All inputs and outputs TTL compatible Fully static operation Three state outputs Data retention voltage : 2V (min.) Package : 32-pin 600 mil PDIP 32-pin 450 mil SOP 32-pin 8x20 mm TSOP-1 32-pin 8x13.4 mm STSOP The UT62L1024 is a 1,048,576-bit low power CMOS static random access memory organized as 131,072 words by 8 bits. It is fabricated using high performance, high reliability CMOS technology. Easy memory expansion is provided by using two chip enable input.( CE 1 ,CE2) It is particularly well suited for battery back-up nonvolatile memory application. The UT62L1024 operates from a single 2.7V~ 3.6V power supply and all inputs and outputs are fully TTL compatible. FUNCTIONAL BLOCK DIAGRAM A0-A16 DECODER 2048 × 512 MEMORY ARRAY I/O DATA CIRCUIT COLUMN I/O Vcc Vss I/O1-I/O8 CE1 CE2 OE CONTROL CIRCUIT WE UTRON TECHNOLOGY INC. 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919 1 P80033 UTRON UT62L1024 128K X 8 BIT LOW POWER CMOS SRAM Rev. 1.7 PIN CONFIGURATION 1 32 Vcc A11 1 32 31 A15 OE 2 A9 2 31 A10 A14 3 30 CE2 A8 3 30 CE1 A12 4 29 WE A13 4 29 I/O8 A7 5 A6 6 A5 7 A4 A3 8 9 A2 10 A1 11 A0 I/O1 I/O2 I/O3 Vss UT62L1024 NC A16 12 13 14 28 A13 WE 5 28 I/O7 27 A8 CE2 6 27 I/O6 26 A9 A15 7 26 I/O5 A11 Vcc 8 25 I/O4 NC 9 A16 25 24 OE 23 A10 22 CE1 21 20 19 I/O8 I/O7 I/O6 15 18 I/O5 16 17 I/O4 UT62L1024 24 Vss 10 23 I/O3 A14 11 22 I/O2 A12 12 21 I/O1 A7 13 20 A0 A6 14 19 A1 A5 15 18 A2 A4 16 17 A3 PDIP / SOP TSOP-I/STSOP PIN DESCRIPTION SYMBOL A0 - A16 I/O1 - I/O8 CE 1 ,CE2 DESCRIPTION Address Inputs Data Inputs/Outputs Chip enable 1,2 Inputs WE Write Enable Input OE VCC VSS NC Output Enable Input Power Supply Ground No Connection UTRON TECHNOLOGY INC. 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919 2 P80033 UTRON UT62L1024 128K X 8 BIT LOW POWER CMOS SRAM Rev. 1.7 ABSOLUTE MAXIMUM RATINGS* PARAMETER Terminal Voltage with Respect to Vss Operating Temperature Storage Temperature Power Dissipation DC Output Current Soldering Temperature (under 10 sec) SYMBOL VTERM TA TSTG PD IOUT Tsolder RATING -0.5 to +4.6 0 to +70 -65 to +150 1 50 260 UNIT V ℃ ℃ W mA ℃ *Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to the absolute maximum rating conditions for extended period may affect device reliability. TRUTH TABLE MODE Standby Standby Output Disable Read Write CE2 X L H H H CE1 H X L L L OE X X H L X WE X X H H L I/O OPERATION SUPPLY CURRENT High - Z High -Z High - Z DOUT DIN ISB,ISB1 ISB,ISB1 ICC , ICC1 ICC , ICC1 ICC , ICC1 Note: H = VIH, L=VIL, X = Don't care. DC ELECTRICAL CHARACTERISTICS (VCC = 2.7V~3.6V, Ta = 0℃ to +70℃) PARAMETER SYMBOL TEST CONDITION Input High Voltage VIH Input Low Voltage VIL Input Leakage Current IIL VSS ≦VIN ≦VCC Output Leakage Current IOL VSS ≦VI/O≦VCC CE 1 =VIH or CE2 = VIL or Output High Voltage Output Low Voltage Average Operating Power Supply Courrent VOH VOL ICC ICC1 Standby Power Supply Current ISB ISB1 OE = VIH or WE = VIL IOH = - 1mA IOL= 4mA Cycle time =Min. 100% Duty, CE 1 =VIL, CE2 = VIH, II/O = 0mA MIN. TYP. MAX. UNIT 2.0 VCC+0.5 V - 0.5 0.6 V -1 1 µA -1 - 1 µA 2.2 - 40 35 30 0.4 60 50 40 V V mA mA mA - - 5 mA - - mA -L - 2.5 LL - 0.5 1.0 100 20* 40 10* 35 55 70 Cycle time = 1µs, 100% Duty, . CE 1 ≦0.2V,CE2≧VCC-0.2V, II/O = 0mA CE 1 =VIH or CE2 = VIL CE 1 ≧VCC-0.2V or .CE2≦0.2V µA µA *Those parameters are for reference only under 50℃ UTRON TECHNOLOGY INC. 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919 3 P80033 UTRON UT62L1024 128K X 8 BIT LOW POWER CMOS SRAM Rev. 1.7 CAPACITANCE (Ta=25℃, f=1.0MHz) PARAMETER Input Capacitance Input/Output Capacitance SYMBOL CIN CI/O MIN. MAX. 6 8 - UNIT pF pF Note : These parameters are guaranteed by device characterization, but not production tested. AC TEST CONDITIONS Input Pulse Levels Input Rise and Fall Times Input and Output Timing Reference Levels Output Load 0.4V to 2.4V 5ns 1.5V CL=50pF, IOH/IOL=-1mA/2mA AC ELECTRICAL CHARACTERISTICS (VCC = 2.7V~3.6V , Ta = 0℃ to +70℃) (1) READ CYCLE PARAMETER SYMBOL UT62L1024-35 UT62L1024-55 UT62L1024-70 UNIT MIN. MAX. MIN. MAX. MIN. MAX. Read Cycle Time tRC 35 55 70 ns Address Access Time tAA 35 55 70 ns Chip Enable Access Time tACE1, tACE2 35 55 70 ns Output Enable Access Time tOE 25 30 35 ns Chip Enable to Output in Low-Z tCLZ1*, tCLZ2* 10 10 10 ns Output Enable to Output in Low-Z tOLZ* 5 5 5 ns Chip Disable to Output in High-Z tCHZ1*, tCHZ2* 25 30 35 ns Output Disable to Output in High-Z tOHZ* 25 30 35 ns Output Hold from Address Change tOH 5 5 5 ns (2) WRITE CYCLE PARAMETER Write Cycle Time Address Valid to End of Write Chip Enable to End of Write Address Set-up Time Write Pulse Width Write Recovery Time Data to Write Time Overlap Data Hold from End of Write-Time Output Active from End of Write Write to Output in High-Z SYMBOL UT62L1024-35 UT62L1024-55 UT62L1024-70 tWC tAW tCW1, tCW2 tAS tWP tWR tDW tDH tOW* tWHZ* MIN. 35 30 30 0 25 0 20 0 5 - MAX. 15 MIN. 55 50 50 0 40 0 25 0 5 - MAX. MIN. 70 60 60 0 45 0 30 0 5 20 - MAX. 25 UNIT ns ns ns ns ns ns ns ns ns ns *These parameters are guaranteed by device characterization, but not production tested. UTRON TECHNOLOGY INC. 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919 4 P80033 UTRON UT62L1024 128K X 8 BIT LOW POWER CMOS SRAM Rev. 1.7 TIMING WAVEFORMS READ CYCLE 1 (Address Controlled) (1,2,4) tRC Address tAA tOH tOH DOUT Data Valid READ CYCLE 2 ( CE1 , CE2 and OE Controlled) (1,3,5,6) t RC Address t AA t ACE1 CE1 CE2 t ACE2 OE t CLZ1 t CLZ2 Dout HIGH-Z t CHZ1 t CHZ2 t OE t OH t OLZ t OHZ HIGH-Z Data Valid Notes : 1. WE is HIGH for a read cycle. 2. Device is continuously selected OE , CE 1 =VIL and CE2=VIH. 3. Address must be valid prior to or coincident with CE 1 4. low and CE2 high transition; otherwise tAA is the limiting parameter. OE is low. 5. tCLZ1, tCLZ2, tOLZ, tCHZ1, tCHZ2 and tOHZ are specified with CL=5pF. Transition is measured ± 500mV from steady state. 6. At any given temperature and voltage condition, tCHZ1 is less than tCLZ1, tCHZ2 is less than tCLZ2, tOHZ is less than tOLZ. UTRON TECHNOLOGY INC. 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919 5 P80033 UTRON UT62L1024 128K X 8 BIT LOW POWER CMOS SRAM Rev. 1.7 WRITE CYCLE 1 ( WE Controlled) (1,2,3,5) t WC Address t AW CE1 t CW1 CE2 t CW2 t AS t WR t WP WE t WHZ Dout t OW High-Z (4) t DW Din t DH (4) Data Valid WRITE CYCLE 2 ( CE 1 and CE2 Controlled) (1,2,5) t WC Address t AW CE1 t AS t CW1 t WR t CW2 CE2 t WP WE t WHZ High-Z Dout t DH t DW Din Data Valid Notes : 1. WE or CE 1 must be HIGH or CE2 must be LOW during all address transitions. 2. A write occurs during the overlap of a low CE 1 , a high CE2 and a low WE . 3. During a WE controlled with write cycle with OE LOW, tWP must be greater than tWHZ+tDW to allow the I/O drivers to turn off and data to be placed on the bus. 4. During this period, I/O pins are in the output state, and input singals must not be applied. 4. If the CE 1 LOW transition occurs simultaneously with or after WE LOW transition, the outputs remain in a high Impedance state. 6. tOW and tWHZ are specified with CL=5pF. Transition is measured ± 500mV from steady state. UTRON TECHNOLOGY INC. 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919 6 P80033 UTRON UT62L1024 128K X 8 BIT LOW POWER CMOS SRAM Rev. 1.7 DATA RETENTION CHARACTERISTICS (Ta = 0℃ to +70℃) PARAMETER Vcc for Data Retention Data Retention Current SYMBOL TEST CONDITION VDR CE 1 ≧ VCC-0.2V or CE2 ≤ 0.2V IDR Vcc=2V Chip Disable to Data Retention Time Recovery Time tCDR CE 1 ≧ VCC-0.2V or CE2 ≤ 0.2V See Data Retention Waveforms (below) MIN. TYP. MAX. 2.0 3.3 -L - - LL - tR 0 - 40 20* 20 5* - tRC* - - 1 0.5 UNIT V µA µA ns ns tRC* = Read Cycle Time *Those parameters are for reference only under 50℃ DATA RETENTION WAVEFORM Date Retention Mode VCC 2.7V 2.7V VDR ≧ 2.0V CE1 tCDR tR VIH VSS VIH CE1 ≧ VCC -0.2V CE2 VIL CE2 ≤ 0.2V UTRON TECHNOLOGY INC. 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919 7 VIL P80033 UTRON UT62L1024 128K X 8 BIT LOW POWER CMOS SRAM Rev. 1.7 PACKAGE OUTLINE DIMENSION 32 pin 600 mil PDIP Package Outline Dimension UNIT SYMBOL A A A1 A2 B B1 c D E E1 e eB L S Q1 INCH(BASE) 0.010 (MIN) 0.150 ± 0.005 0.018 ± 0.005 0.050 ± 0.005 0.010 ± 0.004 1.650 ± 0.005 0.600 ± 0.010 0.544 ± 0.004 0.100 (TYP) 0.640± 0.020 0.130 ± 0.010 0.075 ± 0.010 0.070 ± 0.005 MM(REF) 0.254 (MIN) 3.810 ± 0.127 0.457± 0.127 1.270± 0.127 0.254± 0.102 41.910 ± 0.127 15.240 ± 0.254 13.818 ± 0.102 2.540 (TYP) 16.256 ± 0.508 3.302 ± 0.254 1.905 ± 0.254 1.778 ± 0.127 Note: 1. D/E1/S DIMENSION DO NOT INCLUDE MOLD FLASH. UTRON TECHNOLOGY INC. 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919 8 P80033 UTRON UT62L1024 128K X 8 BIT LOW POWER CMOS SRAM Rev. 1.7 32 pin 450mil SOP Package Outline Dimension UNIT SYMBOL A A C A A1 A2 b c D E E1 e L L1 S y Θ INCH(BASE) 0.118 (MAX) 0.004(MIN) 0.111(MAX) 0.016(TYP) 0.008(TYP) 0.817(MAX) 0.445 ± 0.005 0.555 ± 0.012 0.050(TYP) 0.0347 ± 0.008 0.055 ± 0.008 0.026(MAX) 0.004(MAX) o o 0 -10 MM(REF) 2.997 (MAX) 0.102(MIN) 2.82(MAX) 0.406(TYP) 0.203(TYP) 20.75(MAX) 11.303 ± 0.127 14.097 ± 0.305 1.270(TYP) 0.881 ± 0.203 1.397 ± 0.203 0.066 (MAX) 0.101(MAX) o o 0 -10 UTRON TECHNOLOGY INC. 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919 9 P80033 UTRON UT62L1024 128K X 8 BIT LOW POWER CMOS SRAM Rev. 1.7 32 pin TSOP-I Package Outline Dimension UNIT SYMBOL E C A A1 A2 C b H B c D E e HD L L1 y Θ INCH(BASE) MM(REF) 0.047 (MAX) 0.004 ± 0.002 0.039 ± 0.002 0.008 + 0.002 - 0.001 0.005 (TYP) 0.724 ± 0.004 0.315 ± 0.004 0.020 (TYP) 0.787 ± 0.008 0.0197 ± 0.004 0.0315 ± 0.004 0.003 (MAX) o o 0 〜5 1.20 (MAX) 0.10 ± 0.05 1.00 ± 0.05 0.20 + 0.05 -0.03 0.127 (TYP) 18.40 ± 0.10 8.00 ± 0.10 0.50 (TYP) 20.00 ± 0.20 0.50 ± 0.10 0.08 ± 0.10 0.076 (MAX) o o 0 〜5 UTRON TECHNOLOGY INC. 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919 10 P80033 UTRON UT62L1024 128K X 8 BIT LOW POWER CMOS SRAM Rev. 1.7 32 pin 8mm x 13.4mm STSOP Package Outline Dimension HD cL 12° (2x) 16 17 12° (2x) b E e 1 32 "A" Seating Plane D y 12° (2X) 16 17 0.254 A2 c A GAUGE PLANE A1 0 SEATING PLANE "A" DATAIL VIEW 1 L 12° (2X) L1 32 UNIT SYMBOL c A A1 A2 b c D E e HD L L1 y Θ INCH(BASE) MM(REF) 0.049 (MAX) 1.25 (MAX) 0.005 ± 0.002 0.130 ± 0.05 0.039 ± 0.002 1.00 ± 0.05 ± 0.008 0.01 0.20± 0.025 0.005 (TYP) 0.127 (TYP) 0.465 ± 0.004 11.80 ± 0.10 0.315 ± 0.004 8.00 ± 0.10 0.020 (TYP) 0.50 (TYP) 0.528± 0.008 13.40 ± 0.20. 0.0197 ± 0.004 0.50 ± 0.10 0.0315 ± 0.004 0.8 ± 0.10 0.003 (MAX) 0.076 (MAX) o o o o 0 〜5 0 〜5 UTRON TECHNOLOGY INC. 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919 11 P80033 UTRON UT62L1024 128K X 8 BIT LOW POWER CMOS SRAM Rev. 1.7 ORDERING INFORMATION PART NO. UT62L1024PC-35L UT62L1024PC-35LL UT62L1024PC-55L UT62L1024PC-55LL UT62L1024PC-70L UT62L1024PC-70LL UT62L1024SC-35L UT62L1024SC-35LL UT62L1024SC-55L UT62L1024SC-55LL UT62L1024SC-70L UT62L1024SC-70LL UT62L1024LC-35L UT62L1024LC-35LL UT62L1024LC-55L UT62L1024LC-55LL UT62L1024LC-70L UT62L1024LC-70LL UT62L1024LS-35L UT62L1024LS-35LL UT62L1024LS-55L UT62L1024LS-55LL UT62L1024LS-70L UT62L1024LS-70LL ACCESS TIME (ns) 35 35 55 55 70 70 35 35 55 55 70 70 35 35 55 55 70 70 35 35 55 55 70 70 STANDBY CURRENT (µA) (max) Ta = 50℃ 20 10 20 10 20 10 20 10 20 10 20 10 20 10 20 10 20 10 20 10 20 10 20 10 UTRON TECHNOLOGY INC. 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919 12 PACKAGE 32 PIN PDIP 32 PIN PDIP 32 PIN PDIP 32 PIN PDIP 32 PIN PDIP 32 PIN PDIP 32 PIN SOP 32 PIN SOP 32 PIN SOP 32 PIN SOP 32 PIN SOP 32 PIN SOP 32 PIN TSOP-I 32 PIN TSOP-I 32 PIN TSOP-I 32 PIN TSOP-I 32 PIN TSOP-I 32 PIN TSOP-I 32 PIN STSOP 32 PIN STSOP 32 PIN STSOP 32 PIN STSOP 32 PIN STSOP 32 PIN STSOP P80033 UTRON UT62L1024 128K X 8 BIT LOW POWER CMOS SRAM Rev. 1.7 REVISION HISTORY REVISION Rev. 1.0 Rev. 1.1 Rev. 1.2 Rev. 1.3 Rev. 1.4 Rev. 1.5 Rev. 1.6 Rev. 1.7 DESCRIPTION Original. 128Kx 8 Low Voltage CMOS SRAM 之TN8106 body 已作fine tunings,將ISB1降為0.5uA(LL)、2uA(L)、Vcc range：3.0V~3.6V Add STSOP-I Package Modify the format of power consumption Add speed : -55ns Vcc min 3.1→2.7V 1. The symbols CE1# ,OE# & WE# are revised as CE1 , OE & WE . 2. Add Icc value of 55ns range(access time) . 3. VOH is revised as 2.2V. 4. ISB1 is revised as 100µs. Revised 32 pin 8mmx13.4mm STSOP Package Outline Dimension. UTRON TECHNOLOGY INC. 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919 13 DATE Jun. 01. 1997 Apr. 05. 2000 Aug. 29. 2000 Sep. 01. 2000 Dec. 01. 2000 Mar. 15. 2001 Jun. 26. 2001 Nov. 26. 2001 P80033 UTRON Rev. 1.7 UT62L1024 128K X 8 BIT LOW POWER CMOS SRAM THIS PAGE IS LEFT BLANK INTENTIONALLY. UTRON TECHNOLOGY INC. 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919 14 P80033