Lr Data Sheet Merlin™ Fibre Channel Core Family Overview The Merlin™ Fibre Channel Core Family is a second generation of the field proven Fibre Channel protocol controller architecture. Available in three basic configurations, Merlin™ is a cost-effective Fibre Channel protocol controller, which delivers the highest available Fibre Channel data rate to a wide range of Storage Area Network (SAN) applications. Merlin’s flexible architecture enables designers to choose only the Fibre Channel features they need, reducing cost in price-sensitive applications while preserving performance in performance-critical applications. Combined with other LSI Logic CoreWare cores and customer-specific logic blocks, designers can create high-performance, single-chip disk controllers, tape controllers, RAID disk array controllers, intelligent hubs, switches and Fibre Channel host adapters. Merlin Disk Controller Replaces two-host bus adapter cards with a single chip in dual port applications l Increases loop access and reliability l Enables designers to develop fully customizable Fibre Channel solutions while maintaining interoperability Offers the lowest overhead class of service Buffers tuned to each customer’s price/ performance requirements On-chip exchange management tuned to each customer’s price/performance requirements Key features can be tuned to meet exact customer requirements Reduces initialization latency Supports multiple concurrent exchanges Highly automated FCP SCSI operations reduces the need for processor intervention On-chip data is parity-protected at all times Simplifies code and hardware development through access to core internal resources Integrates smoothly with other CoreWare cores to enable complex designs while reducing time to market l The Merlin™ Fibre Channel Core Family complies with the ANSI Fibre Channel Standard (FC-PH) providing Class 3 service and supports the newly adopted Fibre Channel Arbitrated Loop-2 (FC-AL2) Standard, the Fibre Channel protocol for SCSI (FCP), the Private Loop Direct Attach (PLDA) Profile and the Fabric Loop Attach Profile (FLA). l l Benefits l l l l l l Meets all ANSI X3T.11 Fibre Channel Standard requirements for Class 3 Arbitrated Loop-2 operation Meets all Fibre Channel Profile requirements for transporting SCSI over both private and public loops End-product interoperability success using a proven design architecture Delivers the highest available Fibre Channel data rate to your applications Transmits and Receives simultaneously at the full Fibre Channel data rate (2 X 100 MB/s) Offers the lowest-cost Fibre Channel topology l Enables cost-effective single port controllers l l l l l l l l Features l l l l l l l l l l l l l l l l ANSI Fibre Channel standard compliance: l FC-PH l FC-AL2 ANSI Fibre Channel profile compliance: l FCP (SCSI) l FC-FLA l FC-PLDA Full speed Fibre Channel operation (100 MB/s) Full duplex operation Fibre Channel arbitrated loop topology l Single Port l Dual Port l Dual Loop l Loop Port Controller Class 3 service Customizable transmit and receive buffer sizes Flow through data parity protection Multiple concurrent command support hardware Customizable concurrent exchange management Customizable bolt-on functions l Buffer to Buffer Credit Manager l Exchange Tables Transmit Prioritizer l Command on Second Port Controller l Recieve Buffer l Transmit Buffer Hardware-assisted loop initialization Hardware-assisted FCP SCSI operations End-to-end overlapping error detection Sophisticated debug features Compatible with LSI Logic’s CoreWare library Family Description The Merlin™ Fibre Channel Core Family is comprised of three components: l Fibre Channel Engine (FCE) l Bolt-On Modules l Loop Port Controller (LPC) Fibre Channel Engine The Fibre Channel Engine is responsible for frame transmission and reception, exchange management, and inter-module traffic management. It performs all the processing required to concurrently transmit and receive frames at the full Fibre Channel data rate. It also automates SCSI command processing, generating the required data, control and status frames. Supports multiple concurrent commands (exchanges). Fibre Channel Engine Transmit Exchange Controller FCP SCSI Assist Register File Receive Exchange Controller Processor Interface Figure 1: Fibre Channel Engine (FCE) Bolt-On Modules The Bolt-On Modules are Transmit Buffer, Receive Buffer, Transmit Prioritizer, BB (Buffer-to-Buffer) Credit Manager, Exchange Tables, TXB DMA Interface and RXB DMA Interface. The Transmit Buffer and Receive Buffer can be used if the system memory cannot guarantee immediate full-bandwidth access. The Transmit Prioritizer determines which exchange has the highest priority to send frames. The BB Credit Manager provides efficient buffer-to-buffer flow control on an arbitrated loop. The Exchange Table RAM provides a central data storage area for the Exchange Table used by the FCE. The TXB DMA Interface and RXB DMA Interface allow a DMA module to transfer data from external storage directly to the FCE. Transmit Buffer (TXB) RXB DMA Interface Transmit Prioritizer BB_Credit Manager Exchange Tables Receive Buffer (RXB) TXB DMA Interface Bolt-On Modules Figure 2: Bolt-On Modules 2 Implementation Description Loop Port Controller The Loop Port Controller is responsible for performing the loop protocols such as loop initialization, arbitration and the opening and closing of loop circuits. The Loop Port Controller’s FC-AL2 Loop Port State Machine implements the FC-1 and FC-AL2 layers of the Fibre Channel standard. The integrated GigaBlaze™ Transceiver provides the Fibre Channel FC-0 layer physical interface. The 1.0625 Gb/s transceivers are based on LSI Logic’s widely adopted GigaBlaze™ embedded transceiver technology. The GigaBlaze™ core is a gigabit per second transceiver, which is compliant with the Fibre Channel FC-0 physical interface standard. The transceiver core includes serializer and deserializer circuitry. The deserializer receives a serial gigabit speed input data stream and converts it into parallel. This parallel data is received by the Merlin™ core’s 8B/10B decode circuitry. Likewise, parallel data from Merlin’s 8B/10B encoder can be transmitted at the Fibre Channel physical rate of 1.0625 Gb/s after being converted into a serial stream by the serializer. GigaBlaze™ SeriaLink technology greatly reduces cost, power consumption and board area over system implementations using external bipolar or gallium arsenide transceivers. LPC 1.0625 Gb/s Transceiver Encode E_FIFO Loop Port State Machine Decode Transmit Buffer (TXB) Register File Receive Exchange Controller Processor Interface Receive Buffer (RXB) RXB DMA Interface Transmit Prioritizer FCP SCSI Assist TXB DMA Interface Bolt-On Modules Transmit Exchange Controller BB_Credit Manager Decode Fibre Channel Engine Exchange Tables Loop Port State Machine E_FIFO 1.0625 Gb/s Transceiver Encode The Merlin™ Fibre Channel Core Family is architected for scalability, enabling both high-performance and low-cost Fibre Channel implementations. You can choose on-chip frame buffer sizes to maintain Fibre Channel performance with a wide range of back-end bus structures. Implementers can tune the number of exchange contexts and incoming/outgoing frames cached concurrently on chip to meet varying performance requirements. The Merlin Fibre Channel Core Family has high-speed bus interfaces, which eliminate bottlenecks in the Fibre Channel data path. Available 32-, 64- and 128-bit interfaces handle frame delivery between the cores and downstream logic. A 32-bit local bus is provided for designs requiring a local microprocessor, such as LSI Logic’s MiniRISC, TinyRISC and ARM cores, or RAM. End-to-end flow through parity protection is provided on all Merlin™ core data paths. The Merlin™ core family simplifies the design debug process by providing extensive core visibility through the local bus interface. Figure 3: Loop Port Controller LPC The Merlin™ Fibre Channel Core Family is used in three basic configurations: Loop Port Controller, Single Port and Dual Loop. The Loop Port Controller can be used alone for a cost-effective solution in applications such as Switches/Hubs (see Figure 3). The Single Port and Dual Loop configurations add a high-performance Fibre Channel protocol engine which handles Fibre Channel exchange, sequence and frame management (see Figures 4 & 5). Once programmed with control information for a Fibre Channel exchange, the Single Port and Dual Loop configurations automate the exchange from start to finish. The Single Port and Dual Loop configurations also provide hardware assistance for FCP SCSI Initiator and Target operations including notification of incoming SCSI commands and responses and XFER_RDY management. Two single port configurations can be combined to create a dual port configuration (see Figure 6). Figure 4: Single Port Fibre Channel Controller Combines the Loop Port Controller, a Fibre Channel Engine and the Bolt-On Modules 3 LPC Transmit Exchange Controller Transmit Buffer (TXB) Register File Receive Exchange Controller Processor Interface Receive Buffer (RXB) RXB DMA Interface Transmit Prioritizer FCP SCSI Assist BB_Credit Manager Loop Port State Machine E_FIFO 1.0625 Gb/s Transceiver Encode Bolt-On Modules Exchange Tables LPC Fibre Channel Engine TXB DMA Interface Decode DL Loop Multiplexer Loop Port State Machine E_FIFO 1.0625 Gb/s Transceiver Encode Decode Figure 5: Dual Loop Fibre Channel Controller - Combines two Loop Port Controllers, a Loop Multiplexer module, the Fibre Channel Engine and the Bolt-On Modules 4 LPC Fibre Channel Engine Receive Exchange Controller Receive Buffer (RXB) E_FIFO Exchange Tables RXB DMA Interface BB_Credit Manager Register File FCP SCSI Assist Encode Loop Port State Machine Decode 1.0625 Gb/s Transceiver Transmit Exchange Controller Transmit Buffer (TXB) Transmit Prioritizer TXB DMA Interface Bolt-On Modules Processor Interface Transmit Buffer (TXB) Transmit Exchange Controller FCP SCSI Assist Receive Exchange Controller Receive Buffer (RXB) Encode E_FIFO Exchange Tables RXB DMA Interface BB_Credit Manager Register File LPC Loop Port State Machine Decode 1.0625 Gb/s Transceiver Fibre Channel Engine Transmit Prioritizer TXB DMA Interface Bolt-On Modules Processor Interface Figure 6: Dual Port Fibre Channel Controller - Combines two Single Port configurations. This differs from the Dual Loop configuration because it consists of two completely independent Fibre Channel Ports. The Dual Loop configuration has independent loop controllers, which must share a single protocol engine (FCE) CoreWare Design Program The CoreWare design program enables system-on-a-chip design integration, delivering unmatched market advantages. It is proven and complete, offering the technology and application know-how to put an entire system on a single chip. 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