SONY CXK77Q36B160GB 16Mb LW LS R-R HSTL High Speed Synchronous SRAM (512K x 36) 28/33/4 Preliminary Description The CXK77Q36B160GB is a high speed CMOS synchronous static RAM with common I/O pins, organized as 524,288 words by 36 bits. This synchronous SRAM integrates input registers, high speed RAM, output registers, and a one-deep write buffer onto a single monolithic IC. Register - Register (R-R) read operations and Late Write (LW) write operations are supported, providing a high-performance user interface. Two distinct R-R modes of operation are supported, selectable via the M2 mode pin. When M2 is “high”, this device functions as a conventional R-R SRAM, and pin 4P functions as a conventional SA address input. When M2 is “low”, this device functions as a Late Select (LS) R-R SRAM, and pin 4P functions as a Late Select SAS address input. When Late Select R-R mode is selected, the SRAM is divided into two banks internally. During write operations, SAS is registered in the same cycle as the other address and control signals, and is used to select to which bank input data is ultimately written (through one stage of write pipelining). During read operations, SAS is registered one full clock cycle after the other address and control signals, and is used to select from which bank output data is read. All address and control input signals except G (Output Enable) and ZZ (Sleep Mode) are registered on the rising edge of K (Input Clock). During read operations, output data is driven valid from the rising edge of K, one full clock cycle after all address and control input signals (except SAS) are registered. During write operations, input data is registered on the rising edge of K, one full clock cycle after all address and control input signals (including SAS) are registered. Output drivers are series terminated, and output impedance is programmable via the ZQ input pin. By connecting an external control resistor RQ between ZQ and VSS, the impedance of all data output drivers can be precisely controlled. Sleep (power down) mode control is provided through the asynchronous ZZ input. 350 MHz operation is obtained from a single 2.5V power supply. JTAG boundary scan interface is provided using a subset of IEEE standard 1149.1 protocol. Features • • • • • • • • • • • • • • • • 3 Speed Bins -28 -33 -4 Cycle Time / Access Time 2.8ns / 1.5ns 3.3ns / 1.6ns 4.0ns / 1.8ns Single 2.5V power supply (VDD): 2.5V ± 5% Dedicated output supply voltage (VDDQ): 1.5V typical HSTL-compatible I/O interface with dedicated input reference voltage (VREF): 0.75V typical Register - Register (R-R) read protocol Late Write (LW) write protocol Conventional or Late Select (LS) mode of operation, selectable via dedicated mode pin (M2) Full read/write coherency Byte Write capability Two cycle deselect Differential input clocks (K/K) Asynchronous output enable (G) Programmable output driver impedance Sleep (power down) mode via dedicated mode pin (ZZ) JTAG boundary scan (subset of IEEE standard 1149.1) 119 pin (7x17), 1.27mm pitch, 14mm x 22mm Ball Grid Array (BGA) package 16Mb LW R-R and R-R w/ LS, rev 1.0 1 / 25 October 18, 2001 SONY® Preliminary CXK77Q36B160GB Pin Assignment (Top View) 1 2 3 4 5 6 7 A VDDQ SA SA NC SA SA VDDQ B NC SA SA NC SA SA NC C NC SA SA VDD SA SA NC D DQc DQc V SS ZQ V SS DQb DQb E DQc DQc V SS SS V SS DQb DQb F VDDQ DQc V SS G V SS DQb VDDQ G DQc DQc SBWc NC SBWb DQb DQb H DQc DQc V SS NC V SS DQb DQb J VDDQ VDD VREF VDD VREF VDD VDDQ K DQd DQd V SS K V SS DQa DQa L DQd DQd SBWd K SBWa DQa DQa M VDDQ DQd V SS SW V SS DQa VDDQ N DQd DQd V SS SA V SS DQa DQa P DQd DQd V SS SA / SAS (5) V SS DQa DQa R NC SA M1 (3) VDD M2 (4) SA NC T NC NC (1) SA SA SA NC (1) ZZ U VDDQ TMS TDI TCK TDO RSVD (2) VDDQ Notes: 1. Pad Locations 2T and 6T are true no-connects. However, they are defined as SA address inputs in x18 LW SRAMs. 2. Pad Location 6U must be left unconnected. It is used by Sony for internal test purposes. 3. Pad Location 3R is defined as an M1 mode pin in LW SRAMs. However, it must be tied “low” in this device. 4. Pad Location 5R is defined as an M2 mode pin in this device. It must be tied “high” or “low”. When M2 is tied “high”, this device functions as a conventional R-R SRAM. When M2 is tied “low”, this device functions as a Late Select R-R SRAM. 5. Pad Location 4P is defined as an SA address input in LW SRAMs. However, it functions as a conventional SA address input in this device only when M2 is tied “high”. It functions as a Late Select SAS address input in this device when M2 is tied “low”. 16Mb LW R-R and R-R w/ LS, rev 1.0 2 / 25 October 18, 2001 SONY® CXK77Q36B160GB Preliminary Pin Description Symbol Type Description SA Input Synchronous Address Inputs - Registered on the rising edge of K. SAS Input Synchronous Late Select Address Input (Late Select R-R Mode Only) - Registered on the rising edge of K. Sampled one cycle after the other address and control inputs during read operations. Sampled in the same cycle as the other address and control inputs during write operations. DQa, DQb DQc, DQd I/O Synchronous Data Inputs / Outputs - Registered on the rising edge of K during write operations. Driven from the rising edge of K during read operations. DQa - indicates Data Byte a DQb - indicates Data Byte b DQc - indicates Data Byte c DQd - indicates Data Byte d K, K Input Differential Input Clocks SS Input Synchronous Select Input - Registered on the rising edge of K. specifies a write operation when SW = 0 SS = 0 specifies a read operation when SW = 1 specifies a deselect operation SS = 1 SW Input Synchronous Global Write Enable Input - Registered on the rising edge of K. specifies a write operation when SS = 0 SW = 0 specifies a read operation when SS = 0 SW = 1 SBWa, SBWb, SBWc, SBWd Input Synchronous Byte Write Enable Inputs - Registered on the rising edge of K. SBWa = 0 specifies write Data Byte a when SS = 0 and SW = 0 SBWb = 0 specifies write Data Byte b when SS = 0 and SW = 0 SBWc = 0 specifies write Data Byte c when SS = 0 and SW = 0 SBWd = 0 specifies write Data Byte d when SS = 0 and SW = 0 G Input Asynchronous Output Enable Input - Deasserted (high) disables the data output drivers. ZZ Input Asynchronous Sleep Mode Input - Asserted (high) forces the SRAM into low-power mode. M1 Input Read Operation Protocol Select 1 - This mode pin must be tied “low” at power-up to select Register - Register read operations M2 Input Read Operation Protocol Select 2 - This mode pin must be tied “high” or “low” at power-up. M2 = 0 selects Late Select R-R functionality M2 = 1 selects conventional R-R functionality ZQ Input Output Impedance Control Resistor Input - This pin must be connected to VSS through an external resistor RQ to program data output driver impedance. See the Programmable Output Driver Impedance section for further information. VDD 2.5V Core Power Supply - Core supply voltage. VDDQ Output Power Supply - Output buffer supply voltage. VREF Input Reference Voltage - Input buffer threshold voltage. VSS Ground TCK Input JTAG Clock TMS Input JTAG Mode Select - Weakly pulled “high” internally. TDI Input JTAG Data In - Weakly pulled “high” internally. TDO Output JTAG Data Out RSVD Reserved - This pin is used for Sony test purposes only. It must be left unconnected. NC No Connect - These pins are true no-connects, i.e. there is no internal chip connection to these pins. They can be left unconnected or tied directly to VDD, VDDQ, or VSS. 16Mb LW R-R and R-R w/ LS, rev 1.0 3 / 25 October 18, 2001 SONY® Preliminary CXK77Q36B160GB •Clock Truth Table K ZZ SS (tn) SW (tn) SBWx (tn) G X H X X X X Sleep (Power Down) Mode L→H L H X X X Deselect L→H L L H X H L→H L L H X L→H L L L L→H L L L→H L L DQ (tn) DQ (tn+1) Hi - Z Hi - Z X Hi - Z Read Hi - Z Hi - Z L Read X Q(tn) L X Write All Bytes X D(tn) L X X Write Bytes With SBWx = L X D(tn) L H X Abort Write X Hi - Z Operation •Dynamic M2 Mode Pin State Changes Although M2 is defined as a static input (that is, it must be tied “high” or “low” at power-up), in some instance (such as during device testing) it may be desirable to change its state dynamically (that is, without first powering off the SRAM) while preserving the contents of the memory array. If so, the following criteria must be met: 1. At least two (2) consecutive deselect operations must be initiated prior to changing the state of M2, to ensure that the most recent read or write operation completes successfully. 2. At least thirty-two (32) consecutive deselect operations must be initiated after changing the state of M2 before any read or write operations can be initiated, to allow the SRAM sufficient time to recognize the change in state. •Sleep (Power Down) Mode Sleep (power down) mode is provided through the asynchronous input signal ZZ. When ZZ is asserted (high), the output drivers will go to a Hi-Z state, and the SRAM will begin to draw standby current. Contents of the memory array will be preserved. An enable time (tZZE) must be met before the SRAM is guaranteed to be in sleep mode, and a recovery time (tZZR) must be met before the SRAM can resume normal operation. •Programmable Output Driver Impedance This device has programmable impedance output drivers. The output impedance is controlled by an external resistor RQ connected between the SRAM’s ZQ pin and VSS, and is equal to one-fifth the value of this resistor, nominally. See the DC Electrical Characteristics section for further information. Output Driver Impedance Power-Up Requirements Output driver impedance will reach the programmed value within 8192 cycles after power-up. Consequently, it is recommended that Read operations not be initiated until after the initial 8192 cycles have elapsed. Output Driver Impedance Updates Output driver impedance is updated during Write and Deselect operations when the output driver is disabled. •Power-Up Sequence For reliability purposes, Sony recommends that power supplies power up in the following sequence: VSS, VDD, VDDQ, VREF, and Inputs. VDDQ should never exceed VDD. If this power supply sequence cannot be met, a large bypass diode may be required between VDD and VDDQ. Please contact Sony Memory Application Department for further information. 16Mb LW R-R and R-R w/ LS, rev 1.0 4 / 25 October 18, 2001 SONY® Preliminary CXK77Q36B160GB •Absolute Maximum Ratings(1) Parameter Symbol Rating Units Supply Voltage VDD -0.5 to +3.0 V Output Supply Voltage VDDQ -0.5 to +2.3 V VIN -0.5 to VDDQ + 0.5 (2.3V max) V Input Voltage (M1, M2) VMIN -0.5 to VDD + 0.5 (3.0V max) V Input Voltage (TCK, TMS, TDI)) VTIN -0.5 to +3.8 V Operating Temperature TA 0 to 85 °C Junction Temperature TJ 0 to 110 °C Storage Temperature TSTG -55 to 150 °C Input Voltage (Address, Control, Data, Clock) (1) Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions other than those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. •BGA Package Thermal Characteristics Parameter Junction to Case Temperature Symbol Rating Units ΘJC 1.0 °C/W •I/O Capacitance (TA = 25oC, f = 1 MHz) Parameter Input Capacitance Output Capacitance Symbol Test Conditions Min Max Units Address CIN VIN = 0V --- 4.2 pF Control CIN VIN = 0V --- 4.2 pF Clock CKIN VKIN = 0V --- 3.5 pF Data COUT VOUT = 0V --- 4.8 pF Note: These parameters are sampled and are not 100% tested. 16Mb LW R-R and R-R w/ LS, rev 1.0 5 / 25 October 18, 2001 SONY® Preliminary CXK77Q36B160GB •DC Recommended Operating Conditions Parameter (VSS = 0V, TA = 0 to 85oC) Symbol Min Typ Max Units Notes Supply Voltage VDD 2.37 2.5 2.63 V Output Supply Voltage VDDQ 1.4 1.5 1.6 V Input Reference Voltage VREF 0.6 0.75 0.9 V 1 Input High Voltage (Address, Control, Data) VIH VREF + 0.2 --- VDDQ + 0.3 V 2 Input Low Voltage (Address, Control, Data) VIL -0.3 --- VREF - 0.2 V 3 Input High Voltage (M1, M2) VMIH 1.2 --- VDD + 0.3 V Input Low Voltage (M1, M2) VMIL -0.3 --- 0.4 V Clock Input Signal Voltage VKIN -0.3 --- VDDQ + 0.3 V Clock Input Differential Voltage VDIF 0.2 --- VDDQ + 0.6 V Clock Input Common Mode Voltage VCM 0.6 0.75 0.9 V 1. The peak-to-peak AC component superimposed on V REF may not exceed 5% of the DC component. 2. V IH (max) AC = VDDQ + 0.75V for pulse widths less than one-quarter of the cycle time (tCYC/4). 3. V IL (min) AC = -0.75V for pulse widths less than one-quarter of the cycle time (tCYC/4). 16Mb LW R-R and R-R w/ LS, rev 1.0 6 / 25 October 18, 2001 SONY® Preliminary CXK77Q36B160GB •DC Electrical Characteristics Parameter Symbol Input Leakage Current (Address, Control, Clock) ILI Input Leakage Current (M1, M2) IMLI Output Leakage Current ILO Average Power Supply Operating Current IDD-28 IDD-33 IDD-4 Power Supply Deselect Operating Current IDD2 (NOP Current) (VDD = 2.5V ± 5%, VSS = 0V, TA = 0 to 85oC) Test Conditions Min Typ Max Units VIN = V SS to VDDQ -5 --- 5 uA VMIN = VSS to V DD -5 --- 5 uA -5 --- 5 uA ------- ------- 900 800 700 mA --- --- 300 mA --- --- 250 mA VDDQ - 0.4 --- --- V --- --- 0.4 V --- --- 33 Ω 1,3 Ω 3 Ω 2,3 VOUT = V SS to VDDQ G = VIH IOUT = 0 mA SS = VIL, ZZ = VIL IOUT = 0 mA SS = VIH, ZZ = VIL IOUT = 0 mA Power Supply Standby Current ISB Output High Voltage VOH RQ = 250 Ω Output Low Voltage VOL RQ = 250 Ω ZZ = VIH IOH = -6.0 mA IOL = 6.0 mA VOH, VOL = VDDQ/2 RQ < 150Ω Output Driver Impedance ROUT VOH, VOL = VDDQ/2 (RQ/5)* 150Ω ≤ RQ ≤ 300Ω 0.9 VOH, VOL = VDDQ/2 54 RQ > 300Ω (60*0.9) RQ/5 (30*1.1) (RQ/5)* --- 1.1 --- Notes 4 1. For maximum output drive (i.e. minimum impedance), the ZQ pin can be tied directly to VSS. 2. For minimum output drive (i.e. maximum impedance), the ZQ pin can be left unconnected or tied to VDDQ. 3. This parameter is guaranteed by design through extensive corner lot characterization. 4. Average Power Supply Operating Current in devices marked as “-33” is guaranteed (by test) to meet both the IDD-33 specification at 300 MHz operation and the IDD-4 specification at 250 MHz operation. 16Mb LW R-R and R-R w/ LS, rev 1.0 7 / 25 October 18, 2001 SONY® Preliminary CXK77Q36B160GB •AC Electrical Characteristics (TA = 0 to 85oC) -28 Parameter -33 -4 Symbol Units Min Max Min Max Min Max Notes K Cycle Time tKHKH 2.8 --- 3.3 --- 4.0 --- ns K Clock High Pulse Width tKHKL 1.1 --- 1.3 --- 1.5 --- ns K Clock Low Pulse Width tKLKH 1.1 --- 1.3 --- 1.5 --- ns Address / Late Select Setup Time tAVKH 0.3 --- 0.3 --- 0.3 --- ns Address / Late Select Hold Time tKHAX 0.5 --- 0.6 --- 0.7 --- ns Write Enables Setup Time tWVKH 0.3 --- 0.3 --- 0.3 --- ns Write Enables Hold Time tKHWX 0.5 --- 0.6 --- 0.7 --- ns Synchronous Select Setup Time tSVKH 0.3 --- 0.3 --- 0.3 --- ns Synchronous Select Hold Time tKHSX 0.5 --- 0.6 --- 0.7 --- ns Data Input Setup Time tDVKH 0.3 --- 0.3 --- 0.3 --- ns Data Input Hold Time tKHDX 0.5 --- 0.6 --- 0.7 --- ns K Clock High to Output Valid tKHQV --- 1.5 --- 1.6 --- 1.8 ns K Clock High to Output Hold tKHQX 0.7 --- 0.7 --- 0.7 --- ns 2 K Clock High to Output Low-Z tKHQX1 0.7 --- 0.7 --- 0.7 --- ns 2,3 K Clock High to Output High-Z tKHQZ 0.7 1.7 0.7 1.8 0.7 2.0 ns 2,3 Output Enable Low to Output Valid tGLQV --- 1.7 --- 1.8 --- 2.0 ns Output Enable Low to Output Low-Z tGLQX 0.3 --- 0.3 --- 0.3 --- ns 2,3 Output Enable High to Output High-Z tGHQZ --- 1.7 --- 1.8 --- 2.0 ns 2,3 Sleep Mode Enable Time tZZE --- 15 --- 15 --- 15 ns 2 Sleep Mode Recovery Time tZZR 20 --- 20 --- 20 --- ns 2 1 1 1 1 All parameters are measured from the mid-point of the object signal to the mid-point of the reference signal, unless otherwise noted. 1. These parameters are measured from VREF ± 200mV to the clock mid-point. 2. These parameters are verified through device characterization, and are not 100% tested. 3. These parameters are measured at ± 50mV from steady state voltage. 16Mb LW R-R and R-R w/ LS, rev 1.0 8 / 25 October 18, 2001 SONY® Preliminary CXK77Q36B160GB •AC Test Conditions (VDD = 2.5V ± 5%, V DDQ = 1.5V ± 0.1V, TA = 0 to 85°C) Parameter Symbol Conditions Units VREF 0.75 V Input High Level VIH 1.25 V Input Low Level VIL 0.25 V Input Rise & Fall Time 2.0 V/ns Input Reference Level 0.75 V Input Reference Voltage Notes Clock Input High Voltage VKIH 1.25 V VDIF = 1.0V Clock Input Low Voltage VKIL 0.25 V VDIF = 1.0V Clock Input Common Mode Voltage VCM 0.75 V Clock Input Rise & Fall Time 2.0 V/ns Clock Input Reference Level K/K cross V Output Reference Level 0.75 V Output Load Conditions RQ = 250Ω See Figure 1 below Figure 1: AC Test Output Load (VDDQ = 1.5V) 0.75 V 50 Ω 16.7 Ω 50 Ω 5 pF DQ 16.7 Ω 0.75 V 50 Ω 16.7 Ω 50 Ω 5 pF 16Mb LW R-R and R-R w/ LS, rev 1.0 9 / 25 October 18, 2001 SONY® Preliminary CXK77Q36B160GB Conventional R-R Mode: Timing Diagram of Read-Write-Read Operations Synchronously Controlled via SS and Deselect Operations (G = Low) Figure 2 Read Read Read Deselect Deselect Write Write Write Read Read Read A5 A6 A7 A8 A9 K K tKHKL tKLKH tKHKH tAVKH tKHAX SA A1 A2 A3 A4 tSVKH tKHSX SS tWVKH tKHWX SW tWVKH tKHWX SBWx G = VIL tKHQV DQ tKHQX Q1 tKHQZ Q2 Q3 tDVKH tKHDX D4 tKHQX1 D5 D6 Q7 Note: In the diagram above, two Deselect operations are inserted between Read and Write operations to control the data bus transition from output to input. This depiction is for clarity purposes only. It is NOT a requirement. Depending on the application, one Deselect operation may be sufficient. 16Mb LW R-R and R-R w/ LS, rev 1.0 10 / 25 October 18, 2001 SONY® Preliminary CXK77Q36B160GB Conventional R-R Mode: Timing Diagram of Read-Write-Read Operations Asynchronously Controlled via G and Dummy Read Operations (SS = Low) Figure 3 Read Read Dummy Read Read Dummy Read Write Write Write Read Read Read A5 A6 A7 A8 A9 K K tKHKL tKLKH tKHKH tAVKH tKHAX SA A1 A2 A3 A4 SS = VIL tWVKH tKHWX SW tWVKH tKHWX SBWx G tGLQV tGHQZ tKHQV DQ tKHQX Q1 tKHQZ Q2 Q3 tGLQX tDVKH tKHDX D4 tKHQX1 D5 D6 Q7 Note: In the diagram above, two Dummy Read operations are inserted between Read and Write operations to control the data bus transition from output to input. This depiction is for clarity purposes only. It is NOT a requirement. Depending on the application, one Dummy Read operation may be sufficient. 16Mb LW R-R and R-R w/ LS, rev 1.0 11 / 25 October 18, 2001 SONY® Preliminary CXK77Q36B160GB Late Select R-R Mode: Timing Diagram of Read-Write-Read Operations Synchronously Controlled via SS and Deselect Operations (G = Low) Figure 4 Read Read Read Deselect Deselect Write Write Write Read Read Read A5 A6 A7 A8 A9 A5 A6 A7 A8 K K tKHKL tKLKH tKHKH tAVKH tKHAX SA A1 A2 A3 A4 tAVKH tKHAX SAS A1 A2 A3 A4 tSVKH tKHSX SS tWVKH tKHWX SW tWVKH tKHWX SBWx G = VIL tKHQV DQ tKHQX Q1 tKHQZ Q2 Q3 tDVKH tKHDX D4 tKHQX1 D5 D6 Q7 Note: In the diagram above, two Deselect operations are inserted between Read and Write operations to control the data bus transition from output to input. This depiction is for clarity purposes only. It is NOT a requirement. Depending on the application, one Deselect operation may be sufficient. 16Mb LW R-R and R-R w/ LS, rev 1.0 12 / 25 October 18, 2001 SONY® Preliminary CXK77Q36B160GB Late Select R-R Mode: Timing Diagram of Read-Write-Read Operations Asynchronously Controlled via G and Dummy Read Operations (SS = Low) Figure 5 Read Read Dummy Read Read Dummy Read Write Write Write Read Read Read A5 A6 A7 A8 A9 A5 A6 A7 A8 K K tKHKL tKLKH tKHKH tAVKH tKHAX SA A1 A2 A3 A4 tAVKH tKHAX SAS A1 A2 A3 A4 SS = VIL tWVKH tKHWX SW tWVKH tKHWX SBWx G tGLQV tGHQZ tKHQV DQ tKHQX Q1 tKHQZ Q2 Q3 tGLQX tDVKH tKHDX D4 tKHQX1 D5 D6 Q7 Note: In the diagram above, two Dummy Read operations are inserted between Read and Write operations to control the data bus transition from output to input. This depiction is for clarity purposes only. It is NOT a requirement. Depending on the application, one Dummy Read operation may be sufficient. 16Mb LW R-R and R-R w/ LS, rev 1.0 13 / 25 October 18, 2001 SONY® Preliminary CXK77Q36B160GB Timing Diagram of Sleep (Power-Down) Mode Operation Asynchronously Controlled via ZZ Figure 6 Read (note 1) Deselect (note 2) Deselect (note 2) (note 3) Deselect (note 4) Read (note 5) Read (note 5) Read (note 5) A2 A3 A4 A2 A3 K K SA SAS A1 A1 SS SW SBWx G = VIL tZZE Begin ISB tZZR ZZ DQ Q1 Q2 Note 1: This can be ANY valid operation. The depiction of a Read operation here is provided only as an example. Note 2: Before ZZ is asserted, at least two (2) Deselect operations must be initiated after the last Read or Write operation is initiated, in order to ensure the successful completion of the last Read or Write operation. Note 3: While ZZ is asserted, all of the SRAM’s address, control, data, and clock inputs are ignored. Note 4: After ZZ is deasserted, Deselect operations must be initiated until the specified recovery time (tZZR) has been met. Read and Write operations may NOT be initiated during this time. Note 5: This can be ANY valid operation. The depiction of a Read operation here is provided only as an example. 16Mb LW R-R and R-R w/ LS, rev 1.0 14 / 25 October 18, 2001 SONY® Preliminary CXK77Q36B160GB •Test Mode Description This device provides a JTAG Test Access Port (TAP) and Boundary Scan interface using a limited set of IEEE std. 1149.1 functions. This test mode is intended to provide a mechanism for testing the interconnect between master (processor, controller, etc.), SRAMs, other components, and the printed circuit board. In conformance with a subset of IEEE std. 1149.1, this device contains a TAP Controller and four TAP Registers. The TAP Registers consist of one Instruction Register and three Data Registers (ID, Bypass, and Boundary Scan Registers). The TAP consists of the following four signals: TCK: TMS: TDI: TDO: Test Clock Test Mode Select Test Data In Test Data Out Induces (clocks) TAP Controller state transitions. Inputs commands to the TAP Controller. Sampled on the rising edge of TCK. Inputs data serially to the TAP Registers. Sampled on the rising edge of TCK. Outputs data serially from the TAP Registers. Driven from the falling edge of TCK. Disabling the TAP When JTAG is not used, TCK should be tied “low” to prevent clocking the SRAM. TMS and TDI should either be tied “high” through a pull-up resistor or left unconnected. TDO should be left unconnected. Note: Operation of the TAP does not interfere with normal SRAM operation except when the SAMPLE-Z instruction is selected. Consequently, TCK, TMS, and TDI can be controlled any number of ways without adversely affecting the functionality of the device. (VDD = 2.5V ± 5%, TA = 0 to 85°C) JTAG DC Recommended Operating Conditions Parameter Symbol Test Conditions Min Max Units JTAG Input High Voltage VTIH --- 1.4 3.6 V JTAG Input Low Voltage VTIL --- -0.3 0.8 V JTAG Output High Voltage (CMOS) VTOH ITOH = -100uA VDD - 0.1 --- V JTAG Output Low Voltage (CMOS) VTOL ITOL = 100uA --- 0.1 V JTAG Output High Voltage (TTL) VTOH ITOH = -4.0mA VDD - 0.4 --- V JTAG Output Low Voltage (TTL) VTOL ITOL = 4.0mA --- 0.4 V VTIN = 0V to 3.6V -10 10 uA JTAG Input Leakage Current ITLI (VDD = 2.5V ± 5%, TA = 0 to 85°C) JTAG AC Test Conditions Parameter Symbol Conditions Units JTAG Input High Level VTIH 2.5 V JTAG Input Low Level VTIL 0.0 V JTAG Input Rise & Fall Time 1.0 V/ns JTAG Input Reference Level 1.25 V JTAG Output Reference Level 1.25 V JTAG Output Load Condition 16Mb LW R-R and R-R w/ LS, rev 1.0 Notes See Fig.1 (page 9) 15 / 25 October 18, 2001 SONY® Preliminary CXK77Q36B160GB JTAG AC Electrical Characteristics Parameter Symbol Min Max TCK Cycle Time tTHTH 100 ns TCK High Pulse Width tTHTL 40 ns TCK Low Pulse Width tTLTH 40 ns TMS Setup Time tMVTH 10 ns TMS Hold TIme tTHMX 10 ns TDI Setup Time tDVTH 10 ns TDI Hold TIme tTHDX 10 ns TCK Low to TDO Valid tTLQV TCK Low to TDO Hold tTLQX 20 0 Unit ns ns JTAG Timing Diagram Figure 7 tTHTL tTLTH tTHTH TCK tMVTH tTHMX tDVTH tTHDX TMS TDI tTLQV tTLQX TDO 16Mb LW R-R and R-R w/ LS, rev 1.0 16 / 25 October 18, 2001 SONY® Preliminary CXK77Q36B160GB TAP Registers TAP Registers are serial shift registers that capture serial input data (from TDI) on the rising edge of TCK, and drive serial output data (to TDO) on the subsequent falling edge of TCK. They are divided into two groups: “Instruction Registers”, of which there is one- the Instruction Register, and “Data Registers”, of which there are three - the ID Register, the Bypass Register, and the Boundary Scan Register. Individual TAP registers are “selected” (inserted between TDI and TDO) when the appropriate sequence of commands is given to the TAP Controller. Instruction Register (3 bits) The Instruction Register stores the instructions that are executed by the TAP Controller when the TAP Controller is in the “Run-Test / Idle” state, or in any of the various “Data Register” states. It is loaded with the IDCODE instruction at powerup, or when the TAP Controller is in the “Test-Logic Reset” state or the “Capture-IR” state. It is inserted between TDI and TDO when the TAP Controller is in the “Shift-IR” state, at which time it can be loaded with a new instruction. However, newly loaded instructions are not executed by the TAP Controller until the TAP Controller has reached the “UpdateIR” state. The Instruction Register is 3 bits wide, and is encoded as follows: Code (2:0) Instruction 000 BYPASS Inserts the Bypass Register between TDI and TDO. 001 IDCODE Inserts the ID Register between TDI and TDO. 010 SAMPLE-Z 011 BYPASS Inserts the Bypass Register between TDI and TDO. 100 SAMPLE Captures the SRAM’s I/O ring contents in the Boundary Scan Register. Inserts the Boundary Scan Register between TDI and TDO. 101 PRIVATE Do not use. Reserved for manufacturer use only. 110 BYPASS Inserts the Bypass Register between TDI and TDO. 111 BYPASS Inserts the Bypass Register between TDI and TDO. Description Captures the SRAM’s I/O ring contents in the Boundary Scan Register. Inserts the Boundary Scan Register between TDI and TDO. Disables the SRAM’s data output drivers. Bit 0 is the LSB of the Instruction Register, and Bit 2 is the MSB. When the Instruction Register is selected, TDI serially shifts data into the MSB, and the LSB serially shifts data out through TDO. ID Register (32 bits) The ID Register is loaded with a predetermined device- and manufacturer-specific identification code when the IDCODE instruction has been loaded into the Instruction Register and the TAP Controller is in the “Capture-DR” state. It is inserted between TDI and TDO when the IDCODE instruction has been loaded into the Instruction Register and the TAP Controller is in the “Shift-DR” state. The ID Register is 32 bits wide, and is encoded as follows: Revision Number (31:28) Part Number (27:12) Sony ID (11:1) Start Bit (0) xxxx 0000 0000 0100 1010 0000 1110 001 1 Bit 0 is the LSB of the ID Register, and Bit 31 is the MSB. When the ID Register is selected, TDI serially shifts data into the MSB, and the LSB serially shifts data out through TDO. 16Mb LW R-R and R-R w/ LS, rev 1.0 17 / 25 October 18, 2001 SONY® CXK77Q36B160GB Preliminary Bypass Register (1 bit) The Bypass Register is one bit wide, and provides the minimum length serial path between TDI and TDO. It is loaded with a logic “0” when the BYPASS instruction has been loaded in the Instruction Register and the TAP Controller is in the “Capture-DR” state. It is inserted between TDI and TDO when the BYPASS instruction has been loaded into the Instruction Register and the TAP Controller is in the “Shift-DR” state. Boundary Scan Register (70 bits) The Boundary Scan Register is equal in length to the number of active signal connections to the SRAM (excluding the TAP pins) plus a number of place holder locations reserved for density and/or functional upgrades. The Boundary Scan Register is loaded with the contents of the SRAM’s I/O ring when the SAMPLE or SAMPLE-Z instruction has been loaded into the Instruction Register and the TAP Controller is in the “Capture-DR” state. It is inserted between TDI and TDO when the SAMPLE or SAMPLE-Z instruction has been loaded into the Instruction Register and the TAP Controller is in the “Shift-DR” state. The Boundary Scan Register contains the following bits: DQ 36 SA, SAS 19 K, K 2 SS, SW, SBWx 6 G, ZZ 2 M1, M2 2 ZQ 1 Place Holder 2 For deterministic results, all signals composing the SRAM’s I/O ring must meet setup and hold times with respect to TCK (same as TDI and TMS) when sampled. K/K are connected to a differential input receiver that generates a single-ended input clock signal to the device. Therefore, in order to capture specific values for these signals in the Boundary Scan Register, these signals must be at opposite logic levels when sampled. Place Holders are required for some NC pins to allow for future density and/or functional upgrades. They are connected to VSS internally, regardless of pin connection externally. The Boundary Scan Register Bit Order Assignment table that follows depicts the order in which the bits from the table above are arranged in the Boundary Scan Register. In the notation, Bit 1 is the LSB of the register, and Bit 70 is the MSB. When the Boundary Scan Register is selected, TDI serially shifts data into the MSB, and the LSB serially shifts data out through TDO. 16Mb LW R-R and R-R w/ LS, rev 1.0 18 / 25 October 18, 2001 SONY® Preliminary CXK77Q36B160GB Boundary Scan Register Bit Order Assignment (By Exit Sequence) Bit Signal Pad Bit Signal Pad 1 M2 5R 36 SA 3B 2 SA / SAS 4P 37 SA 2B 3 SA 4T 38 SA 3A 4 SA 6R 39 SA 3C 5 SA 5T 40 SA 2C 6 ZZ 7T 41 SA 2A 7 DQa 6P 42 DQc 2D 8 DQa 7P 43 DQc 1D 9 DQa 6N 44 DQc 2E 10 DQa 7N 45 DQc 1E 11 DQa 6M 46 DQc 2F 12 DQa 6L 47 DQc 2G 13 DQa 7L 48 DQc 1G 14 DQa 6K 49 DQc 2H 15 DQa 7K 50 DQc 1H 16 SBWa 5L 51 SBWc 3G 17 K 4L 52 ZQ 4D 18 K 4K 53 SS 4E 19 G 4F 54 NC (1) 4G (1) 4H 20 SBWb 5G 55 NC 21 DQb 7H 56 SW 4M 22 DQb 6H 57 SBWd 3L 22 DQb 7G 58 DQd 1K 24 DQb 6G 59 DQd 2K 25 DQb 6F 60 DQd 1L 26 DQb 7E 61 DQd 2L 27 DQb 6E 62 DQd 2M 28 DQb 7D 63 DQd 1N 29 DQb 6D 64 DQd 2N 30 SA 6A 65 DQd 1P 31 SA 6C 66 DQd 2P 32 SA 5C 67 SA 3T 33 SA 5A 68 SA 2R 34 SA 6B 69 SA 4N 35 SA 5B 70 M1 3R Note 1: NC pins at pad locations 4G and 4H are connected to VSS internally, regardless of pin connection externally. 16Mb LW R-R and R-R w/ LS, rev 1.0 19 / 25 October 18, 2001 SONY® CXK77Q36B160GB Preliminary TAP Instructions IDCODE IDCODE is the default instruction loaded into the Instruction Register at power-up, and when the TAP Controller is in the “Test-Logic Reset” state. When the IDCODE instruction is selected, a predetermined device- and manufacturer-specific identification code is loaded into the ID Register when the TAP Controller is in the “Capture-DR” state, and the ID Register is inserted between TDI and TDO when the TAP Controller is in the “Shift-DR” state. Normal SRAM operation is not disrupted when the IDCODE instruction is selected. BYPASS When the BYPASS instruction is selected, a logic “0” is loaded into the Bypass Register when the TAP Controller is in the “Capture-DR” state, and the Bypass Register is inserted between TDI and TDO when the TAP Controller is in the “Shift-DR” state. Normal SRAM operation is not disrupted when the BYPASS instruction is selected. SAMPLE When the SAMPLE instruction is selected, the individual logic states of all signals composing the SRAM’s I/O ring (see the Boundary Scan Register description for the complete list of signals) are loaded into the Boundary Scan Register when the TAP Controller is in the “Capture-DR” state, and the Boundary Scan Register is inserted between TDI and TDO when the TAP Controller is in the “Shift-DR” state. Normal SRAM operation is not disrupted when the SAMPLE instruction is selected. SAMPLE-Z When the SAMPLE-Z instruction is selected, the individual logic states of all signals composing the SRAM’s I/O ring (see the Boundary Scan Register description for the complete list of signals) are loaded into the Boundary Scan Register when the TAP Controller is in the “Capture-DR” state, and the Boundary Scan Register is inserted between TDI and TDO when the TAP Controller is in the “Shift-DR” state. Additionally, when the SAMPLE-Z instruction is selected, the SRAM’s data output drivers are disabled. Consequently, normal SRAM operation is disrupted when the SAMPLE-Z instruction is selected. Read operations initiated while the SAMPLE-Z instruction is selected will fail. 16Mb LW R-R and R-R w/ LS, rev 1.0 20 / 25 October 18, 2001 SONY® Preliminary CXK77Q36B160GB TAP Controller The TAP Controller is a 16-state state machine that controls access to the various TAP Registers and executes the operations associated with each TAP Instruction. State transitions are controlled by TMS and occur on the rising edge of TCK. The TAP Controller enters the “Test-Logic Reset” state in one of two ways: 1. At power up. 2. When a logic “1” is applied to TMS for at least 5 consecutive rising edges of TCK. The TDI input receiver is sampled only when the TAP Controller is in either the “Shift-IR” state or the “Shift-DR” state. The TDO output driver is active only when the TAP Controller is in either the “Shift-IR” state or the “Shift-DR” state. TAP Controller State Diagram Figure 8 1 Test-Logic Reset 0 0 Run-Test / Idle 1 Select DR-Scan 1 Select IR-Scan 0 0 1 1 Capture-DR Capture-IR 0 0 0 Shift-DR 1 1 Exit1-DR Exit1-IR 0 0 0 Pause-DR 1 0 Exit2-IR Update-DR 16Mb LW R-R and R-R w/ LS, rev 1.0 0 21 / 25 0 1 1 1 0 Pause-IR 1 Exit2-DR 0 Shift-IR 1 1 1 Update-IR 1 0 October 18, 2001 SONY® Preliminary CXK77Q36B160GB •Ordering Information VDD I/O Type Size Speed (Cycle Time / Data Access Time) CXK77Q36B160GB-28 2.5V HSTL 512K x 36 2.8ns / 1.5ns CXK77Q36B160GB-33 2.5V HSTL 512K x 36 3.3ns / 1.6ns CXK77Q36B160GB-4 2.5V HSTL 512K x 36 4.0ns / 1.8ns Part Number Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. 16Mb LW R-R and R-R w/ LS, rev 1.0 22 / 25 October 18, 2001 SONY® Preliminary CXK77Q36B160GB (7x17) 119 Pin BGA Package Dimensions 2.5 MAX 0.15 S A 13.0 0.6 ± 0.1 x4 7.62 0.35 S U T R P N M L K J H G F E D C B A 22.0 0.15 S B C 4- 0. 7 19.0 B 0 1. 4C A 0.15 S 0.20 20.32 14.0 1 2 3 4 5 S 6 7 1.27 119 - φ0.75 ± 0.15 φ0.15 M S AB P RELIMINARY PACKAGE STRUCTURE PACKAGE MATERIAL EPOXY RESIN SONY CODE BGA-119P-021 BORAD TREATMENT COPPER-CLAD LAMINATE EIAJ CODE BGA119-P-1422 LEAD MATERIAL SOLDER PACKAGE MASS 1.3g JEDEC CODE 16Mb LW R-R and R-R w/ LS, rev 1.0 23 / 25 October 18, 2001 SONY® CXK77Q36B160GB Preliminary •Revision History Rev. # Rev. Date Description of Modification rev 0.0 07/18/00 Initial Version rev 0.1 05/18/01 1. Modified I/O Capacitance (p. 5). 3.5pF to 4.2pF Address (CADDR) and Control (CCTRL) 4.5pF to 4.8pF Data (CDATA) 2. Modified DC Recommended Operating Conditions (p. 6). 1.6V to 1.9V VDDQ (max) 0.9V to 1.0V VREF, VCM (max) VREF + 0.3V to 1.2V VMIH (min) VREF - 0.3V to 0.4V VMIL (max) 3. Modified DC Electrical Characteristics (p. 7). 830mA to 930mA IDD-28 (max) 700mA to 840mA IDD-33 (max) 640mA to 780mA IDD-37 (max) 590mA to 740mA IDD-4 (max) 200mA to 300mA IDD3 (max) 130mA to 250mA ISB (max) 4. Modified AC Electrical Characteristics (p. 8). 1.7ns to 1.8ns -37 tKHQV 5. Combined 1.5V VDDQ AC Test Conditions for VDD = 2.5V and 3.3V (p.9). 6. Added 1.8V V DDQ AC Test Conditions for VDD = 2.5V and 3.3V (p.10). 7. Modified JTAG DC Recommended Operating Conditions (p. 16). 2.7V to 2.6V VTOH-3.3 (min) at ITOH = -100uA 2.4V to 2.3V VTOH-3.3 (min) at ITOH = -8mA rev 0.2 09/18/01 1. Removed 3.3V VDD support and AC Test Conditions. 2. Removed 1.8V VDDQ support and AC Test Conditions. 3. Modified Absolute Maximum Ratings (p. 5). 3.8V to 3.0V VDD (max) 4. Modified DC Recommended Operating Conditions (p. 6). 3.47V to 2.63V VDD (max) 1.9V to 1.6V VDDQ (max) 1.0V to 0.9V VREF, VCM (max) VREF + 0.1V to VREF + 0.2V VIH (min) VREF - 0.1V to VREF - 0.2V VIL (max) 5. Modified DC Electrical Characteristics (p. 7). 930mA to 900mA IDD-28 (max) 840mA to 800mA IDD-33 (max) 740mA to 700mA IDD-4 (max) Removed IDD3 (max) spec (3 MHz operating current). 300mA Added IDD2 (max) spec (Deselect operating current) 6. Modified AC Electrical Characteristics (p. 8). Removed “-37” bin. Removed “A” sub-bin from “-4” bin. 7. Modified JTAG DC Recommended Operating Conditions (p. 15). Removed VTOH-33 (min) specs. -8mA to -4mA ITOH Test Condition for VTOH (min) = V DD - 0.4V 8mA to 4mA ITOL Test Condition for VTOL (max) = 0.4V 16Mb LW R-R and R-R w/ LS, rev 1.0 24 / 25 October 18, 2001 SONY® Rev. # rev 1.0 CXK77Q36B160GB Rev. Date 10/18/01 Preliminary Description of Modification 1. Updated the Programmable Output Driver Impedance description (p. 4). 2. Modified DC Electrical Characteristics (p. 7). Added note 4 stating that Average Power Supply Operating Current in devices marked as “-33” is guaranteed (by test) to meet both the IDD-33 specification at 300 MHz operation and the IDD-4 specification at 250 MHz operation. ±10uA to ±5uA IMLI (min/max) ±10uA to ±5uA ILO (min/max) 3. Modified AC Electrical Characteristics (p. 8). Removed Output Enable Setup and Hold Time specifications. 16Mb LW R-R and R-R w/ LS, rev 1.0 25 / 25 October 18, 2001