PRELIMINARY DATA SHEET MOS INTEGRATED CIRCUIT µPD44325082, 44325092, 44325182, 44325362 36M-BIT QDRTMII SRAM 2-WORD BURST OPERATION Description The µPD44325082 is a 4,194,304-word by 8-bit, the µPD44325092 is a 4,194,304-word by 9-bit, the µPD44325182 is a 2,097,152-word by 18-bit and the µPD44325362 is a 1,048,576-word by 36-bit synchronous quad data rate static RAM fabricated with advanced CMOS technology using full CMOS six-transistor memory cell. The µPD44325082, µPD44325092, µPD44325182 and µPD44325362 integrate unique synchronous peripheral circuitry and a burst counter. All input registers controlled by an input clock pair (K and /K) are latched on the positive edge of K and /K. These products are suitable for application which require synchronous operation, high speed, low voltage, high density and wide bit configuration. These products are packaged in 165-pin PLASTIC FBGA. Features • 1.8 ± 0.1 V power supply and HSTL I/O • DLL circuitry for wide output data valid window and future frequency scaling • Separate independent read and write data ports with concurrent transactions • 100% bus utilization DDR READ and WRITE operation • Two-tick burst for low DDR transaction size • Two input clocks (K and /K) for precise DDR timing at clock rising edges only • Two output clocks (C and /C) for precise flight time and clock skew matching-clock and data delivered together to receiving device • Internally self-timed write control • Clock-stop capability with µs restart • User programmable impedance output • Fast clock cycle time : 4.0 ns (250 MHz), 5.0 ns (200 MHz) • Simple control logic for easy depth expansion • JTAG boundary scan The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. Not all products and/or types are available in every country. Please check with an NEC Electronics sales representative for availability and additional information. Document No. M16783EJ1V0DS00 (1st edition) Date Published October 2004 NS CP(K) Printed in Japan The mark shows major revised points. 2003 µPD44325082, 44325092, 44325182, 44325362 Ordering Information Part number Cycle Clock Time Frequency ns MHz µPD44325082F5-E40-EQ2 4.0 250 µPD44325082F5-E50-EQ2 5.0 200 µPD44325092F5-E40-EQ2 4.0 250 µPD44325092F5-E50-EQ2 5.0 200 µPD44325182F5-E40-EQ2 4.0 250 µPD44325182F5-E50-EQ2 5.0 200 µPD44325362F5-E40-EQ2 4.0 250 µPD44325362F5-E50-EQ2 5.0 200 2 Organization Core Supply (word x bit) Voltage I/O Package Interface V 4 M x 8-bit 1.8 ± 0.1 HSTL 165-pin PLASTIC FBGA (13 x 15) 4 M x 9-bit 2 M x 18-bit 1M x 36-bit Preliminary Data Sheet M16783EJ1V0DS µPD44325082, 44325092, 44325182, 44325362 Pin Configurations /××× indicates active low signal. 165-pin PLASTIC FBGA (13 x 15) (Top View) [µPD44325082F5-EQ2] 1 2 3 4 5 6 7 8 9 10 11 A /CQ VSS A /W /NW1 /K NC /R A A CQ B NC NC NC A NC K /NW0 A NC NC Q3 C NC NC NC VSS A A A VSS NC NC D3 D NC D4 NC VSS VSS VSS VSS VSS NC NC NC E NC NC Q4 VDDQ VSS VSS VSS VDDQ NC D2 Q2 F NC NC NC VDDQ VDD VSS VDD VDDQ NC NC NC G NC D5 Q5 VDDQ VDD VSS VDD VDDQ NC NC NC H /DLL VREF VDDQ VDDQ VDD VSS VDD VDDQ VDDQ VREF ZQ J NC NC NC VDDQ VDD VSS VDD VDDQ NC Q1 D1 K NC NC NC VDDQ VDD VSS VDD VDDQ NC NC NC L NC Q6 D6 VDDQ VSS VSS VSS VDDQ NC NC Q0 M NC NC NC VSS VSS VSS VSS VSS NC NC D0 N NC D7 NC VSS A A A VSS NC NC NC P NC NC Q7 A A C A A NC NC NC R TDO TCK A A A /C A A A TMS TDI A : Address inputs TMS : IEEE 1149.1 Test input D0 to D7 : Data inputs TDI : IEEE 1149.1 Test input Q0 to Q7 : Data outputs TCK : IEEE 1149.1 Clock input /R : Read input TDO : IEEE 1149.1 Test output /W : Write input VREF : HSTL input reference input /NW0, /NW1 : Nibble Write data select VDD : Power Supply K, /K : Input clock VDDQ : Power Supply C, /C : Output clock VSS : Ground CQ, /CQ : Echo clock NC : No connection ZQ : Output impedance matching /DLL : DLL disable Remarks 1. Refer to Package Drawing for the index mark. 2. 2A and 7A are expansion addresses: 2A for 72Mb and 7A for 144Mb. Preliminary Data Sheet M16783EJ1V0DS 3 µPD44325082, 44325092, 44325182, 44325362 165-pin PLASTIC FBGA (13 x 15) (Top View) [µPD44325092F5-EQ2] 1 2 3 4 5 6 7 8 9 10 11 A /CQ VSS A /W NC /K NC /R A A CQ B NC NC NC A NC K /BW0 A NC NC Q4 C NC NC NC VSS A A A VSS NC NC D4 D NC D5 NC VSS VSS VSS VSS VSS NC NC NC E NC NC Q5 VDDQ VSS VSS VSS VDDQ NC D3 Q3 F NC NC NC VDDQ VDD VSS VDD VDDQ NC NC NC G NC D6 Q6 VDDQ VDD VSS VDD VDDQ NC NC NC H /DLL VREF VDDQ VDDQ VDD VSS VDD VDDQ VDDQ VREF ZQ J NC NC NC VDDQ VDD VSS VDD VDDQ NC Q2 D2 K NC NC NC VDDQ VDD VSS VDD VDDQ NC NC NC L NC Q7 D7 VDDQ VSS VSS VSS VDDQ NC NC Q1 M NC NC NC VSS VSS VSS VSS VSS NC NC D1 N NC D8 NC VSS A A A VSS NC NC NC P NC NC Q8 A A C A A NC D0 Q0 R TDO TCK A A A /C A A A TMS TDI A : Address inputs TMS : IEEE 1149.1 Test input D0 to D8 : Data inputs TDI : IEEE 1149.1 Test input Q0 to Q8 : Data outputs TCK : IEEE 1149.1 Clock input /R : Read input TDO : IEEE 1149.1 Test output /W : Write input VREF : HSTL input reference input /BW0 : Byte Write data select VDD : Power Supply K, /K : Input clock VDDQ : Power Supply C, /C : Output clock VSS : Ground CQ, /CQ : Echo clock NC : No connection ZQ : Output impedance matching /DLL : DLL disable Remarks 1. Refer to Package Drawing for the index mark. 2. 2A and 7A are expansion addresses: 2A for 72Mb and 7A for 144Mb. 4 Preliminary Data Sheet M16783EJ1V0DS µPD44325082, 44325092, 44325182, 44325362 165-pin PLASTIC FBGA (13 x 15) (Top View) [µPD44325182F5-EQ2] 1 2 3 4 5 6 7 8 9 10 11 A /CQ VSS A /W /BW1 /K NC /R A VSS CQ B NC Q9 D9 A NC K /BW0 A NC NC Q8 C NC NC D10 VSS A A A VSS NC Q7 D8 D NC D11 Q10 VSS VSS VSS VSS VSS NC NC D7 E NC NC Q11 VDDQ VSS VSS VSS VDDQ NC D6 Q6 F NC Q12 D12 VDDQ VDD VSS VDD VDDQ NC NC Q5 G NC D13 Q13 VDDQ VDD VSS VDD VDDQ NC NC D5 H /DLL VREF VDDQ VDDQ VDD VSS VDD VDDQ VDDQ VREF ZQ J NC NC D14 VDDQ VDD VSS VDD VDDQ NC Q4 D4 K NC NC Q14 VDDQ VDD VSS VDD VDDQ NC D3 Q3 L NC Q15 D15 VDDQ VSS VSS VSS VDDQ NC NC Q2 M NC NC D16 VSS VSS VSS VSS VSS NC Q1 D2 N NC D17 Q16 VSS A A A VSS NC NC D1 P NC NC Q17 A A C A A NC D0 Q0 R TDO TCK A A A /C A A A TMS TDI A : Address inputs TMS : IEEE 1149.1 Test input D0 to D17 : Data inputs TDI : IEEE 1149.1 Test input Q0 to Q17 : Data outputs TCK : IEEE 1149.1 Clock input /R : Read input TDO : IEEE 1149.1 Test output /W : Write input VREF : HSTL input reference input /BW0, /BW1 : Byte Write data select VDD : Power Supply K, /K : Input clock VDDQ : Power Supply C, /C : Output clock VSS : Ground CQ, /CQ : Echo clock NC : No connection ZQ : Output impedance matching /DLL : DLL disable Remarks 1. Refer to Package Drawing for the index mark. 2. 2A and 10A are expansion addresses: 10A for 72Mb and 2A for 144Mb. Preliminary Data Sheet M16783EJ1V0DS 5 µPD44325082, 44325092, 44325182, 44325362 165-pin PLASTIC FBGA (13 x 15) (Top View) [µPD44325362F5-EQ2] 1 2 3 4 5 6 7 8 9 10 11 A /CQ VSS NC /W /BW2 /K /BW1 /R A VSS CQ B Q27 Q18 D18 A /BW3 K /BW0 A D17 Q17 Q8 C D27 Q28 D19 VSS A A A VSS D16 Q7 D8 D D28 D20 Q19 VSS VSS VSS VSS VSS Q16 D15 D7 E Q29 D29 Q20 VDDQ VSS VSS VSS VDDQ Q15 D6 Q6 F Q30 Q21 D21 VDDQ VDD VSS VDD VDDQ D14 Q14 Q5 G D30 D22 Q22 VDDQ VDD VSS VDD VDDQ Q13 D13 D5 H /DLL VREF VDDQ VDDQ VDD VSS VDD VDDQ VDDQ VREF ZQ J D31 Q31 D23 VDDQ VDD VSS VDD VDDQ D12 Q4 D4 K Q32 D32 Q23 VDDQ VDD VSS VDD VDDQ Q12 D3 Q3 L Q33 Q24 D24 VDDQ VSS VSS VSS VDDQ D11 Q11 Q2 M D33 Q34 D25 VSS VSS VSS VSS VSS D10 Q1 D2 N D34 D26 Q25 VSS A A A VSS Q10 D9 D1 P Q35 D35 Q26 A A C A A Q9 D0 Q0 R TDO TCK A A A /C A A A TMS TDI A : Address inputs TMS : IEEE 1149.1 Test input D0 to D35 : Data inputs TDI : IEEE 1149.1 Test input Q0 to Q35 : Data outputs TCK : IEEE 1149.1 Clock input /R : Read input TDO : IEEE 1149.1 Test output /W : Write input VREF : HSTL input reference input /BW0 to /BW3 : Byte Write data select VDD : Power Supply K, /K : Input clock VDDQ : Power Supply C, /C : Output clock VSS : Ground CQ, /CQ : Echo clock NC : No connection ZQ : Output impedance matching /DLL : DLL disable Remarks 1. Refer to Package Drawing for the index mark. 2. 3A and 10A are expansion addresses: 3A for 72Mb and 10A for 144Mb. 6 Preliminary Data Sheet M16783EJ1V0DS µPD44325082, 44325092, 44325182, 44325362 Pin Identification Symbol A D0 to Dxx Q0 to Qxx /R /W /BWx /NWx K, /K C, /C CQ, /CQ ZQ Description Synchronous Address Inputs: These inputs are registered and must meet the setup and hold times around the rising edge of K for READ cycles and must meet the setup and hold times around the rising edge of /K for WRITE cycles. All transactions operate on a burst of two words (one clock period of bus activity). These inputs are ignored when device is deselected. Synchronous Data Inputs: Input data must meet setup and hold times around the rising edges of K and /K during WRITE operations. See Pin Configurations for ball site location of individual signals. x8 device uses D0 to D7. x9 device uses D0 to D8. x18 device uses D0 to D17. x36 device uses D0 to D35. Synchronous Data Outputs: Output data is synchronized to the respective C and /C or to K and /K rising edges if C and /C are tied HIGH. This bus operates in response to /R commands. See Pin Configurations for ball site location of individual signals. x8 device uses Q0 to Q7. x9 device uses Q0 to Q8. x18 device uses Q0 to Q17. x36 device uses Q0 to Q35. Synchronous Read: When LOW this input causes the address inputs to be registered and a READ cycle to be initiated. This input must meet setup and hold times around the rising edge of K. Synchronous Write: When LOW this input causes the address inputs to be registered and a WRITE cycle to be initiated. This input must meet setup and hold times around the rising edge of K. Synchronous Byte Writes (Nibble Writes on x8): When LOW these inputs cause their respective byte or nibble to be registered and written during WRITE cycles. These signals must meet setup and hold times around the rising edges of K and /K for each of the two rising edges comprising the WRITE cycle. See Pin Configurations for signal to data relationships. Input Clock: This input clock pair registers address and control inputs on the rising edge of K, and registers data on the rising edge of K and the rising edge of /K. /K is ideally 180 degrees out of phase with K. All synchronous inputs must meet setup and hold times around the clock rising edges. Output Clock: This clock pair provides a user controlled means of tuning device output data. The rising edge of /C is used as the output timing reference for first output data. The rising edge of C is used as the output reference for second output data. Ideally, /C is 180 degrees out of phase with C. C and /C may be tied HIGH to force the use of K and /K as the output reference clocks instead of having to provide C and /C clocks. If tied HIGH, C and /C must remain HIGH and not be toggled during device operation. Synchronous Echo Clock Outputs. The rising edges of these outputs are tightly matched to the synchronous data outputs and can be used as a data valid indication. These signals run freely and do not stop when Q tristates. Output Impedance Matching Input: This input is used to tune the device outputs to the system data bus impedance. DQ and CQ output impedance are set to 0.2 x RQ, where RQ is a resistor from this bump to ground. This pin cannot be connected directly to GND or left unconnected. /DLL DLL Disable: When LOW, this input causes the DLL to be bypassed for stable low frequency operation. TMS TDI TCK IEEE 1149.1 Test Inputs: 1.8V I/O levels. These balls may be left Not Connected if the JTAG function is not used in the circuit. IEEE 1149.1 Clock Input: 1.8V I/O levels. This pin must be tied to VSS if the JTAG function is not used in the circuit. TDO IEEE 1149.1 Test Output: 1.8V I/O level. VREF HSTL Input Reference Voltage: Nominally VDDQ/2. Provides a reference voltage for the input buffers. VDD Power Supply: 1.8V nominal. See DC Characteristics and Operating Conditions for range. VDDQ Power Supply: Isolated Output Buffer Supply. Nominally 1.5V. 1.8V is also permissible. See DC Characteristics and Operating Conditions for range. VSS Power Supply: Ground NC No Connect: These signals are internally connected and appear in the JTAG scan chain as the logic level applied to the ball sites. These signals may be connected to ground to improve package heat dissipation. Preliminary Data Sheet M16783EJ1V0DS 7 µPD44325082, 44325092, 44325182, 44325362 Block Diagram [µPD44325082] 21 ADDRESS /R ADDRESS /W 21 REGISTRY & LOGIC K /K /W /NW0 /R ARRAY 16 MUX 16 OUTPUT BUFFER & LOGIC MEMORY OUTPUT SELECT REGISTRY 21 2 x 16 OUTPUT REGISTER 16 SENSE AMPS DATA WRITE DRIVER D0 to D7 8 WRITE REGISTER /NW1 8 Q0 to Q7 2 CQ, /CQ K K /K K C, /C OR K, /K [µPD44325092] 21 ADDRESS /R ADDRESS /W 21 REGISTRY & LOGIC K /K /W /BW0 18 OUTPUT BUFFER /R ARRAY 18 MUX OUTPUT SELECT & LOGIC MEMORY OUTPUT REGISTER REGISTRY D0 to D8 21 2 x 18 SENSE AMPS 18 WRITE DRIVER DATA WRITE REGISTER 9 9 Q0 to Q8 2 CQ, /CQ K K /K K C, /C OR K, /K [µPD44325182] 20 ADDRESS /R ADDRESS /W 20 REGISTRY & LOGIC K /K /W /BW0 ARRAY 36 MUX /R 36 8 18 Q0 to Q17 2 CQ, /CQ K /K OUTPUT BUFFER MEMORY OUTPUT SELECT & LOGIC 20 2 x 36 OUTPUT REGISTER 36 REGISTRY SENSE AMPS DATA WRITE DRIVER 18 WRITE REGISTER /BW1 D0 to D17 K K Preliminary Data Sheet M16783EJ1V0DS C, /C OR K, /K µPD44325082, 44325092, 44325182, 44325362 [µPD44325362] 19 ADDRESS /R ADDRESS /W 19 REGISTRY & LOGIC K /K /W 72 OUTPUT BUFFER ARRAY 72 MUX OUTPUT SELECT & LOGIC D0 to D35 MEMORY OUTPUT REGISTER REGISTRY 19 2 x 72 SENSE AMPS 36 72 WRITE DRIVER DATA WRITE REGISTER /BW0 /BW1 /BW2 /BW3 36 Q0 to Q35 2 CQ, /CQ /R K K /K K C, /C OR K, /K Power-on Sequence The following two timing charts show the recommended power-on sequence, i.e., when starting the clock after VDD/VDDQ stable and when starting the clock before VDD/VDDQ stable. 1. Clock starts after VDD/VDDQ stable VDD/VDDQ VDD/VDDQ Stable (< ±0.1 V DC per 50 ns) Clock Clock Start 1,024 cycles or more Stable Clock Start Normal Operation 2. Clock starts before VDD/VDDQ stable VDD/VDDQ VDD/VDDQ Stable (< ±0.1 V DC per 50 ns) Clock Clock Start 30 ns (MIN.) DLL Reset or DLL Off Preliminary Data Sheet M16783EJ1V0DS 1,024 cycles or more Start Normal Operation Stable Clock 9 µPD44325082, 44325092, 44325182, 44325362 Truth Table Operation WRITE cycle CLK /R /W D or Q L→H X L Data in Load address, input write data on Input data DA (A+0) DA (A+1) consecutive K and /K rising edge Input clock K( t ) ↑ /K( t ) ↑ L→H READ cycle L X Data out Load address, output data on Output data QA (A+0) QA (A+1) consecutive C and /C rising edge Output clock /C(t+1) ↑ C(t+2) ↑ NOP (No operation) STANDBY(Clock stopped) L→H H H D=X or Q=High-Z Stopped X X Previous state Remarks 1. H : High level, L : Low level, × : don’t care, ↑ : rising edge. 2. Data inputs are registered at K and /K rising edges. Data outputs are delivered at C and /C rising edges except if C and /C are HIGH then Data outputs are delivered at K and /K rising edges. 3. All control inputs in the truth table must meet setup/hold times around the rising edge (LOW to HIGH) of K. All control inputs are registered during the rising edge of K. 4. This device contains circuitry that will ensure the outputs will be in high impedance during power-up. 5. Refer to state diagram and timing diagrams for clarification. 6. It is recommended that K = /(/K) = C = /(/C) when clock is stopped. This is not essential but permits most rapid restart by overcoming transmission line charging symmetrically. 10 Preliminary Data Sheet M16783EJ1V0DS µPD44325082, 44325092, 44325182, 44325362 Byte Write Operation [µPD44325082] Operation Write D0 to D7 Write D0 to D3 Write D4 to D7 Write nothing K /K /NW0 /NW1 L→H – 0 0 – L→H 0 0 L→H – 0 1 – L→H 0 1 L→H – 1 0 – L→H 1 0 L→H – 1 1 – L→H 1 1 Remarks 1. H : High level, L : Low level, → : rising edge. 2. Assumes a WRITE cycle was initiated. /NW0 and /NW1 can be altered for any portion of the BURST WRITE operation provided that the setup and hold requirements are satisfied. [µPD44325092] Operation Write D0 to D8 Write nothing K /K /BW0 L→H – 0 – L→H 0 L→H – 1 – L→H 1 Remarks 1. H : High level, L : Low level, → : rising edge. 2. Assumes a WRITE cycle was initiated. /BW0 can be altered for any portion of the BURST WRITE operation provided that the setup and hold requirements are satisfied. [µPD44325182] K /K /BW0 /BW1 Write D0 to D17 Operation L→H – 0 0 – L→H 0 0 Write D0 to D8 L→H – 0 1 – L→H 0 1 Write D9 to D17 L→H – 1 0 – L→H 1 0 Write nothing L→H – 1 1 – L→H 1 1 Remarks 1. H : High level, L : Low level, → : rising edge. 2. Assumes a WRITE cycle was initiated. /BW0 and /BW1 can be altered for any portion of the BURST WRITE operation provided that the setup and hold requirements are satisfied. Preliminary Data Sheet M16783EJ1V0DS 11 µPD44325082, 44325092, 44325182, 44325362 [µPD44325362] K /K /BW0 /BW1 /BW2 /BW3 Write D0 to D35 Operation L→H – 0 0 0 0 – L→H 0 0 0 0 Write D0 to D8 L→H – 0 1 1 1 – L→H 0 1 1 1 Write D9 to D17 L→H – 1 0 1 1 – L→H 1 0 1 1 L→H – 1 1 0 1 – L→H 1 1 0 1 L→H – 1 1 1 0 – L→H 1 1 1 0 L→H – 1 1 1 1 – L→H 1 1 1 1 Write D18 to D26 Write D27 to D35 Write nothing Remarks 1. H : High level, L : Low level, → : rising edge. 2. Assumes a WRITE cycle was initiated. /BW0 to /BW3 can be altered for any portion of the BURST WRITE operation provided that the setup and hold requirements are satisfied. Bus Cycle State Diagram LOAD NEW WRITE ADDRESS AT /K Always LOAD NEW READ ADDRESS /R = L /W = L WRITE DOUBLE AT /K Always READ DOUBLE /R = L /W = L /W = H /R = H /W = H WRITE PORT NOP /R = H Supply voltage provided Power UP Supply voltage provided READ PORT NOP R_Init = 0 Remarks 1. The address is concatenated with 1 additional internal LSB to facilitate burst operation. The address order is always fixed as: xxx...xxx+0, xxx...xxx+1. Bus cycle is terminated at the end of this sequence (burst count = 2). 2. Read and write state machines can be active simultaneously. 3. State machine control timing sequence is controlled by K. 12 Preliminary Data Sheet M16783EJ1V0DS µPD44325082, 44325092, 44325182, 44325362 Electrical Specifications Absolute Maximum Ratings Parameter Supply voltage Symbol Conditions MIN. TYP. MAX. Unit VDD –0.5 +2.5 V VDDQ –0.5 VDD V Input voltage VIN –0.5 VDD + 0.5 (2.5 V MAX.) V Input / Output voltage VI/O –0.5 VDDQ + 0.5 (2.5 V MAX.) V Operating ambient temperature TA 0 70 °C Storage temperature Tstg –55 +125 °C Output supply voltage Caution Exposing the device to stress above those listed in Absolute Maximum Ratings could cause permanent damage. The device is not meant to be operated under conditions outside the limits described in the operational section of this specification. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Recommended DC Operating Conditions (TA = 0 to 70 °C) Parameter Supply voltage Symbol Conditions MIN. TYP. MAX. Unit Note VDD 1.7 1.9 V Output supply voltage VDDQ 1.4 VDD V 1 High level input voltage VIH (DC) VREF + 0.1 VDDQ + 0.3 V 1, 2 Low level input voltage VIL (DC) –0.3 VREF – 0.1 V 1, 2 Clock input voltage VIN –0.3 VDDQ + 0.3 V 1, 2 Reference voltage VREF 0.68 0.95 V MAX. Unit Note Notes 1. During normal operation, VDDQ must not exceed VDD. 2. Power-up: VIH ≤ VDDQ + 0.3 V and VDD ≤ 1.7 V and VDDQ ≤ 1.4 V for t ≤ 200 ms Recommended AC Operating Conditions (TA = 0 to 70 °C) Parameter Symbol Conditions MIN. TYP. High level input voltage VIH (AC) VREF + 0.2 – V 1 Low level input voltage VIL (AC) – VREF – 0.2 V 1 Note 1. Overshoot: VIH (AC) ≤ VDD + 0.7 V for t ≤ TKHKH/2 Undershoot: VIL (AC) ≥ – 0.5 V for t ≤ TKHKH/2 Control input signals may not have pulse widths less than TKHKL (MIN.) or operate at cycle rates less than TKHKH (MIN.). Preliminary Data Sheet M16783EJ1V0DS 13 µPD44325082, 44325092, 44325182, 44325362 DC Characteristics (TA = 0 to 70°C, VDD = 1.8 ± 0.1 V) Parameter Symbol Test condition MIN. TYP. MAX. x8, x9 x18 Unit x36 Input leakage current ILI –2 – +2 µA I/O leakage current ILO –2 – +2 µA Operating supply current IDD mA (Read Write cycle) Note VIN ≤ VIL or VIN ≥ VIH, –E40 750 1,050 1,250 II/O = 0 mA –E50 650 900 1,050 Cycle = MAX. Standby supply current ISB1 (NOP) VIN ≤ VIL or VIN ≥ VIH, –E40 400 II/O = 0 mA –E50 350 mA Cycle = MAX. High level output voltage VOH(Low) |IOH| ≤ 0.1 mA VOH Low level output voltage Note1 VDDQ – 0.2 – VDDQ VDDQ/2–0.12 – VDDQ/2+0.12 VSS – 0.2 VDDQ/2–0.12 – VDDQ/2+0.12 VOL(Low) IOL ≤ 0.1 mA VOL Note2 V 3,4 3,4 V 3,4 3,4 Notes 1. Outputs are impedance-controlled. | IOH | = (VDDQ/2)/(RQ/5) for values of 175 Ω ≤ RQ ≤ 350 Ω. 2. Outputs are impedance-controlled. IOL = (VDDQ/2)/(RQ/5) for values of 175 Ω ≤ RQ ≤ 350 Ω. 3. AC load current is higher than the shown DC values. 4. HSTL outputs meet JEDEC HSTL Class I and Class II standards. Capacitance (TA = 25 °C, f = 1MHz) Parameter Symbol Test conditions MIN. TYP. MAX. Unit Input capacitance(Address, Control) CIN VIN = 0 V 4 5 pF Input / Output capacitance(D, Q) CI/O VI/O = 0 V 6 7 pF Clock Input capacitance Cclk Vclk = 0 V 5 6 pF Remark These parameters are periodically sampled and not 100% tested. 14 Preliminary Data Sheet M16783EJ1V0DS µPD44325082, 44325092, 44325182, 44325362 AC Characteristics (TA = 0 to 70 °C, VDD = 1.8 ± 0.1 V) AC Test Conditions Input waveform (Rise / Fall time ≤ 0.3 ns) 1.25 V 0.75 V Test Points 0.75 V 0.25 V Output waveform Test Points VDDQ / 2 VDDQ / 2 Output load condition Figure 1. External load at test VDDQ / 2 0.75 V 50 Ω VREF ZO = 50 Ω SRAM 250 Ω ZQ Preliminary Data Sheet M16783EJ1V0DS 15 µPD44325082, 44325092, 44325182, 44325362 Read and Write Cycle Parameter -E40 -E50 (250 MHz) (200 MHz) Symbol Unit Note MIN. MAX. MIN. MAX. 4.0 8.4 5.0 8.4 ns 1 2 Clock Average Clock cycle time (K, /K, C, /C) TKHKH Clock phase jitter (K, /K, C, /C) TKC var – 0.2 – 0.2 ns Clock HIGH time (K, /K, C, /C) TKHKL 1.6 – 2.0 – ns ns Clock LOW time (K, /K, C, /C) TKLKH 1.6 – 2.0 – Clock to /clock (K→/K., C→/C.) TKH /KH 1.8 – 2.2 – ns Clock to /clock (/K→K., /C→C.) T /KHKH 1.8 – 2.2 – ns Clock to data clock 200 to 250 MHz TKHCH 0 1.8 – – ns (K→C., /K→/C.) 167 to 200 MHz 0 2.3 0 2.3 133 to 167 MHz 0 2.8 0 2.8 < 133 MHz 0 3.55 0 3.55 DLL lock time (K, C) TKC lock 1,024 – 1,024 – Cycle K static to DLL reset TKC reset 30 – 30 – ns TCHQV – 0.45 – 0.45 ns 3 Output Times C, /C HIGH to output valid C, /C HIGH to output hold TCHQX – 0.45 – – 0.45 – ns TCHCQV – 0.45 – 0.45 ns C, /C HIGH to echo clock hold TCHCQX – 0.45 – – 0.45 – ns CQ, /CQ HIGH to output valid TCQHQV – 0.3 – 0.35 ns 4 CQ, /CQ HIGH to output hold TCQHQX – 0.3 – – 0.35 – ns 4 C, /C HIGH to echo clock valid C HIGH to output High-Z TCHQZ – 0.45 – 0.45 ns C HIGH to output Low-Z TCHQX1 – 0.45 – – 0.45 – ns Address valid to K rising edge TAVKH 0.35 – 0.4 – ns 5 Control inputs (/R, /W) valid to K rising TIVKH 0.35 – 0.4 – ns 5 TDVKH 0.35 – 0.4 – ns 5 K rising edge to address hold TKHAX 0.35 – 0.4 – ns 5 K rising edge to control inputs (/R, /W) hold TKHIX 0.35 – 0.4 – ns 5 K, /K rising edge to data inputs and TKHDX 0.35 – 0.4 – ns 5 Setup Times edge Data inputs and write data select inputs (/BWx, /NWx) valid to K, /K rising edge Hold Times write data select inputs (/BWx, /NWx) hold 16 Preliminary Data Sheet M16783EJ1V0DS µPD44325082, 44325092, 44325182, 44325362 Notes 1. The device will operate at clock frequencies slower than TKHKH(MAX.). 2. Clock phase jitter is the variance from clock rising edge to the next expected clock rising edge. 3. VDD slew rate must be less than 0.1 V DC per 50 ns for DLL lock retention. DLL lock time begins once VDD and input clock are stable. It is recommended that the device is kept inactive during these cycles. 4. Echo clock is very tightly controlled to data valid / data hold. By design, there is a ± 0.1 ns variation from echo clock to data. The data sheet parameters reflect tester guardbands and test setup variations. 5. This is a synchronous device. All addresses, data and control lines must meet the specified setup and hold times for all latching clock edges. Remarks 1. This parameter is sampled. 2. Test conditions as specified with the output loading as shown in AC Test Conditions unless otherwise noted. 3. Control input signals may not be operated with pulse widths less than TKHKL (MIN.). 4. If C, /C are tied HIGH, K, /K become the references for C, /C timing parameters. 5. VDDQ is 1.5 V DC. Preliminary Data Sheet M16783EJ1V0DS 17 µPD44325082, 44325092, 44325182, 44325362 Read and Write Timing READ WRITE 1 2 READ WRITE 3 4 READ WRITE 5 NOP 6 7 WRITE NOP 8 9 10 K TKHKL TKLKH TKH/KH T/KHKH TKHKH /K /R TKHIX TIVKH /W Address A0 A1 TAVKH Data in A2 A3 A4 A5 A6 D50 D51 TKHAX TKHAX TAVKH D11 D30 D10 D31 TDVKH TKHDX Data out D60 D61 TDVKH TKHDX Q00 Q01 TCHQX TCHQX Q20 Q40 TCHQZ TCHQV CQ TCHCQX TCHCQV /CQ TKHCH TCHCQX TCHCQV C TKHKL TKLKH TKHKH TKH/KH T/KHKH TKHCH /C Remarks 1. Q00 refers to output from address A0+0. Q01 refers to output from the next internal burst address following A0,i.e.,A0+1. 2. Outputs are disable (high impedance) one clock cycle after a NOP. 3. In this example, if address A0=A1, data Q00=D10, Q01=D11. Write data is forwarded immediately as read results. 18 Preliminary Data Sheet M16783EJ1V0DS Q41 TCQHQV TCHQX1 TCHQV Q21 µPD44325082, 44325092, 44325182, 44325362 JTAG Specification These products support a limited set of JTAG functions as in IEEE standard 1149.1. Test Access Port (TAP) Pins Pin name TCK Pin assignments Description Test Clock Input. 2R All input are captured on the rising edge of TCK and all outputs propagate from the falling edge of TCK. TMS 10R TDI 11R Test Mode Select. This is the command input for the TAP controller state machine. Test Data Input. This is the input side of the serial registers placed between TDI and TDO. The register placed between TDI and TDO is determined by the state of the TAP controller state machine and the instruction that is currently loaded in the TAP instruction. TDO 1R Test Data Output. Output changes in response to the falling edge of TCK. This is the output side of the serial registers placed between TDI and TDO. Remark The device does not have TRST (TAP reset). The Test-Logic Reset state is entered while TMS is held high for five rising edges of TCK. The TAP controller state is also reset on the SRAM POWER-UP. JTAG DC Characteristics (TA = 0 to 70°C, VDD = 1.8 ± 0.1 V, unless otherwise noted) Parameter Symbol Conditions MIN. TYP. MAX. Unit JTAG Input leakage current ILI 0 V ≤ VIN ≤ VDD –5.0 – +5.0 µA JTAG I/O leakage current ILO 0 V ≤ VIN ≤ VDDQ , –5.0 – +5.0 µA Note Outputs disabled JTAG input high voltage VIH 1.3 – VDD+0.3 V JTAG input low voltage VIL –0.3 – +0.5 V JTAG output high voltage JTAG output low voltage VOH1 | IOHC | = 100 µA 1.6 – – V VOH2 | IOHT | = 2 mA 1.4 – – V VOL1 IOLC = 100 µA – – 0.2 V VOL2 IOLT = 2 mA – – 0.4 V Preliminary Data Sheet M16783EJ1V0DS 19 µPD44325082, 44325092, 44325182, 44325362 JTAG AC Test Conditions Input waveform (Rise / Fall time ≤ 1 ns) 1.8 V 0.9 V Test Points 0.9 V 0.9 V Test Points 0.9 V 0V Output waveform Output load Figure 2. External load at test VTT = 0.9 V 50 Ω ZO = 50 Ω TDO 20 pF 20 Preliminary Data Sheet M16783EJ1V0DS µPD44325082, 44325092, 44325182, 44325362 JTAG AC Characteristics (TA = 0 to 70 °C) Parameter Symbol Conditions MIN. TYP. MAX. Unit 100 – – ns Note Clock Clock cycle time tTHTH Clock frequency fTF – – 10 MHz Clock high time tTHTL 40 – – ns Clock low time tTLTH 40 – – ns TCK low to TDO unknown tTLOX 0 – – ns TCK low to TDO valid tTLOV – – 20 ns TDI valid to TCK high tDVTH 10 – – ns TCK high to TDI invalid tTHDX 10 – – ns tMVTH 10 – – ns tCS 10 – – ns tTHMX 10 – – ns tCH 10 – – ns Output time Setup time TMS setup time Capture setup time Hold time TMS hold time Capture hold time JTAG Timing Diagram tTHTH TCK tTLTH tTHTL tMVTH TMS tTHMX tDVTH TDI tTHDX tTLOX tTLOV TDO Preliminary Data Sheet M16783EJ1V0DS 21 µPD44325082, 44325092, 44325182, 44325362 Scan Register Definition (1) Register name Instruction register Description The instruction register holds the instructions that are executed by the TAP controller when it is moved into the run-test/idle or the various data register state. The register can be loaded when it is placed between the TDI and TDO pins. The instruction register is automatically preloaded with the IDCODE instruction at power-up whenever the controller is placed in test-logic-reset state. Bypass register The bypass register is a single bit register that can be placed between TDI and TDO. It allows serial test data to be passed through the RAMs TAP to another device in the scan chain with as little delay as possible. ID register The ID Register is a 32 bit register that is loaded with a device and vendor specific 32 bit code when the controller is put in capture-DR state with the IDCODE command loaded in the instruction register. The register is then placed between the TDI and TDO pins when the controller is moved into shift-DR state. Boundary register The boundary register, under the control of the TAP controller, is loaded with the contents of the RAMs I/O ring when the controller is in capture-DR state and then is placed between the TDI and TDO pins when the controller is moved to shift-DR state. Several TAP instructions can be used to activate the boundary register. The Scan Exit Order tables describe which device bump connects to each boundary register location. The first column defines the bit’s position in the boundary register. The second column is the name of the input or I/O at the bump and the third column is the bump number. Scan Register Definition (2) Register name Bit size Unit Instruction register 3 bit Bypass register 1 bit ID register 32 bit Boundary register 109 bit ID Register Definition Part number Organization ID [31:28] vendor revision no. ID [27:12] part no. ID [11:1] vendor ID no. ID [0] fix bit µPD44325082 4M x 8 XXXX 0000 0000 0100 1001 00000010000 1 µPD44325092 4M x 9 XXXX 0000 0000 0100 1010 00000010000 1 µPD44325182 2M x 18 XXXX 0000 0000 0100 1011 00000010000 1 µPD44325362 1M x 36 XXXX 0000 0000 0100 1100 00000010000 1 22 Preliminary Data Sheet M16783EJ1V0DS µPD44325082, 44325092, 44325182, 44325362 SCAN Exit Order Bit no. Signal name x8 x9 x18 x36 Bump Bit Signal name ID no. x8 x9 x18 Bump Bit Signal name Bump x36 ID no. x8 X9 x18 x36 ID 1 /C 6R 37 NC NC NC D15 10D 73 NC NC NC Q28 2C 2 C 6P 38 NC NC NC Q15 9E 74 Q4 Q5 Q11 Q20 3E 3 A 6N 39 NC NC Q7 Q7 10C 75 D4 D5 D11 D20 2D 4 A 7P 40 NC NC D7 D7 11D 76 NC NC NC D29 2E 5 A 7N 41 NC NC NC D16 9C 77 NC NC NC Q29 1E 6 A 7R 42 NC NC NC Q16 9D 78 NC NC Q12 Q21 2F 7 A 8R 43 Q3 Q4 Q8 Q8 11B 79 NC NC D12 D21 3F 8 A 8P 44 D3 D4 D8 D8 11C 80 NC NC NC D30 1G 9 A 9R 45 NC NC NC D17 9B 81 NC NC NC Q30 1F NC NC NC Q17 10B 82 Q5 Q6 Q13 Q22 3G 11A 83 D5 D6 D13 D22 2G 10A 84 10 NC Q0 Q0 Q0 11P 46 11 NC D0 D0 D0 10P 47 12 NC NC NC D9 10N 48 13 NC NC NC Q9 9P 49 A 9A 85 NC NC NC D31 1J 14 NC NC Q1 Q1 10M 50 A 8B 86 NC NC NC Q31 2J 15 NC NC D1 D1 11N 51 A 7C 87 NC NC Q14 Q23 3K 16 NC NC NC D10 9M 52 A 6C 88 NC NC D14 D23 3J 17 NC NC NC Q10 9N 53 /R 8A 89 NC NC NC D32 2K 18 Q0 Q1 Q2 Q2 11L 54 /BW1 7A 90 NC NC NC Q32 1K 19 D0 D1 D2 D2 11M 55 /NW0 /BW0 /BW0 /BW0 7B 91 Q6 Q7 Q15 Q24 2L 20 NC NC NC D11 9L 56 K 6B 92 D6 D7 D15 D24 3L 21 NC NC NC Q11 10L 57 /K 6A 93 NC NC NC D33 1M 22 NC NC Q3 Q3 11K 58 /BW3 5B 94 NC NC NC Q33 1L 23 NC NC D3 D3 10K 59 /BW1 /BW2 5A 95 NC NC Q16 Q25 3N 24 NC NC NC D12 9J 60 /W 4A 96 NC NC D16 D25 3M 25 NC NC NC Q12 9K 61 A 5C 97 NC NC NC D34 1N 26 Q1 Q2 Q4 Q4 10J 62 A 4B 98 NC NC NC Q34 2M 27 D1 D2 D4 D4 11J 63 3A 99 Q7 Q8 Q17 Q26 3P 11H 64 VSS 2A 100 D7 D8 D17 D26 2N /CQ 1A 101 NC NC NC D35 2P NC NC NC Q35 1P 28 ZQ CQ A NC NC A VSS NC NC /NW1 NC A NC NC A A VSS NC /DLL 1H 29 NC NC NC D13 10G 65 30 NC NC NC Q13 9G 66 NC NC Q9 Q18 2B 102 31 NC NC Q5 Q5 11F 67 NC NC D9 D18 3B 103 A 3R 32 NC NC D5 D5 11G 68 NC NC NC D27 1C 104 A 4R 33 NC NC NC D14 9F 69 NC NC NC Q27 1B 105 A 4P 34 NC NC NC Q14 10F 70 NC NC Q10 Q19 3D 106 A 5P 35 Q2 Q3 Q6 Q6 11E 71 NC NC D10 D19 3C 107 A 5N 36 D2 D3 D6 D6 10E 72 NC NC NC D28 1D 108 A 5R 109 – Internal Preliminary Data Sheet M16783EJ1V0DS 23 µPD44325082, 44325092, 44325182, 44325362 JTAG Instructions Instructions EXTEST Description The EXTEST instruction allows circuitry external to the component package to be tested. Boundaryscan register cells at output pins are used to apply test vectors, while those at input pins capture test results. Typically, the first test vector to be applied using the EXTEST instruction will be shifted into the boundary scan register using the PRELOAD instruction. Thus, during the update-IR state of EXTEST, the output drive is turned on and the PRELOAD data is driven onto the output pins. IDCODE The IDCODE instruction causes the ID ROM to be loaded into the ID register when the controller is in capture-DR mode and places the ID register between the TDI and TDO pins in shift-DR mode. The IDCODE instruction is the default instruction loaded in at power up and any time the controller is placed in the test-logic-reset state. BYPASS The BYPASS instruction is loaded in the instruction register when the bypass register is placed between TDI and TDO. This occurs when the TAP controller is moved to the shift-DR state. This allows the board level scan path to be shortened to facilitate testing of other devices in the scan path. SAMPLE / PRELOAD SAMPLE / PRELOAD is a Standard 1149.1 mandatory public instruction. When the SAMPLE / PRELOAD instruction is loaded in the instruction register, moving the TAP controller into the captureDR state loads the data in the RAMs input and Q pins into the boundary scan register. Because the RAM clock(s) are independent from the TAP clock (TCK) it is possible for the TAP to attempt to capture the I/O ring contents while the input buffers are in transition (i.e., in a metastable state). Although allowing the TAP to sample metastable input will not harm the device, repeatable results cannot be expected. RAM input signals must be stabilized for long enough to meet the TAPs input data capture setup plus hold time (tCS plus tCH). The RAMs clock inputs need not be paused for any other TAP operation except capturing the I/O ring contents into the boundary scan register. Moving the controller to shift-DR state then places the boundary scan register between the TDI and TDO pins. SAMPLE-Z If the SAMPLE-Z instruction is loaded in the instruction register, all RAM Q pins are forced to an inactive drive state (high impedance) and the boundary register is connected between TDI and TDO when the TAP controller is moved to the shift-DR state. JTAG Instruction Coding IR2 IR1 IR0 Instruction 0 0 0 EXTEST 0 0 1 IDCODE 0 1 0 SAMPLE-Z 0 1 1 RESERVED 1 0 0 SAMPLE / PRELOAD 1 0 1 RESERVED 1 1 0 RESERVED 1 1 1 BYPASS Note 1. TRISTATE all Q pins and CAPTURE the pad values into a SERIAL SCAN LATCH. 24 Preliminary Data Sheet M16783EJ1V0DS Note 1 µPD44325082, 44325092, 44325182, 44325362 TAP Controller State Diagram 1 Test-Logic-Reset 0 1 0 1 Run-Test / Idle 1 Select-DR-Scan Select-IR-Scan 0 0 1 1 Capture-DR Capture-IR 0 0 0 Shift-DR 0 Shift-IR 1 1 1 1 Exit1-DR Exit1-IR 0 0 0 Pause-DR 0 Pause-IR 1 1 0 0 Exit2-DR Exit2-IR 1 1 Update-DR 1 Update-IR 0 1 0 Disabling the Test Access Port It is possible to use this device without utilizing the TAP. To disable the TAP Controller without interfering with normal operation of the device, TCK must be tied to VSS to preclude mid level inputs. TDI and TMS are designed so an undriven input will produce a response identical to the application of a logic 1, and may be left unconnected. But they may also be tied to VDD through a 1 kΩ resistor. TDO should be left unconnected. Preliminary Data Sheet M16783EJ1V0DS 25 26 Test Logic Operation (Instruction Scan) TCK TDI µPD44325082, 44325092, 44325182, 44325362 Run-Test/Idle Update-IR Exit1-IR Shift-IR Exit2-IR Pause-IR Exit1-IR Shift-IR Capture-IR New Instruction IDCODE Instruction Register state Select-IR-Scan Select-DR-Scan Run-Test/Idle Output Inactive TDO Test-Logic-Reset Contoroller state Preliminary Data Sheet M16783EJ1V0DS TMS Test Logic (Data Scan) TCK TDI 27 µPD44325082, 44325092, 44325182, 44325362 Test-Logic-Reset Select-IR-Scan Select-DR-Scan Run-Test/Idle Update-DR Exit1-DR Shift-DR Exit2-DR Pause-DR Exit1-DR Shift-DR IDCODE Instruction Instructin Register state Capture-DR Select-DR-Scan Output Inactive TDO Run-Test/Idle Controller state Preliminary Data Sheet M16783EJ1V0DS TMS µPD44325082, 44325092, 44325182, 44325362 Package Drawing 165-PIN PLASTIC FBGA (13x15) E w S B ZD ZE B 11 10 9 8 7 6 5 4 3 2 1 A D R P N M L K J H G F E D C B A w S A INDEX MARK A2 y1 S h A S e y S φb φx M A1 S AB This package drawing is a preliminary version. It may be changed in the future. 28 Preliminary Data Sheet M16783EJ1V0DS ITEM D E ZD ZE e h A A1 A2 b y x w y1 MILLIMETERS 13.00 15.00 1.50 0.50 1.00 0.60 1.40 0.40 1.00 0.50 0.08 0.08 0.15 0.20 µPD44325082, 44325092, 44325182, 44325362 Recommended Soldering Condition Please consult with our sales offices for soldering conditions of these products. Types of Surface Mount Devices µPD44325082F5-EQ2: 165-pin PLASTIC FBGA (13 x 15) µPD44325092F5-EQ2: 165-pin PLASTIC FBGA (13 x 15) µPD44325182F5-EQ2: 165-pin PLASTIC FBGA (13 x 15) µPD44325362F5-EQ2: 165-pin PLASTIC FBGA (13 x 15) Preliminary Data Sheet M16783EJ1V0DS 29 µPD44325082, 44325092, 44325182, 44325362 Revision History Edition/ Date 1st edition/ Page Type of This Previous edition edition Location Description (Previous edition → This edition) revision Throughout Throughout Modification Preliminary Product Information → Preliminary Data sheet Oct. 2004 F5-EQ1 → F5-EQ2 Package Code Deletion pp.3-6 pp.3-6 p.9 p.14 p.14 Addition −E60 (167MHz) and −E75 (133MHz) Pin Configurations Remark 2 has been added Power-on Sequence Power-on sequence has been added Modification DC Characteristics IDD (MAX.) MAX. x8, x9 x18 Unit MAX. x36 x8, x9 x18 Unit x36 −E40 850 900 1,030 mA −E40 750 1,050 1,250 mA −E50 720 760 −E50 650 870 900 1,050 DC Characteristics ISB1 (MAX.) MAX. x8, x9 x18 30 −E40 230 −E50 210 Unit MAX. x36 x8, x9 x18 mA Preliminary Data Sheet M16783EJ1V0DS −E40 400 −E50 350 Unit x36 mA µPD44325082, 44325092, 44325182, 44325362 NOTES FOR CMOS DEVICES 1 VOLTAGE APPLICATION WAVEFORM AT INPUT PIN Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the CMOS device stays in the area between VIL (MAX) and VIH (MIN) due to noise, etc., the device may malfunction. Take care to prevent chattering noise from entering the device when the input level is fixed, and also in the transition period when the input level passes through the area between VIL (MAX) and VIH (MIN). 2 HANDLING OF UNUSED INPUT PINS Unconnected CMOS device inputs can be cause of malfunction. If an input pin is unconnected, it is possible that an internal input level may be generated due to noise, etc., causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND via a resistor if there is a possibility that it will be an output pin. All handling related to unused pins must be judged separately for each device and according to related specifications governing the device. 3 PRECAUTION AGAINST ESD A strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it when it has occurred. Environmental control must be adequate. When it is dry, a humidifier should be used. It is recommended to avoid using insulators that easily build up static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work benches and floors should be grounded. The operator should be grounded using a wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with mounted semiconductor devices. 4 STATUS BEFORE INITIALIZATION Power-on does not necessarily define the initial status of a MOS device. Immediately after the power source is turned ON, devices with reset functions have not yet been initialized. Hence, power-on does not guarantee output pin levels, I/O settings or contents of registers. A device is not initialized until the reset signal is received. A reset operation must be executed immediately after power-on for devices with reset functions. 5 POWER ON/OFF SEQUENCE In the case of a device that uses different power supplies for the internal operation and external interface, as a rule, switch on the external power supply after switching on the internal power supply. When switching the power supply off, as a rule, switch off the external power supply and then the internal power supply. Use of the reverse power on/off sequences may result in the application of an overvoltage to the internal elements of the device, causing malfunction and degradation of internal elements due to the passage of an abnormal current. The correct power on/off sequence must be judged separately for each device and according to related specifications governing the device. 6 INPUT OF SIGNAL DURING POWER OFF STATE Do not input signals or an I/O pull-up power supply while the device is not powered. The current injection that results from input of such a signal or I/O pull-up power supply may cause malfunction and the abnormal current that passes in the device at this time may cause degradation of internal elements. Input of signals during the power off state must be judged separately for each device and according to related specifications governing the device. Preliminary Data Sheet M16783EJ1V0DS 31 µPD44325082, 44325092, 44325182, 44325362 QDR RAMs and Quad Data Rate RAMs comprise a new series of products developed by Cypress Semiconductor, Renesas, IDT, Micron Technology, Inc., NEC Electronics, and Samsung. • The information in this document is current as of October, 2004. The information is subject to change without notice. For actual design-in, refer to the latest publications of NEC Electronics data sheets or data books, etc., for the most up-to-date specifications of NEC Electronics products. Not all products and/or types are available in every country. Please check with an NEC Electronics sales representative for availability and additional information. • No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Electronics. 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