19-2697; Rev 0; 12/02 Low-Jitter 155MHz/622MHz Clock Generator Features ♦ Single +3.3V or +5.0V Supply ♦ Power Dissipation: 150mW at +3.3V Supply ♦ External VCO Center Frequencies (fVCO): 155MHz to 700MHz ♦ Reference Clock Frequencies: fVCO, fVCO/2, fVCO/4, fVCO/8, fVCO/32 ♦ Main Clock Output Frequency: fVCO ♦ Optional Output Clock Frequencies: fVCO, fVCO/2, fVCO/4, fVCO/8 ♦ Low Intrinsic Jitter: <0.4psRMS The MAX3672 operates from a single +3.3V or +5.0V supply and dissipates 150mW (typ) at 3.3V. The operating temperature range is -40°C to +85°C. Applications ♦ Loss-of-Lock Indicator ♦ PECL Clock Output Interface Ordering Information OC-12 to OC-192 SONET/WDM Transport Systems Clock Jitter Clean-Up and Frequency Synchronization PART TEMP RANGE PIN-PACKAGE MAX3672E/D -40°C to +85°C Dice* *Dice are designed to operate from -40° to +85°C, but are tested and guaranteed at TA = +25° only. Frequency Conversion System Clock Distribution Typical Application Circuit +3.3V 142Ω 155MHz REFCLK+ +3.3V VCCD 16:1 SERIALIZER 142Ω VCOIN+ VCO KVCO = 25kHz/V 155MHz MAX3892 MOUT- REFCLK- 142Ω MOUT+ 100Ω VCOIN- MAX3672 142Ω RSEL VSEL N.C. NSEL1 N.C. 332Ω NSEL2 VC 4700pF 0.01µF 500kΩ OPAMP- GSEL OPAMP+ 4700pF REPRESENTS A CONTROLLED-IMPEDANCE TRANSMISSION LINE. 500kΩ VFILTER 1000pF POLAR GND 3.3V SETUP FOR 10kHz LOOP BANDWIDTH ________________________________________________________________ Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. 1 MAX3672 General Description The MAX3672 is a low-jitter 155MHz/622MHz reference clock generator IC designed for system clock distribution and frequency synchronization in OC-48 and OC-192 SONET/SDH and WDM transmission systems. The MAX3672 integrates a phase/frequency detector, an operational amplifier (op amp), prescaler dividers, and input/output buffers. Using an external VCO, the MAX3672 can be configured easily as a phase-lock loop with bandwidth programmable from 30Hz to 10kHz. MAX3672 Low-Jitter 155MHz/622MHz Clock Generator ABSOLUTE MAXIMUM RATINGS Supply Voltage ......................................................-0.5V to +7.0V Voltage at C2+, C2-, THADJ, CTH, NSEL1, NSEL2, GSEL, LOL, RSEL, REFCLK-, REFCLK+, VSEL, VCOIN+, VCOIN-, VC, POLAR, PSEL1, PSEL2, COMP, OPAMP+, OPAMP- ..................................-0.5V to (VCC + 0.5V) Voltage at VFILTER .................................................-0.5V to +3.0V PECL Output Current (MOUT+, MOUT-, POUT+, POUT-).................................................56mA Operating Temperature Range ...........................-40°C to +85°C Storage Temperature Range. ............................-65°C to +160°C Die-Attach Process Temperature.....................................+400°C Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. DC ELECTRICAL CHARACTERISTICS (VCC = +3.3V ±10% or VCC = +5.0V ±10%, TA = -40°C to +85°C. Typical values are at VCC = +3.3V and TA = +25°C, unless otherwise noted.) (Note 1) PARAMETER Supply Current SYMBOL ICC CONDITIONS MIN (Note 2) TYP MAX UNITS 50 72 mA INPUT SPECIFICATIONS (REFCLK±, VCOIN±) Input High Voltage VIH VCC 1.16 VCC 0.88 V Input Low Voltage VIL VCC 1.81 VCC 1.48 V VCC 1.3 Input Bias Voltage V Common-Mode Input Resistance 7.2 11.5 17.5 kΩ Differential Input Resistance 12.0 21.0 32.5 kΩ mVP-P Differential Input Voltage Swing AC-coupled 300 1900 0°C to +85°C VCC 1.025 VCC 0.88 -40°C to 0°C VCC 1.085 VCC 0.88 0°C to +85°C VCC 1.81 VCC 1.62 -40°C to 0°C VCC 1.83 VCC 1.556 2.4 VCC V 0.4 V PECL OUTPUT SPECIFICATIONS Output High Voltage Output Low Voltage VOH V VOL V TTL SPECIFICATIONS 2 Output High Voltage VOH Sourcing 20µA Output Low Voltage VOL Sinking 2mA _______________________________________________________________________________________ Low-Jitter 155MHz/622MHz Clock Generator (VCC = +3.3V ±10% or VCC = +5.0V ±10%, TA = -40°C to +85°C. Typical values are at VCC = +3.3V and TA = +25°C, unless otherwise noted.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS OPERATIONAL AMPLIFIER SPECIFICATIONS (Note 3) Op Amp Output Voltage Range VCC = +3.3V ±10% 0.3 VCC 0.3 VCC = +5.0V ±10% 0.5 VCC 0.5 VO Op Amp Input Offset Voltage | VOS | Op Amp Open-Loop Gain 3 AOL 90 V mV dB PHASE FREQUENCY DETECTOR (PFD)/CHARGE-PUMP (CP) SPECIFICATIONS (Note 4) Full-Scale PFD/CP Output Current | IPD | PFD/CP Offset Current High gain 16.0 20 24.4 Low gain 4.0 5 6.2 High gain 0.80 Low gain 1.08 µA % | IPD | AC ELECTRICAL CHARACTERISTICS (VCC = +3.3V ±10% or VCC = +5.0V ±10%, TA = -40°C to +85°C. Typical values are at VCC = +3.3V and TA = +25°C, unless otherwise noted.) (Note 5) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS 700 MHz CLOCK OUTPUT SPECIFICATIONS Clock Output Frequency Optional Clock Output Frequency fVCO = 622MHz 622/311/ 155/78 fVCO = 155MHz 155/78/ 38/19 Clock Output Rise/Fall Time Measured from 20% to 80% Clock Output Duty Cycle (Note 6) 45 MHz 280 ps 55 % 1.14 µVRMS /√Hz NOISE SPECIFICATIONS Random Noise Voltage at LoopFilter Output VNOISE Spurious Noise Voltage at LoopFilter Output Power-Supply Rejection at LoopFilter Output Freq > 1kHz (Note 7) (Note 8) PSR (Note 9) 50 µVRMS 30 dB REFERENCE CLOCK INPUT SPECIFICATIONS 622/ 155/78/ 19 Reference Clock Frequency Reference Clock Duty Cycle 30 700 MHz 70 % _______________________________________________________________________________________ 3 MAX3672 DC ELECTRICAL CHARACTERISTICS (continued) MAX3672 Low-Jitter 155MHz/622MHz Clock Generator AC ELECTRICAL CHARACTERISTICS (continued) (VCC = +3.3V ±10% or VCC = +5.0V ±10%, TA = -40°C to +85°C. Typical values are at VCC = +3.3V and TA = +25°C, unless otherwise noted.) (Note 5) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS PLL SPECIFICATIONS PLL Jitter Transfer Bandwidth BW (Note 10) 30 FJITTER ≤ BW (Note 11) Jitter Transfer Peaking 10,000 Hz 0.1 dB OPAMP SPECIFICATION Unity-Gain Bandwidth 7 MHz VCO INPUT SPECIFICATIONS VCO Input Frequency VCO Input Slew Rate fVCO 622/155 0.5 700 MHz V/ns Specifications at -40°C are guaranteed by design and characterization. Measured with PECL outputs unterminated. OPAMP specifications met with 10kΩ load to ground or 5kΩ load to VCC (POLAR = 0 and POLAR = VCC). PFD/CP currents are measured from pins OPAMP+ to OPAMP-. See Table 4 for gain settings. AC characteristics are guaranteed by design and characterization. Measured with 50% VCO input duty cycle. Random noise voltage at op amp output with 800kΩ resistor connected between VC and OPAMP-, PFD/CP gain (KPD) = 5µA/UI, and POLAR = 0. Measured with the PLL open loop and no REFCLK or VCO input. Note 8: Spurious noise voltage due to PFD/CP output pulses measured at op amp output with R1 = 800kΩ, KPD = 5µA/UI, and compare frequency 400 times greater than the higher-order pole frequency (see the Design Procedure section). Note 9: PSR measured with a 100mVP-P sine wave on VCC in a frequency range from 100Hz to 2MHz. External resistors R1 matched to within 1%, external capacitors C1 matched to within 10%. Measured closed loop with PLL bandwidth set to 200Hz. Note 10: The PLL 3dB bandwidth is adjusted from 30Hz to 10kHz by changing external components R1 and C1, by selecting the internal programmable divider ratio and phase-detector gain. Measured with VCO gain of 150ppm/V and C1 limited to 2.2µF. Note 11: When input jitter frequency is above PLL transfer bandwidth (BW), the jitter transfer function rolls off at -20dB/decade. Note 1: Note 2: Note 3: Note 4: Note 5: Note 6: Note 7: 4 _______________________________________________________________________________________ Low-Jitter 155MHz/622MHz Clock Generator 5.0V 3.3V 40 30 20 -40 -20 0 20 40 60 80 0 MAX3672 toc02 270 260 250 240 230 220 210 200 190 180 170 160 150 140 BW = 1kHz -10 SUPPLY REJECTION (dB) SUPPLY CURRENT (mA) 60 EDGE SPEED 20% TO 80% (ps) MAX3672 toc01 70 50 POWER-SUPPLY REJECTION vs. FREQUENCY OUTPUT CLOCK EDGE SPEED vs. TEMPERATURE 155.52 667 -20 -30 LOOP FILTER OUTPUT -40 -50 -60 -40 -20 TEMPERATURE (°C) 0 20 40 60 80 1k 10k 667MHz CLOCK OUTPUT 100k 1M 10M FREQUENCY (Hz) TEMPERATURE (°C) 155MHz CLOCK OUTPUT MAX3672 toc04 200mV/div MAX3672 toc03 SUPPLY CURRENT vs. TEMPERATURE MAX3672 toc05 200mV/div 500ps/div 2ns/div _______________________________________________________________________________________ 5 MAX3672 Typical Operating Characteristics (TA = +25°C, unless otherwise noted.) Low-Jitter 155MHz/622MHz Clock Generator MAX3672 Pad Description PAD NAME FUNCTION 1 C2+ Positive Filter Input. External capacitor connected between C2+ and C2- used for setting the higher order pole frequency (see the Setting the Higher-Order Poles section). 2 C2- Negative Filter Input. External capacitor connected between C2+ and C2- used for setting the higher order pole frequency (see the Setting the Higher-Order Poles section). 3, 10, 16 VCCD Positive Digital Supply Voltage 4 THADJ Threshold Adjust Input. Used to adjust the loss-of-lock threshold (see the LOL Setup section). 5, 12, 18, 27, 33 GND Ground 6 CTH Threshold Capacitor Input. Connect capacitor connected between CTH and ground to control the loss-of-lock conditions (see the LOL Setup section). 7 NSEL1 Divide Selector 1 Input. Three-level pin used to set the frequency divider ratio (N2) (Table 3). 8 NSEL2 Divide Selector 2 Input. Three-level pin used to set the frequency divider ratio (N2) (Table 3). 9 GSEL Gain Selector Input. Three-level pin used to set the phase-detector gain (Kpd) (Table 4). 11 LOL Loss of Lock. LOL signals a TTL low when the reference frequency differs from the VCO frequency. LOL signals a TTL high when the reference frequency equals the VCO frequency. 13 RSEL Reference Clock Selector Input. Three-level pin used to set the pre-divider ratio (N3) for the input reference clock (Table 1). 14 REFCLK+ Positive Reference Clock Input, PECL 15 REFCLK- Negative Reference Clock Input, PECL 17 VSEL 19 POUT- Negative Optional Clock Output, PECL 20 POUT+ Positive Optional Clock Output, PECL 21, 24 VCCO Positive Supply Voltage for PECL Outputs 22 MOUT- Negative Main Clock Output, PECL 23 MOUT+ Positive Main Clock Output, PECL 25 VCOIN- Negative VCO Clock Input, PECL 26 VCOIN+ Positive VCO Clock Input, PECL 28 VFILTER Optional Noise Filter. Connect an external capacitor to reduce PECL output noise (see the Typical Application Circuit). 29 VC 30 POLAR Polarity Control of Op Amp Input. POLAR = GND for VCOs with positive-gain transfer. POLAR = VCC for VCOs with negative-gain transfer. 31 PSEL1 Optional Clock Selector 1 Input. Sets the divider ratio for the optional clock output (Table 5). 32 PSEL2 Optional Clock Selector 2 Input. Sets the divider ratio for the optional clock output (Table 5). 34 VCCA Positive Analog Supply Voltage for the Charge Pump and Op Amp COMP Compensation Control Input. Op Amp Compensation Reference Control Input. COMP = GND for VCOs whose control pin is VCC referenced. COMP = VCC for VCOs whose control pin is GND referenced. 35 6 VCO Clock Selector Input. Three-level pin used to set the pre-divider ratio (N1) for the input VCO clock (Table 2). Control Voltage Output. The voltage output from the op amp that controls the VCO. 36 OPAMP- Negative Op Amp Input, POLAR = GND 37 OPAMP+ Positive Op Amp Input, POLAR = GND _______________________________________________________________________________________ Low-Jitter 155MHz/622MHz Clock Generator C1 R1 C1 R1 POLAR OPAMP- R3 VCO KVCO C3 LOL THADJ CTH VC COMP OPAMP LOL REFCLK+ DIV (N3) 1/2/8 PECL REFCLK- OPAMP+ DIV (N2) PFD/CP Kpd GSEL RSEL C2VSEL DIV (N1) 4/8/32 DIV (N2) C2+ VCOIN+ VCOIN- MOUT+ PECL PECL MOUT- MAX3672 DIVIDER CONTROL LOGIC NSEL1 NSEL2 Detailed Description The MAX3672 contains all the blocks needed to form a PLL except for the VCO, which must be supplied separately. The MAX3672 consists of input buffers for the reference clock and VCO, input and output clock-divider circuitry, LOL detection circuitry phase detector, gaincontrol logic, a phase-frequency detector and charge pump, an op amp, and PECL output buffers. This device is designed to clean up the noise on the reference clock input and provide a low-jitter system clock output. This device also supports frequency conversion. Input Buffer for Reference Clock and VCO The MAX3672 contains differential inputs for the reference clock and the VCO. These high impedance inputs can be DC-coupled and are internally biased with so POUT+ DIV 1/2/4/8 PSEL1 PECL POUT- PSEL2 VFILTER that they can be AC-coupled (Figure 1 in the Interface Schematic section). A single-ended VCO or reference clock can also be applied. Input and Output Clock-Divider Circuitry The pre-dividers scale the input frequencies of the VCO and reference clock. Clock-divider ratios N1 and N3 must be chosen so that the output frequencies of the pre-dividers are equal. The maximum allowable predivider output frequency is 77.76MHz (Table 1). The main dividers (N2) facilitate tuning the loop bandwidth by setting the frequency divider ratio. The divider control logic can be programmed to divide from 1 to 256 in binary multiples (Table 3). The POUT output buffer is preceded by a clock divider that scales the main clock output by 1, 2, 4, or 8 to provide an optional clock. _______________________________________________________________________________________ 7 MAX3672 Functional Diagram MAX3672 Low-Jitter 155MHz/622MHz Clock Generator LOL Detection Circuitry The MAX3672 incorporates a loss-of-lock (LOL) monitor that consists of an XOR gate, filter, and comparator with adjustable threshold (see the LOL Setup section). A loss-of-lock condition is signaled with a TTL low when the reference clock frequency differs from the VCO frequency. Phase-Frequency Detector and Charge Pump The phase-frequency detector incorporated into the MAX3672 produces pulses proportional to the phase difference between the reference clock and the VCO input. The charge pump converts this pulse train to a current signal that is fed to the op amp. The phase detector gain can be set to either 5µA/UI or 20µA/UI with the GSEL input (Table 4). Op Amp The op amp is used to form an active PLL loop filter capable of driving the VCO control voltage input. Using the POLAR input, the op amp input polarity can be selected to work with VCOs having positive or negative gaintransfer functions. The COMP pin selects the op amp internal compensation. Connect COMP to ground if the VCO control voltage is VCC referenced. Connect COMP to VCC if the VCO control voltage is ground referenced. Design Procedure Setting Up the VCO and Reference Clock The MAX3672 accepts a range of reference clock and VCO frequencies. The RSEL and VSEL inputs must be set so that the output frequencies of the reference clock and VCO pre-dividers are equal. Table 1 shows the divider ratios and pre-divider output frequencies for various reference clock and VCO frequencies. Setting the Loop Bandwidth To eliminate jitter present on the reference clock, the proper selection of loop bandwidth is critical. If the total output jitter is dominated by the noise at the reference clock input, then lowering the loop bandwidth will reduce system jitter. The loop bandwidth (K) is a function of the VCO gain (KVCO), the gain of the phase detector (KPD), the loop filter resistor (R1), and the total feedback-divider ratio (N = N1 ✕ N2). The loop bandwidth of the MAX3672 can be approximated by: K= KPDR1K VCO 2πN For stability, a zero must be added to the loop in the form of resistor R 1 in series with capacitor C 1 (see the Functional Diagram). The location of the zero can be approximated as: fZ = 1 2πR1C1 Because of the second-order nature of the PLL jitter transfer, peaking will occur and is proportional to fZ/K. For certain applications, it may be desirable to limit jitter peaking in the PLL passband region to less than 0.1dB. This can be achieved by setting fZ ≤ K/100. A more detailed analysis of the loop filter is located in application note HFDN-13.0 on www.maxim-ic.com. Table 1. VCO and Reference Clock Setup 8 RSEL INPUT REFERENCECLOCK DIVIDER N3 PRE-DIVIDER OUTPUT FREQUENCY (MHz) FVOC (MHz) FREF (MHz) VSEL INPUT VCO DIVIDER N1 622.08 622.08 OPEN 8 GND 8 77.76 622.08 155.52 OPEN 8 OPEN 2 77.76 622.08 77.76 OPEN 8 VCC 1 77.76 622.08 19.44 GND 32 VCC 1 19.44 155.52 622.08 — — — — –– 155.52 155.52 OPEN 8 GND 8 19.44 155.52 77.76 VCC 4 OPEN 2 38.88 155.52 19.44 OPEN 8 VCC 1 19.44 _______________________________________________________________________________________ Low-Jitter 155MHz/622MHz Clock Generator INPUT PIN VSEL VCO DIVIDER N1 INPUT PIN RSEL REFERENCECLOCK DIVIDER N3 VCC 4 VCC 1 OPEN 8 OPEN 2 GND 32 GND 8 Table 3. Divider Logic Setup INPUT PIN NSEL1 INPUT PIN NSEL2 f HOP = 1 2π(20kΩ)(C2 ) or by adding a lowpass filter, consisting of R3 and C3, directly on the VCO tuning port, which produces a pole at: f HOP = DIVIDER RATIO N2 VCC VCC 1 OPEN VCC 2 GND VCC 4 VCC OPEN 8 OPEN OPEN 16 GND OPEN 32 VCC GND 64 OPEN GND 128 GND GND 256 Table 4. Phase Detector Gain Setup INPUT PIN GSEL Kpd (µA/UI) OPEN or VCC 20 GND 5 Table 5. Optional Clock Setup INPUT PIN PSEL1 The HOP can be implemented either by providing a compensation capacitor C2, which produces a pole at: 1 2πR3 C3 Using R3 and C3 might be preferable for filtering more noise in the PLL, but it might still be necessary to provide filtering through C2 when using large values of R1 and N1 ✕ N2, to prevent clipping in the op amp. Setting the Optional Output The MAX3672 optional clock output can be set to binary subdivisions of the main clock frequency. The PSEL1 and PSEL2 pins control the binary divisions. Table 5 shows the pin configuration and possible divider ratios. Applications Information PECL Interfacing The MAX3672 outputs (MOUT+, MOUT-, POUT+, POUT-) are designed to interface with PECL signal levels and should be biased appropriately. Proper termination requires an external circuit that provides a Thevenin equivalent of 50Ω to VCC - 2.0V and controlled-impedance transmission lines. To ensure best performance, the differential outputs must have balanced loads. If the optional clock output is not used, the output can be left floating to save power. INPUT PIN PSEL2 VCO TO POUT DIVIDER RATIO VCC VCC 1 Layout GND VCC 2 The MAX3672 performance can be significantly affected by circuit board layout and design. Use good highfrequency design techniques, including minimizing ground inductance and using fixed-impedance transmission lines on the reference and VCO clock signals. Power-supply decoupling should be placed as close to the die as possible. Take care to isolate the input from the output signals to reduce feedthrough. VCC GND 4 GND GND 8 Setting the Higher-Order Poles Spurious noise is generated by the phase detector switching at the compare frequency, where fCOMPARE = fVCO/(N1 ✕ N2). Reduce the spurious noise from the digital phase detector by placing a higher-order pole (HOP) at a frequency much less than the compare frequency. The HOP should, however, be placed high enough in frequency that it does not decrease the overall loop-phase margin and impact jitter peaking. These two conditions can be met by selecting the HOP frequency to be (K ✕ 4) < fHOP < fCOMPARE, where K is the loop bandwidth. VCO Selection The MAX3672 is designed to accommodate a wide range of VCO gains, positive or negative transfer slopes, and VCC-referenced or ground-referenced control voltages. These features allow the user a wide range of options in VCO selection; however, the proper VCO must be selected to allow the clock generator circuitry to operate at the optimum levels. When selecting _______________________________________________________________________________________ 9 MAX3672 Table 2. RSEL and VSEL Settings MAX3672 Low-Jitter 155MHz/622MHz Clock Generator Interface Schematics VCC VCC VCC - 1.3V 10.5kΩ 10.5kΩ OUT+ REFLCK+ OUT- REFLCK- MAX3672 MAX3672 Figure 2. Output Interface Figure 1. Input Interface a VCO, the user needs to take into account the VCO’s phase noise and modulation bandwidth. Phase noise is important because the phase noise above the PLL bandwidth is dominated by the VCO noise performance. The modulation bandwidth of the VCO contributes an additional higher-order pole (HOP) to the system and should be greater than the HOP set with the external filter components. LOL Noise Performance Optimization 60kΩ THADJ 0.6V CTH 60kΩ REFCLK VCO Figure 3. Loss-of-Lock Indicator 10 MAX3672 Depending on the application, there are many different ways to optimize the PLL performance. The following are general guidelines to improve the noise on the system output clock. 1) If the reference clock noise dominates the total system-clock output jitter, then decreasing the loop bandwidth (K) reduces the output jitter. 2) If the VCO noise dominates the total system clock output jitter, then increasing the loop bandwidth (K) reduces the output jitter. 3) Smaller total divider ratio (N1 ✕ N2), lower HOP, and smaller R1 reduce the spurious output jitter. 4) Smaller R1 reduces the random noise due to the op amp. ______________________________________________________________________________________ Low-Jitter 155MHz/622MHz Clock Generator PAD PAD COORDINATES (µm) X Y 1 50.8 1557.3 2 50.8 1408.8 3 50.8 1179.3 4 50.8 1028.1 5 50.8 874.2 6 50.8 720.4 7 50.8 566.5 8 50.8 412.6 9 50.8 258.7 10 266.8 50.8 11 420.7 50.8 12 574.6 50.8 13 728.5 50.8 14 882.4 50.8 15 1036.2 50.8 16 1190.1 50.8 17 1344 50.8 18 1549.2 50.8 19 1792.2 256 20 1792.2 409.9 21 1792.2 563.8 22 1792.2 717.7 23 1792.2 871.6 24 1792.2 1025.4 25 1792.2 1179.3 26 1792.2 1333.2 27 1792.2 1530.3 28 1792.2 1692.3 29 1565.4 1692.3 30 1411.5 1692.3 31 1257.6 1692.3 32 1103.7 1692.3 33 893.2 1692.3 34 685.3 1692.3 35 531.4 1692.3 36 377.5 1692.3 37 223.6 1692.3 LOL Setup The LOL output indicates if the PLL has locked onto the reference clock using an XOR gate and comparator. The comparator threshold can be adjusted with THADJ, and the XOR gate output can be filtered with a capacitor between CTH and ground (Figure 3). When the voltage at pin CTH exceeds the voltage at pin THADJ, then the LOL output goes low and indicates that the PLL is not locked. Note that excessive jitter on the reference clock input at frequencies above the loop bandwidth may degrade LOL functionality. The user can set the amount of frequency or phase difference between VCO and reference clock at which LOL indicates an out-of-lock condition. The frequency difference is called the beat frequency. The CTH pin can be connected to an external capacitor, which sets the lowpass filter frequency to approximately fL = 1 2πC TH 60kΩ This lowpass filter frequency should be set about 10 times lower then the beat frequency to ensure that the filtered signal at CTH does not drop below the THADJ threshold voltage. Internal comparisons occur at the pre-divider output frequency (see Table 1 for VCO and reference clock setup). For example, assume the predivider output frequency is 19.44MHz. For a 1ppm sensitivity, the minimum beat frequency is 19Hz, and the filter should be set to 1.9Hz. Set CTH to 1.36uF. The voltage at THADJ will determine the level at which the LOL output flags. THADJ is set to a default value of 0.6V which corresponds to a 45° phase difference. This value can be overridden by applying the desired threshold voltage to the THADJ input. The range of THADJ is 0V (0°) to 2.4V (180°). ______________________________________________________________________________________ 11 MAX3672 Bond Pad Coordinates C2+ 1 C2- 2 32 31 30 29 28 27 GND 26 VCOIN+ VCOIN- Package Information For the latest package outline information, go to www.maxim-ic.com/packages. VCCD 3 25 THADJ 4 24 VCCD GND 5 23 MOUT+ CTH 6 22 MOUT- (1.930mm) 19 POUT- 13 14 15 16 17 18 GND 11 12 GND 9 VSEL GSEL VCCD POUT+ REFCLK- VCCD 20 RSEL 21 8 REFCLK+ 7 LOL NSEL1 NSEL2 10 Chip Information PROCESS: GST2 SUBSTRATE CONNECTED TO GND DIE THICKNESS: 14 mils VFILTER 33 VC 34 PSEL1 PSEL2 35 POLAR GND 36 COMP OPAMP- 37 VCCA OPAMP+ Chip Topography VCCD MAX3672 Low-Jitter 155MHz/622MHz Clock Generator 0.076" 0.080" (2.032mm) Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 12 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 © 2002 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.