AD ADRF6655

Broadband Up/Downconverting Mixer with
Integrated Fractional-N PLL and VCO
ADRF6655
The programmable divider is controlled by an Σ-Δ modulator
(SDM). The modulus of the SDM can be programmed between
1 and 2047.
FEATURES
Broadband active mixer with integrated fractional-N PLL
RF input frequency range: 100 MHz to 2500 MHz
Internal LO frequency range: 1050 MHz to 2300 MHz
Flexible IF output interface
Input P1dB: 12 dBm
Input IP3: 29 dBm
Noise figure (SSB): 12 dB
Voltage conversion gain: 6 dB
Matched 200 Ω output impedance
SPI serial interface for PLL programming
40-lead 6 mm × 6 mm LFCSP
The broadband, active mixer employs a bias adjustment to allow
for enhanced IP3 performance at the expense of increased supply
current. The mixer provides an input IP3 exceeding 25 dBm
with 12 dB single sideband NF under typical conditions. The IIP3
can be boosted to ~29 dBm with roughly 20 mA of additional
supplied current. The mixer provides a typical voltage conversion
gain of 6 dB with a 200 Ω differential IF output impedance. The
IF output can be externally matched to support upconversion over
a limited frequency range.
The ADRF6655 is fabricated using an advanced silicon-germanium
BiCMOS process. It is packaged in a 40-lead, exposed-paddle,
Pb-free, 6 mm × 6 mm LFCSP. Performance is specified over a
−40°C to +85°C temperature range.
GENERAL DESCRIPTION
The ADRF6655 is a high dynamic range active mixer with
integrated PLL and VCO. The synthesizer uses a programmable
integer-N/fractional-N PLL to generate a local oscillator input
to the mixer. The PLL reference input is nominally 20 MHz. The
reference input can be divided by or multiplied by and then
applied to the PLL phase detector. The PLL can support input
reference frequencies from 10 MHz to 160 MHz. The phase
detector output controls a charge pump whose output is integrated
in an off-chip loop filter. The loop filter output is then applied to an
integrated VCO. The VCO output at 2 × fLO is then applied to a local
oscillator (LO) divider as well as to a programmable PLL divider.
FUNCTIONAL BLOCK DIAGRAM
GND
GND
VCCLO
NC
NC
GND
36
35
34
33
32
31
30 GND
LOSEL
LON 37
ADRF6655
29 IP3SET
BUFFER
28 GND
LOP 38
27 VCCMIX
FRACTION MODULUS
REG
GND 11
BUFFER
INTEGER
REG
MUX
DATA 12
SPI
INTERFACE
LE 14
N COUNTER
21 TO 123
GND 15
25 INN
LOSEL
THIRD-ORDER
FRACTIONAL
INTERPOLATOR
VCO
CORE
PRESCALER
24 GND
×2
REFIN 6
GND 7
÷2
23 GND
MUX
–
PHASE
+ FREQUENCY
DETECTOR
TEMP
SENSOR
÷4
3.3V LDO
MUXOUT 8
CHARGE PUMP
250µA,
500µA (DEFAULT),
750µA,
1000µA
1
2
3
VCC1
DECL1
CP
4
5
22 VCCV2I
21 GND
2.5V LDO
9
10
VCO LDO
39
40
16
17
18
19
20
GND RSET DECL2 VCC2 VTUNE DECL3 NC VCCLO OUTN OUTP GND
08817-001
CLK 13
26 INP
DIVIDER
÷2 OR ÷3
Figure 1.
Rev. 0
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responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
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www.analog.com
Fax: 781.461.3113
©2010 Analog Devices, Inc. All rights reserved.
ADRF6655
TABLE OF CONTENTS
Features .............................................................................................. 1 Output Matching and Biasing................................................... 19 General Description ......................................................................... 1 Input Matching ........................................................................... 20 Functional Block Diagram .............................................................. 1 IP3SET Linearization Feature ................................................... 21 Revision History ............................................................................... 2 CDAC Linearization Feature .................................................... 21 Specifications..................................................................................... 3 External LO Interface ................................................................ 21 Timing Characteristics ................................................................ 5 Using an External VCO ............................................................. 22 Absolute Maximum Ratings............................................................ 6 ADRF6655 Control Software ........................................................ 23 ESD Caution .................................................................................. 6 PLL Loop Filter Design ............................................................. 23 Pin Configuration and Function Despcriptions .......................... 7 Register Structure ........................................................................... 24 Typical Performance Characteristics ............................................. 9 Device Programming ................................................................. 25 Downconversion........................................................................... 9 Initialization Sequence .............................................................. 25 Upconversion .............................................................................. 11 Register 0—Integer Divide Control ......................................... 26 PLL Characteristic ...................................................................... 12 Register 1—Modulus Divide Control ...................................... 27 Complimentary Cumulative Distribution Function (CCDF):
Downconversion, LO = 1100 MHz, RF = 900 MHz .............. 14 Register 2—Fractional Divide Control .................................... 27 Complimentary Cumulative Distribution Function (CCDF):
Downconversion, LO = 1700 MHz, RF = 1900 MHz ............ 15 Register 4—Charge Pump, PFD, and Reference
Path Control ................................................................................ 29 Complimentary Cumulative Distribution Function (CCDF):
Upconversion Distribution ....................................................... 16 Register 5—LO Path and Mixer Control................................. 31 Circuit Description ......................................................................... 17 PLL and VCO Block ................................................................... 17 RF Mixer Block ........................................................................... 17 Digital Interfaces ........................................................................ 18 Analog Interfaces ............................................................................ 19 Supply Connections ................................................................... 19 Register 3—Σ-Δ Modulator Dither Control ........................... 28 Register 6—VCO Control and PLL Enables ........................... 32 Register 7—External VCO Control ......................................... 33 Characterization Setups ................................................................. 34 Evaluation Board Layout and Thermal Grounding ................... 38 Outline Dimensions ....................................................................... 41 Ordering Guide .......................................................................... 41 Synthesizer Connections ........................................................... 19 REVISION HISTORY
2/10—Revision 0: Initial Version
Rev. 0 | Page 2 of 44
ADRF6655
SPECIFICATIONS
VCC = 5 V; ambient temperature (TA) = 25°C; REFIN = 20 MHz, phase frequency detector (PFD) frequency = 20 MHz, IF output loaded
into 4-to-1 transformer matched to a 50 Ω system, unless otherwise noted.
Table 1.
Parameter
RF INPUT FREQUENCY RANGE
IF OUTPUT FREQUENCY RANGE
INTERNAL LO FREQUENCY RANGE
EXTERNAL LO FREQUENCY RANGE
MIXER
Input Return Loss
Output Return Loss
IF Output Impedance
Output Common Mode
Voltage Conversion Gain
Output Swing
LO-to-IF Output Leakage
DYNAMIC PERFORMANCE
Upconversion
Gain Flatness
Gain Temperature Coefficient
Output P1dB
Second-Order Output Intercept (IIP2)
Third-Order Output Intercept (IIP3)
Output Noise Spectral Density
Downconversion
Gain Flatness
Gain Temperature Coefficient
Input P1dB
Second-Order Input Intercept (IIP2)
Third-Order Input Intercept (IIP3)
SSB Noise Figure (NF)
SSB Noise Figure Under Blocking
Conditions
IF/2 Spurious
LO OUTPUT
Output Level
Test Conditions/Comments
Can be matched externally for improved return loss at higher
frequencies (see the Output Matching and Biasing section)
Divide-by-3 mode 1
Divide-by-2 mode1
Divide-by-2 mode 2
INP, INN; relative to 50 Ω, from 350 MHz to 2200 MHz using
TC1-1-13M+ balun 3
OUTP, OUTN; relative to 50 Ω out to 200 MHz using TC4-1W
output transformer option3
OUTP, OUTN
OUTP, OUTN; external pull-up balun or inductors required
IF output loaded into 200 Ω differential load
Can be improved using external filtering
IP3Set = 3.2 V
340 MHz RF input, 1200 MHz IF output using 1540 MHz
LO (see Figure 56 for output matching network)
Over ±50 MHz bandwidth for 1200 MHz output center
frequency
Average values from −40°C to +85°C
−5 dBm each tone
−5 dBm each tone, IP3SET = 3.2 V
−5 dBm each tone, IP3SET = open
IP3SET = 3.2 V, RF input terminated with 50 Ω
IP3SET = 3.2 V, RF input = −5 dBm, fLO = 1315 MHz with
fRF = 380 MHz applied, measured noise at fIF = 915 MHz
1880 MHz RF input, 140 MHz IF output using 1740 MHz LO
Over ±50 MHz bandwidth for 1880 MHz input center
frequency
Average values from −40°C to +85°C
IP3SET = 3.2 V
IP3SET = open
−5 dBm each tone
−5 dBm each tone, IP3SET = 3.2 V
−5 dBm each tone, IP3SET = open
IP3SET = 3.2 V
IP3SET = open
−5 dBm RF input blocker applied at 995 MHz, fLO = 1200 MHz,
noise measured at 5 MHz offset from IF output blocker
IP3SET = 3.2 V
IP3SET = open
−5 dBm RF input power
LOP, LON
1 × LO into a 50 Ω load, LO buffer enabled
Rev. 0 | Page 3 of 44
Min
100
LF
Typ
1050
1530
500
Max
2500
2200
Unit
MHz
MHz
1530
2300
2300
MHz
MHz
MHz
12
dB
12
dB
200
VPOS
6
2
−40
Ω
V
dB
V p-p
dBm
0.25
dB p-p
−10
11
60
31
28
−160
−155
mdB/°C
dBm
dBm
dBm
dBm
dBm/Hz
dBm/Hz
0.25
dB p-p
−10
14
12
50
27
26
14
12
mdB/°C
dBm
dBm
dBm
dBm
dBm
dB
dB
20.75
20.25
−65
dB
dB
dBc
−7
dBm
ADRF6655
Parameter
SYNTHESIZER SPECIFICATIONS
Fundamental VCO Sensitivity
Spurs
Reference/PFD Spurs
Phase Noise
LO Frequency = 1330 MHz
Integrated Phase Noise
LO Frequency = 1840 MHz
Integrated Phase Noise
PFD Frequency
REFERENCE CHARACTERISTICS
REFIN Input Frequency
REFIN Input Capacitance
REFIN Input Current
REFIN Input Sensitivity
MUXOUT Output Levels
CHARGE PUMP
Pump Current
Output Compliance Range
LOGIC INPUTS
VINH, Input High Voltage
VINL, Input Low Voltage
IINH/IINL, Input Current
CIN, Input Capacitance
POWER SUPPLIES
Voltage Range
Supply Current
Test Conditions/Comments
Synthesizer specifications referenced to 1 × LO 4
VCO tuning sensitivity before divide-by-2 or divide-by-3
Measured at LO output
fPFD/2
fPFD
2 × fPFD
4 × fPFD
PFD frequency = 20 MHz4
Min
Max
Unit
75
MHz/V
−95
−83
−85
−88
dBc
dBc
dBc
dBc
@ 10 kHz offset
@ 100 kHz offset
@ 1 MHz offset
@ 10 MHz offset
10 kHz to 40 MHz integration bandwidth
−85
−114
−138
−154
0.3
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
°rms
@ 10 kHz offset
@ 100 kHz offset
@ 1 MHz offset
@ 10 MHz offset
10 kHz to 40 MHz integration bandwidth
−83
−111
−136
−152
0.4
20
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
°rms
MHz
19.33
40
REFIN, MUXOUT
10
AC-coupled
VOL (lock detect output selected)
VOH (lock detect output selected)
CP
Charge pump current adjustable using Register 4 and/or
RSET (see Pin 5 description)
0.25
20
4
±100
1
160
3.3
0.25
2.7
500
MHz
pF
μA
V p-p
V
V
μA
1
2.8
V
1.4
0
3.3
0.7
V
V
μA
pF
5.25
V
CLK, DATA, LE
±1
3
VCC1, VCC2, VCCLO
4.75
LO output buffer disabled
PLL only
Normal TX mode, IP3SET = 3.2 V, fLO ≤1530 MHz (divide-by-3)
Normal TX mode, IP3SET = 3.2 V, fLO > 1530 MHz (divide-by-2)
Normal RX mode, IP3SET = open, fLO ≤ 1530 MHz (divide-by-3)
Normal RX mode, IP3SET = open, fLO > 1530 MHz (divide-by-2)
Power-down mode
1
Internal LO path divider programmed via serial interface. See the LO Signal Chain section for additional information.
2
See the External LO Interface section.
3
Improved return loss can be achieved using external matching. See the Circuit Description section for more details.
Measured on standard evaluation board with 1.5 kHz loop filter (C13 = 47 nF, C14 = 0.1 μF, C15 = 4.7 μF, R9 = 270 Ω, R10 = 68 Ω).
4
Typ
Rev. 0 | Page 4 of 44
5
115
310
270
285
245
15
mA
mA
mA
mA
mA
mA
ADRF6655
TIMING CHARACTERISTICS
Table 2. Serial Interface Timing, VCC = 5 V ± 5%
Parameter
t1
t2
t3
t4
t5
t6
t7
Limit
20
10
10
25
25
10
20
Unit
ns minimum
ns minimum
ns minimum
ns minimum
ns minimum
ns minimum
ns minimum
Test Conditions/Comments
LE setup time
DATA to CLK setup time
DATA to CLK hold time
CLK high duration
CLK low duration
CLK to LE setup time
LE pulse width
t4
t5
CLK
t2
DATA
DB23 (MSB)
t3
DB22
DB2
(CONTROL BIT C3)
DB1
(CONTROL BIT C2)
DB0 (LSB)
(CONTROL BIT C1)
t7
t1
08817-002
t6
LE
Figure 2. Timing Diagram
Rev. 0 | Page 5 of 44
ADRF6655
ABSOLUTE MAXIMUM RATINGS
Table 3.
Parameter
Supply Voltage, VCC
Digital I/O CLK, DATA, LE
OUTP, OUTN
LOP, LON
INN, INP
DECL3 Using External Bias Option
θJA (Exposed Paddle Soldered Down)1
Maximum Junction Temperature
Operating Temperature Range
Storage Temperature Range
1
Rating
5.5 V
−0.3 V to +3.6 V
VCC
16 dBm
20 dBm
3.5 V
35°C/W
150°C
−40°C to +85°C
−65°C to +150°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
Per JDEC standard JESD 51-2. For information on optimizing thermal
impedance, see the Evaluation Board Layout and Thermal Grounding
section.
Rev. 0 | Page 6 of 44
ADRF6655
31 GND
32 NC
33 NC
34 VCCLO
35 GND
36 GND
37 LON
38 LOP
39 VTUNE
40 DECL3
PIN CONFIGURATION AND FUNCTION DESPCRIPTIONS
VCO
LDO
VCC1 1
30 GND
ADRF6655
CP
WIDEBAND
UP/DOWN
CONVERTER
3.3V
LDO
DECL1 2
PD +
CHARGE
PUMP
3
PFD
29 IP3SET
28 GND
GND 4
27 VCCMIX
VCO
BAND
AND
CURRENT
CAL/SET
RSET 5
REFIN 6
6
VCO
CORE
6
MUX
÷2 OR ÷3
26 INP
25 INN
×2
MUX
PROGRAMMABLE
DIVIDER
÷2 OR ÷4
GND 7
ENABLE
PRESCALER
24 GND
MUXOUT 8
THIRD-ORDER
SDM
GND 20
OUTP 19
OUTN 18
INTEGER
LE 14
CLK 13
DATA 12
GND 11
NC = NO CONNECT
21 GND
MODULUS
SERIAL
PORT
VCCLO 17
FRACTION
NC 16
VCC2 10
22 VCCV2I
08817-003
2.5V
LDO
GND 15
DECL2 9
23 GND
Figure 3. Pin Configuration
Table 4. Pin Function Descriptions
Pin No.
1
Mnemonic
VCC1
2
DECL1
3
4, 7, 11, 15,
20, 21, 23,
24, 28, 30,
31, 35, 36
CP
GND
Description
Power Supply for Internal 3.3 V LDO. The power supply voltage range is 4.75 V to 5.25 V. Supply pin should
be decoupled with 100 pF and 0.1 μF capacitors located close to the pin.
Decoupling Node for 3.3 V LDO. Pin should be decoupled with 100 pF, 0.1 μF, and 10 μF capacitors
located close to the pin.
Charge Pump Output Pin. Connect this pin to VTUNE through the loop filter.
Ground. Connect these pins to a low impedance ground plane.
Rev. 0 | Page 7 of 44
ADRF6655
Pin No.
5
Mnemonic
RSET
6
REFIN
8
MUXOUT
9
DECL2
10
VCC2
12
13
DATA
CLK
14
LE
16, 32, 33
17, 34
NC
VCCLO
18,19
22
OUTN, OUTP
VCCV2I
25, 26
27
INN, INP
VCCMIX
29
37, 38
IP3SET
LON, LOP
39
VTUNE
40
DECL3
EPAD (EP)
Description
Charge Pump Current. The nominal charge pump current can be set to either 250 μA, 500 μA, 750 μA,
or 1 mA using DB10 and DB11 of Register 4 and by setting DB18 to 0 (internal reference current).
In this mode, no external RSET is required. If DB18 is set to 1, the four nominal charge pump currents
(INOMINAL) can be externally tweaked according to
⎡ 217 . 4 × I CP , BASE ⎤
RSET [Ω ] = ⎢
⎥ − 37 . 8
250
⎣
⎦
where ICP, BASE is the base charge pump current in μA.
For further details on the charge pump current,see the Register 4—Charge Pump, PFD, and Reference
Path Control section.
Reference Input. Nominal input level is 1 V p-p. Input range is 10 MHz to 160 MHz. This pin must be
ac-coupled.
Multiplexer Output. This output allows either a digital lock detect, a voltage proportional to temperature,
or a buffered, frequency-scaled reference signal to be accessed externally. The output is selected by
programming the appropriate bits in Register 4.
Decoupling Node for 2.5 V LDO. Pin should be decoupled with 100 pF, 0.1 μF, and 10 μF capacitors
located close to the pin.
Power Supply for Internal 2.5 V LDO. The power supply voltage range is 4.75 V to 5.25 V. Supply pin
should be decoupled with 100 pF and 0.1 μF capacitors located close to the pin.
Serial Data Input. The serial data input is loaded MSB first with the three LSBs being the control bits.
Serial Clock Input. This serial clock input is used to clock in the serial data to the registers. The data
is latched into the 24-bit shift register on the CLK rising edge. Maximum clock frequency is 20 MHz.
Load Enable. When the LE input pin goes high, the data stored in the shift registers is loaded into one
of the six registers, the relevant latch being selected by the first three control bits of the 24-bit word.
No Connection.
Power Supply for LO Path. The power supply voltage range is 4.75 V to 5.25 V. Supply pin should be
decoupled with 100 pF and 0.1 μF capacitors located close to the pin.
Mixer IF Outputs. These pins should be pulled to VCC with RF chokes.
Power Supply for Voltage to Current Input Stage. The power supply voltage range is 4.75 V to 5.25 V.
Supply pin should be decoupled with 100 pF and 0.1 μF capacitors located close to the pin.
Mixer RF Inputs. Differential RF Inputs. Internally matched to 50 Ω. This pin must be ac-coupled.
Power Supply for Mixer. The power supply voltage range is 4.75 V to 5.25 V. Supply pin should be
decoupled with 100 pF and 0.1 μF capacitors located close to the pin.
Connect Resistor to VCC to Adjust IP3.
Local Oscillator Input/Output. The internally generated 1 × fLO is available on these pins. When internal
LO generation is disabled, an external 2 × fLO or 3 × fLO (depending on divider selection) can be applied
to these pins. This pin must be ac-coupled.
VCO Control Voltage Input. This pin is driven by the output of the loop filter. Nominal input voltage
range on this pin is 1 V to 2.8 V.
Decoupling Node for VCO LDO. Connect a 100 pF capacitor and a 10 μF capacitor between this pin
and ground.
The exposed paddle should be soldered to a low impedance ground plane.
Rev. 0 | Page 8 of 44
ADRF6655
TYPICAL PERFORMANCE CHARACTERISTICS
VS = 5 V, TA = 25°C, PFD = 20 MHz, REFIN = 20 MHz, IP3SET = 3.2 V, unless otherwise noted.
DOWNCONVERSION
Measured using typical downconversion circuit schematic with high-side LO and 140 MHz IF output, unless otherwise noted.
+25°C
–40°C
+85°C
3
INPUT IP3 (dBm)
GAIN (dB)
2
1
0
–1
–2
–3
–5
900
1100
1300
1500
1700
1900
2100
08817-086
–4
2300
INPUT FREQUENCY (MHz)
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
900
INPUT IP2 (dBm)
NOISE FIGURE (dB)
18
16
14
1100
1300
1500
1700
1900
08817-123
12
10
900
2100
RF FREQUENCY (MHz)
100
95
90
85
80
75
70
65
60
55
50
45
40
35
30
25
20
900
IP3SET = 3.2V
IP3SET = OPEN
INPUT P1 dB (dBm)
24
22
20
18
16
14
12
–40
–35
–30
–25
–20
–15
–10
CW BLOCKER LEVEL (dBm)
–5
0
08817-104
NOISE FIGURE (dB)
26
–45
1700
1900
2100
+25°C
–40°C
+85°C
LOW-SIDE LO
HIGH-SIDE LO
1100
1300
1500
1700
1900
2100
2300
2500
Figure 8. Input IP2 vs. Input Frequency
30
10
–50
1500
INPUT FREQUENCY (MHz)
Figure 5. SSB Noise Figure vs. RF Frequency
28
1300
Figure 7. Input IP3 vs. Input Frequency
+25°C
–40°C
+85°C
IP3SET = 3.2V
IP3SET = OPEN
1100
INPUT FREQUENCY (MHz)
Figure 4. Conversion Gain vs. Input Frequency
20
+25°C
–40°C
+85°C
IP3SET = 3.2V
IP3SET = OPEN
08817-088
LOW-SIDE LO
HIGH-SIDE LO
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
900
+25°C
–40°C
+85°C
IP3SET = 3.2V
IP3SET = OPEN
1100
1300
1500
1700
1900
INPUT FREQUENCY (MHz)
Figure 9. Input P1dB vs. Input Frequency
Figure 6. SSB Noise Figure vs. CW Blocker Level
Rev. 0 | Page 9 of 44
2100
08817-089
4
08817-087
5
ADRF6655
–5
SUPPLY CURRENT (mA)
–10
–20
–25
–30
–35
–45
500
1000
1500
2000
2500
3000
FREQUENCY (MHz)
240
1.6
210
1.4
180
1.2
150
1.0
120
0.8
90
0.6
60
0.4
30
0.2
150
200
250
300
350
400
450
0
500
08817-124
100
LO OUTPUT POWER (dBm)
1.8
OUTPUT CAPACITANCE (pF)
270
FREQUENCY (MHz)
0
–1
–2
–3
–4
–5
–6
–7
–8
–9
–10
–11
–12
–13
–14
–15
–16
–17
–18
–19
–20
1050
1850
2050
2250
+25°C
–40°C
+85°C
1250
1450
1650
1850
2050
2250
Figure 14. LO Port Output Power vs. LO Frequency
–40
–20
+25°C
–40°C
+85°C
–50
+25°C
–40°C
+85°C
–25
LO-TO-IF OUTPUT LEAKAGE (dBm)
–45
–55
–60
–65
–70
–75
–80
–85
–90
–95
–30
–35
–40
–45
–50
–55
–60
–65
–70
–75
1250
1450
1650
1850
2050
2250
LO FREQUENCY (MHz)
–80
08817-090
–100
1050
1650
LO FREQUENCY (MHz)
Figure 11. IF Port Output Impedance vs. Frequency
LO-TO-RF INPUT LEAKAGE (dBm)
OUTPUT RESISTANCE (Ω)
2.0
50
1450
Figure 13. Supply Current vs. LO Frequency
300
0
1250
LO FREQUENCY (MHz)
Figure 10. RF Port Input Return Loss (S11) vs.
Frequency Measured through TC1-1-13M+
0
+25°C
–40°C
+85°C
IP3SET = 3.2V
IP3SET = OPEN
08817-092
0
08817-122
–40
1050 1150 1250 1350 1450 1550 1650 1750 1850 1950 2050 2150 2250
LO FREQUENCY (MHz)
Figure 12. LO-to-RF Input Port Leakage vs. LO Frequency
Figure 15. LO-to-IF Output Port Leakage vs. LO Frequency
Rev. 0 | Page 10 of 44
08817-014
S11 (dB)
–15
400
380
360
340
320
300
280
260
240
220
200
180
160
140
120
100
80
60
40
20
0
1050
08817-091
0
ADRF6655
UPCONVERSION
Measured using typical upconversion circuit schematic with high-side LO and 340 MHz RF input, unless otherwise noted.
5
35
+25°C
–40°C
+85°C
4
34
33
3
32
31
OUTPUT IP3 (dBm)
1
0
–1
–2
30
29
28
27
26
25
24
–3
23
22
–4
1010
1110
1210
1310
1410
1510
1610
OUTPUT FREQUENCY (MHz)
20
710
1010
1110 1210 1310 1410 1510 1610
Figure 19. Output IP3 vs. Output Frequency
0
+25°C
–40°C
+85°C
–20
OUTPUT P1dB (dBm)
–30
–40
–50
–60
–70
–80
–90
–100
1050 1150 1250 1350 1450 1550 1650 1750 1850 1950 2050 2150 2250
LO FREQUENCY (MHz)
08817-016
fLO – 2 × fRF SPURIOUS RESPONSE (dBc)
910
OUTPUT FREQUENCY (MHz)
Figure 16. Conversion Gain vs. Output Frequency
–10
810
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
710
+25°C
–40°C
+85°C
IP3SET = 3.2V
IP3SET = OPEN
810
910
1010
1110 1210 1310 1410 1510 1610
OUTPUT FREQUENCY (MHz)
08817-095
910
08817-093
810
08817-094
21
–5
710
Figure 20. Output P1dB vs. Output Frequency
Figure 17. fLO − 2 × fRF Spurious Response vs.
LO Frequency (Relative to IF Output Power)
–100
0
–10
NOISE SPECTRAL DENSITY (dBm/Hz)
+25°C
–40°C
+85°C
–20
–30
–40
–50
–60
–80
1050 1150 1250 1350 1450 1550 1650 1750 1850 1950 2050
LO FREQUENCY (MHz)
08817-105
–70
–110
–120
–130
–140
–150
–160
–170
710
810
910
1010 1110 1210 1310 1410 1510 1610
OUTPUT FREQUENCY (MHz)
Figure 21. Output Noise Spectral Density vs. Output Frequency
Figure 18. LO-to-IF Output Leakage vs. Frequency
Rev. 0 | Page 11 of 44
08817-121
GAIN (dB)
2
LO-TO-IF OUTPUT LEAKAGE (dBm)
+25°C
–40°C
+85°C
IP3SET = 3.2V
IP3SET = OPEN
ADRF6655
PLL CHARACTERISTIC
0
–10
–20
–30
–40
–50
–60
0
+25°C
–10°C
–40°C
+70°C
+85°C
LO REFERENCE PFD SPURS (dBc)
–10
LO = 2275MHz
–70
–80
–90
–100
–110
–120
–130
–140
–150
–160
LO = 1100MHz
–20
–30
–40
–50
–60
–70
–80
–90
100k
1M
10M
100M
–110
1050
OFFSET FREQUENCY (kHz)
+25°C
–10°C
–40°C
+70°C
+85°C
0.7
0.6
VTUNE (V)
1850
2050
2250
0.5
0.4
0.3
0.2
0
1050 1150 1250 1350 1450 1550 1650 1750 1850 1950 2050 2150 2250
LO FREQUENCY (MHz)
08817-022
0.1
3.0
2.9
2.8
2.7
2.6
2.5
2.4
2.3
2.2
2.1
2.0
1.9
1.8
1.7
1.6
1.5
1.4
1.3
1.2
1.1
1.0
+25°C
–40°C
+85°C
HIGH-SIDE LO
LOW-SIDE LO
1050 1150 1250 1350 1450 1550 1650 1750 1850 1950 2050 2150 2250
LO FREQUENCY (MHz)
Figure 23.10 kHz to 40 MHz Integrated Phase Noise vs. LO Frequency
Figure 26. Tuning Voltage vs. LO Frequency
2500
1.9
1: 10ms 2.289999883GHz
LO = 1100MHz, IP3SET = 3.2V
2000
1.8
1500
1000
1.7
VPTAT (V)
500
1
2.290G
–500
1.6
LO = 2300MHz, IP3SET = 3.2V
1.5
–1000
LO =2300MHz, IP3SET = OPEN
–1500
1.4
–2500
0
10
TIME (ms)
25
08817-120
–2000
1.3
–40 –30 –20 –10
0
10
20
30
40
50
60
70
TEMPERATURE (°C)
Figure 24. Lock Time for 10 MHz Step with 1.5 kHz Loop Filter
Figure 27. VPTAT MUXOUT Voltage vs. Temperature
Rev. 0 | Page 12 of 44
80
08817-097
INTEGRATED PHASE NOISE (°C rms)
1650
Figure 25. LO Reference/PFD Spurs vs. LO Frequency
1.0
0.8
1450
LO FREQUENCY (MHz)
Figure 22. Typical Fractional-N Phase Noise Plot
0.9
1250
08817-096
10k
08817-025
–170
1k
FREQUENCY DEVIATION FROM 2.29GHz (Hz)
+25°C
–40°C
+85°C
1 × PFD OFFSET
2 × PFD OFFSET
4 × PFD OFFSET
–100
08817-021
PHASE NOISE (dBc/Hz)
Measured using typical downconversion circuit schematic with high-side LO and 140 MHz IF output, loop filter = 1.5 kHz, unless
otherwise noted.
Figure 31. 70°C Spot Phase Noise vs. LO Frequency
–60
AVERAGE
–65
AVERAGE + 3 × ST DEV
–70
–75
10kHz OFFSET
–80
–85
–90
–95
–100
–105
100kHz OFFSET
–110
–115
–120
–125
–130
1MHz OFFSET
–135
–140
–145
–150
1050 1150 1250 1350 1450 1550 1650 1750 1850 1950 2050 2150 2250
–60
AVERAGE
–65
AVERAGE + 3 × ST DEV
–70
–75
10kHz OFFSET
–80
–85
–90
–95
–100
–105
100kHz OFFSET
–110
–115
–120
–125
1MHz OFFSET
–130
–135
–140
–145
–150
1050 1150 1250 1350 1450 1550 1650 1750 1850 1950 2050 2150 2250
LO FREQUENCY (MHz)
LO FREQUENCY (MHz)
08817-041
–60
AVERAGE
–65
AVERAGE + 3 × ST DEV
–70
–75
10kHz OFFSET
–80
–85
–90
–95
–100
–105
100kHz OFFSET
–110
–115
–120
–125
–130
1MHz OFFSET
–135
–140
–145
–150
1050 1150 1250 1350 1450 1550 1650 1750 1850 1950 2050 2150 2250
LO FREQUENCY (MHz)
Figure 32. 85°C Spot Phase Noise vs. LO Frequency
Figure 30. 25°C Spot Phase Noise vs. LO Frequency
Rev. 0 | Page 13 of 44
08817-042
08817-043
PHASE NOISE (dBc/Hz)
Figure 28. −40°C Spot Phase Noise vs. LO Frequency
Figure 29. −10°C Spot Phase Noise vs. LO Frequency
PHASE NOISE (dBc/Hz)
–60
AVERAGE
–65
AVERAGE + 3 × ST DEV
–70
–75
10kHz OFFSET
–80
–85
–90
–95
–100
–105
100kHz OFFSET
–110
–115
–120
–125
1MHz OFFSET
–130
–135
–140
–145
–150
1050 1150 1250 1350 1450 1550 1650 1750 1850 1950 2050 2150 2250
LO FREQUENCY (MHz)
PHASE NOISE (dBc/Hz)
PHASE NOISE (dBc/Hz)
LO FREQUENCY (MHz)
08817-039
–60
AVERAGE
–65
AVERAGE + 3 × ST DEV
–70
–75
10kHz OFFSET
–80
–85
–90
–95
–100
–105
–110
100kHz OFFSET
–115
–120
–125
–130
1MHz OFFSET
–135
–140
–145
–150
1050 1150 1250 1350 1450 1550 1650 1750 1850 1950 2050 2150 2250
08817-040
PHASE NOISE (dBc/Hz)
ADRF6655
ADRF6655
COMPLIMENTARY CUMULATIVE DISTRIBUTION FUNCTION (CCDF): DOWNCONVERSION, LO = 1100 MHz,
RF = 900 MHz
INPUT P1dB
2
4
6
8
10 12 14 16 18 20
GAIN (dB), INPUT P1dB (dBm)
100
95
90
85
80
75
70
65
60
55
50
45
40
35
30
25
20
15
10
5
0
0
DISTRIBUTION PERCENTAGE (%)
DISTRIBUTION PERCENTAGE (%)
+25°C
–40°C
+85°C
16
18
20
22
24
26
28
30
32
34
36
38
40
INPUT IP3 (dBm)
08817-107
14
+25°C
–40°C
+85°C
–95
–90
–85
–80
–75
–70
–65
6
8
10
12
14
100
95
90
85
80
75
70
65
60
55
50
45
40
35
30
25
20
15
10
5
0
–60
LO-TO-RF LEAKAGE (dBm)
16
18
+25°C
–40°C
+85°C
IP3SET = 3.2V
IP3SET = OPEN
0
VPTAT (V)
Figure 37. VPTAT MUXOUT Voltage
–55
–50
08817-098
DISTRIBUTION PERCENTAGE (%)
Figure 34. Rx Input IP3 CCDF
100
95
90
85
80
75
70
65
60
55
50
45
40
35
30
25
20
15
10
5
0
–100
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0
4
Figure 36. Noise Figure CCDF
IP3SET = 3.2V
IP3SET = OPEN
12
20
2
NOISE FIGURE (dB)
Figure 33. Gain and Input P1dB CCDF
100
95
90
85
80
75
70
65
60
55
50
45
40
35
30
25
20
15
10
5
0
+25°C
–40°C
+85°C
IP3SET = 3.2V
IP3SET = OPEN
08817-108
DISTRIBUTION PERCENTAGE (%)
+25°C
–40°C
+85°C
08817-109
100
IP3SET = 3.2V
95
IP3SET = OPEN
90
85
80
75
GAIN
70
65
60
55
50
45
40
35
30
25
20
15
10
5
0
–10 –8 –6 –4 –2 0
08817-106
DISTRIBUTION PERCENTAGE (%)
VS = 5 V, TA = 25°C, PFD = 20 MHz, REFIN = 20 MHz, IP3SET = open, as measured using typical downconversion circuit schematic with
high-side LO and 200 MHz IF output, unless otherwise noted.
Figure 35. Rx LO-to-RF Leakage CCDF
Rev. 0 | Page 14 of 44
ADRF6655
COMPLIMENTARY CUMULATIVE DISTRIBUTION FUNCTION (CCDF): DOWNCONVERSION, LO = 1700 MHz,
RF = 1900 MHz
INPUT P1dB
–5 –4 –3 –2 –1 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
GAIN, INPUT P1dB (dB, dBm)
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
NOISE FIGURE (dB)
Figure 41. Rx Noise Figure CCDF
100
IP3SET = 3.2V
95
IP3SET = OPEN
90
85
80
75
70
65
60
55
50
45
40
35
30
25
20
15
10
5
0
20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37
DISTRIBUTION PERCENTAGE (%)
+25°C
–40°C
+85°C
38 39 40
INPUT IP3 (dBm)
08817-034
DISTRIBUTION PERCENTAGE (%)
Figure 38. Gain and Input P1dB
+25°C
–40°C
+85°C
IP3SET = 3.2V
IP3SET = OPEN
–90
–80
–70
–60
100
95
90
85
80
75
70
65
60
55
50
45
40
35
30
25
20
15
10
5
0
0.5
+25°C
–40°C
+85°C
IP3SET = 3.2V
IP3SET = OPEN
0.7
0.9
1.1
1.3
1.5
1.7
1.9
VPTAT (V)
Figure 42. VPTAT MUXOUT Voltage
–50
LO-TO-RF LEAKAGE (dBm)
–40
–30
08817-099
DISTRIBUTION PERCENTAGE (%)
Figure 39. Rx Input IP3
100
95
90
85
80
75
70
65
60
55
50
45
40
35
30
25
20
15
10
5
0
–100
+25°C
–40°C
+85°C
IP3SET = 3.2V
IP3SET = OPEN
Figure 40. Rx LO-to-RF Leakage
Rev. 0 | Page 15 of 44
2.1
2.3
2.5
08817-038
GAIN
100
95
90
85
80
75
70
65
60
55
50
45
40
35
30
25
20
15
10
5
0
08817-110
+25°C
–40°C
+85°C
IP3SET = 3.2V
IP3SET = OPEN
DISTRIBUTION PERCENTAGE (%)
100
95
90
85
80
75
70
65
60
55
50
45
40
35
30
25
20
15
10
5
0
08817-033
DISTRIBUTION PERCENTAGE (%)
VS = 5 V, TA = 25°C, PFD = 20 MHz, REFIN = 20 MHz, IP3SET = open, as measured using typical downconversion circuit schematic with
high-side LO and 200 MHz IF output, unless otherwise noted.
ADRF6655
100
OUTPUT P1dB
0
2
4
6
8
10 12 14 16 18 20
Figure 43. Gain and Output P1dB CCDF, LO = 1220 MHz, RF = 340 MHz
70
60
50
OUTPUT P1dB
GAIN
40
30
20
IP3SET = 3.2V
IP3SET = OPEN
0
–10 –8 –6 –4 –2
0
2
4
6
8
10
12
14
16
18 20
GAIN (dB), OUTPUT P1dB (dBm)
Figure 46. Gain and Output P1dB CCDF, LO = 1840 MHz, RF = 340 MHz
100
100
IP3SET = 3.2V
IP3SET = OPEN
+25°C
–40°C
+85°C
80
70
60
50
40
30
20
10
+25°C
–40°C
+85°C
IP3SET = 3.2V
IP3SET = OPEN
90
DISTRIBUTION PERCENTAGE (%)
90
80
70
60
50
40
30
20
5
10
15
20
25
30
35
40
45
50
55
60
OUTPUT IP3 (dBm)
0
08817-101
0
0
IP3SET = 3.2V
IP3SET = OPEN
–80
–70
–60
–50
–40
–30
–20
–10
DISTRIBUTION PERCENTAGE (%)
+25°C
–40°C
+85°C
LO-TO-IF OUTPUT LEAKAGE (dBm)
15
20
25
30
35
40
45
50
55
60
Figure 47. Output IP3 CCDF, LO = 1840 MHz, RF = 340 MHz
08817-113
–90
10
OUTPUT IP3 (dBm)
Figure 44. Output IP3 CCDF, LO = 1220 MHz, RF = 340 MHz
100
95
90
85
80
75
70
65
60
55
50
45
40
35
30
25
20
15
10
5
0
–100
5
08817-103
10
0
100
95
90
85
80
75
70
65
60
55
50
45
40
35
30
25
20
15
10
5
0
–100
IP3SET = 3.2V
IP3SET = OPEN
–90
–80
–70
+25°C
–40°C
+85°C
–60
–50
–40
–30
LO-TO-IF PORT LEAKAGE (dBm)
Figure 45. LO-to-IF Output Leakage CCDF, LO = 1220 MHz, RF = 340 MHz
–20
–10
0
08817-114
DISTIBUTION PERCENTAGE (%)
80
10
GAIN (dB), OUTPUT P1dB (dBm)
DISTRIBUTION PERCENTAGE (%)
+25°C
–40°C
+85°C
90
08817-102
+25°C
–40°C
+85°C
IP3SET = 3.2V
IP3SET = OPEN
DISTRIBUTION PERCENTAGE (%)
100
95
90
85
80
75
GAIN
70
65
60
55
50
45
40
35
30
25
20
15
10
5
0
–10 –8 –6 –4 –2
08817-100
DISTRIBUTION PERCENTAGE (%)
COMPLIMENTARY CUMULATIVE DISTRIBUTION FUNCTION (CCDF): UPCONVERSION DISTRIBUTION
Figure 48. LO-to-IF Output Leakage CCDF, LO = 1840 MHz, RF = 340 MHz
Rev. 0 | Page 16 of 44
ADRF6655
CIRCUIT DESCRIPTION
The VCO operates at twice the LO frequency for improved
isolation. The nominal value of Kv is 75 MHz/V at the VCO
output. As the VCO band is changed from 0 to 63, the size of the
varactor is also changed, thus maintaining a roughly constant
Kv across the entire operating range.
The ADRF6655 can be subdivided into a PLL and VCO block
and a mixer block. A detailed circuit description for each block
follows.
PLL AND VCO BLOCK
The PLL and VCO block, shown in Figure 49, is made up of a
reference input block, a phase and frequency detector (PFD), a
charge pump, a VCO, and a divide-by-N modulus block. An
off-chip loop filter completes the loop.
RF MIXER BLOCK
LO
VCC
133Ω
LOOP
FILTER
OUTN
OUTP
VTUNE
÷2 OR ÷3
CP
REFIN
÷2
IP3SET
VCO
BAND
SELECT
×2
SIF
CDAC
PFD
TO MIXER
BLOCk
÷4
ADRF6655 MIXER BLOCK
V2I
RFIN
08817-053
CP
133Ω
Figure 51. Mixer Block
FRAC
MOD
INT
THIRD-ORDER
INTERPOLATOR
PRESCALER
08817-051
PROGRAMMABLE
DIVIDER
ADRF6655 PLL BLOCK DIAGRAM
Figure 49. PLL and VCO Block
The VCO is implemented with a single core that consists of 64
overlapping bands, as shown in Figure 50. The correct band is
selected automatically by the VCO band calibration circuit when
Register R0, Register R1, or Register R2 is programmed. The
VCO band selection takes roughly 4000 PFD cycles. During
calibration, an internal mux is used to disconnect the VCO input
voltage from the VTUNE pin and apply an internal reference
voltage for calibration. When calibration is complete, the VCO
input voltage is reconnected to the VTUNE pin and normal
PLL operation resumes.
2.4
2.0
LO Signal Chain
The LO chain consists of a mux that selects between the internal
VCO and an external LO source. The LO signal can then be
divided by 2 or divided by 3, providing a wide range of LO
frequencies from 1050 MHz to 2300 MHz. A buffer then drives
this divided down signal to the mixer core. The LO signal can
also be observed via the LO I/O port when the internal VCO
is selected. When the external LO buffer is enabled, the supply
current and die temperature increase, resulting in a slight
degradation of RF performance. In normal operation mode,
the external LO buffer should be disabled to help minimize
power consumption and provide optimal RF performance.
1.8
1.6
1.4
0.5
1.0
1.5
2.0
2.5
VTUNE (V)
08817-052
fVCO /2 (GHz)
2.2
The mixer portion of the ADRF6655, shown in Figure 51, consists
of an LO signal chain, an RF voltage-to-current (V-to-I) converter,
and a mixer core. The LO chain receives a signal from either the
internal VCO or an external LO source. This LO signal then passes
through a frequency divider, which can be set to divide-by-2
or divide-by-3, depending on the desired LO frequency. The
differential RF inputs are converted into currents by the V-to-I
converter and fed into the mixer core. A pair of 133 Ω pull-up
resistors are used to present a ~250 Ω source impedance at the
IF output.
Figure 50. fVCO/2 vs. Tuning Voltage for All 64 Bands
Rev. 0 | Page 17 of 44
ADRF6655
V-to-I Converter
DIGITAL INTERFACES
The differential RF input signal is applied to a pair of resistively
degenerated common-emitter stages, which converts the
differential input voltage to output currents. The input stage also
provides 50 Ω termination to the RF input port. The linearity
of this V-to-I stage can be optimized for a given frequency with
Pin IP3SET at the expense of power dissipation and noise figure.
An additional way of improving linearity without affecting
power dissipation or noise figure is provided by the CDAC
signal controlled by serial port interface (SPI).
The ADRF6655 provides access to the many programmable
features available within the IC using a 3-wire SPI control
interface. The minimum delays and hold times are presented
in the timing diagram in Figure 2. The SPI interface provides
digital control of the internal PLL/VCO as well as several other
features related to the mixer core, on-chip referencing, and available
system monitoring functions. The MUXOUT pin provides access
to several output signals that can be selected via the SPI interface.
The available outputs are buffered, frequency-scaled versions of
the reference, a PLL lock-detect signal, and an internal voltage
that is proportional to the IC junction temperature. Details
regarding the register settings and initialization sequence are
included in the Register Structure section.
Mixer Core
The mixer core, based on the Gilbert cell design of four crossconnected transistors, takes the currents from the V-to-I stage
and mixes them with the LO signal. This mixer core can be used
as a downconvert mixer as is or as an upconvert mixer with an
off-chip matching network for a given frequency range.
+5V
VCC1
2
DECL1
3
CP
4
GND
5
RSET
40
39
38
37
36
35
34
33
32
31
VTUNE
LOP
LON
GND
GND
VCCLO
NC
NC
GND
RSET
29
GND
28
VCCMIX
27
INP
26
INN
25
21
SPI
CONTROL
IF OUTPUT
MATCHING
BALUN AND BIAS
+5V
NC = NO CONNECT
Figure 52. Basic Circuit Connections
Rev. 0 | Page 18 of 44
VSET
+5V
RF INPUT
MATCHING
BALUN
RF INPUT
+5V
GND
GND
OUTP
VCC2
19
10
OUTN
22
18
VCCV2I
VCCLO
DECL2
17
9
NC
23
16
GND
GND
MUXOUT
15
8
LE
24
14
GND
CLK
GND
13
7
DATA
REFIN
12
+5V
IP3SET
6
GND
MONITOR
OUTPUT
30
ADRF6655
11
EXTERNAL
REFERENCE
GND
IF OUTPUT
08817-054
1
20
+5V
DECL3
CHARGE PUMP
LOOP FILTER
ADRF6655
ANALOG INTERFACES
The basic circuit connections for a typical ADRF6655 application
are presented in Figure 52.
ADRF6655
GND
20
1.5pF
GJM
15nH
0302CS
TC4-14G2+ 1nF
12nH
0302CS
IF OUT
2.7pF
GJM
+VCC
08817-055
OUTP
19
12nH
0302CS
T3
Figure 53. 850 MHz Output Matching Network Using the Center-Tap of the
TC4-14T+ Transformer for Biasing the Open Collector Outputs (Output
return loss measured to be better than 12 dB from 800 MHz to 925 MHz.)
ADRF6655
OUTP
GND
900MHz OUTPUT INTERFACE
OUTN
SYNTHESIZER CONNECTIONS
18
19
20
47nH
0603CS
5.1nH
0402CS
68nH
0402CS
150pF
+VCC
TC1-1-13M+ 1nF
1pF
GJM
T3
IF OUT
1nF
5.1nH
0402CS
+VCC
08817-056
47nH
0603CS
150pF
Figure 54. 900 MHz Output Matching Network Using the TC1-1-13M+ 1:1
Impedance Ratio Balun and External Pull-Up Choke Inductors (Output return
loss measured to be better than 12 dB from 815 MHz to 1075 MHz.)
ADRF6655
GND
1200MHz OUTPUT INTERFACE
OUTP
18
19
20
2.1nH
0302CS
150pF
+VCC
TC1-1-13M+ 1nF
IF OUT
17nH
0302CS
OUTPUT MATCHING AND BIASING
1.8pF
GJM
T3
1nF
2.1nH
+VCC
08817-057
47nH
0603CS
150pF
Figure 55. 1200 MHz Output Matching Network (Output return loss
measured to be better than 12 dB from 950 MHz to 1500 MHz.)
ADRF6655
OUTP
GND
1300MHz OUTPUT INTERFACE
OUTN
The ADRF6655 output stage consists of collector connected
output transistors with on-board pull-up resistors. The output
transistors and pull-up network presents a 200 Ω differential
output impedance in parallel with a small amount of shunt
capacitance. The measured RC equivalent impedance of Pin 18
and Pin 19 is ~250 Ω//1.5 pF. This impedance needs to be taken
into consideration when designing the external output matching
network. In addition to matching the presented output source
impedance to the intended load impedance, it is important to
provide pull-up choke connections to the supply pins to allow
for dc current to directly supply the mixer output transistors.
The reactance of the pull-up chokes may need to be considered
when designing the output matching network. For convenience,
several output matching/bias networks are presented in Figure 53
through Figure 58 for reference.
47nH
0603CS
18
19
20
47nH
0603CS
2.7nH
0402CS
150pF
+VCC
TC1-1-13M+ 1nF
IF OUT
10nH
0302CS
1.2pF
GJM
T3
1nF
2.7nH
0402CS
47nH
0603CS
+VCC
150pF
08817-058
The ADRF6655 includes an on-board VCO and PLL for LO
synthesis. An external reference must be applied for the PLL to
operate. The external reference should be ac-coupled and provide a
~1 V p-p nominal input level at Pin 6. The reference is compared
to an internally divided version of the VCO output frequency to
create a charge pump error current to control and lock the VCO. The
charge pump output current is filtered and converted to a VTUNE
control voltage through the external loop filter. ADIsimPLL™
can be a helpful tool when designing the external charge pump
loop filter. The typical Kv of the VCO, the charge pump output
current magnitude, and PFD frequency should all be considered
when designing the loop filter. The charge pump current magnitude
can be set internally or with an external RSET resistor connected
to Pin 5 and ground, along with the internal digital settings
applied to the PLL (see the Register 4—Charge Pump, PFD, and
Reference Path Control section for more details).
18
OUTN
The ADRF6655 has several supply connections and on-board
regulated reference voltages that should be bypassed to ground
using low inductance bypass capacitors located in close proximity
to the supply and reference pins of the ADRF6655. Specifically
Pin 1, Pin 2, Pin 9, Pin 10, Pin 17, Pin 22, Pin 27, and Pin 40
should be bypassed to ground using individual bypass capacitors.
Pin 9 is the supply used for the on-board VCO, and for best
phase noise performance, several bypass capacitors ranging
from 100 pF to 10 μF may help to improve phase noise
performance. For additional details on bypassing the supply
nodes, refer to the evaluation board schematic in Figure 82.
OUTN
SUPPLY CONNECTIONS
850MHz OUTPUT INTERFACE
Figure 56. 1300 MHz Output Matching Network (Output return loss
measured to be better than 12 dB from 1075 MHz to 1525 MHz.)
Rev. 0 | Page 19 of 44
ADRF6655
2
GND
19
20
0
–1
150pF
36nH
–2
VCC
1nF
0Ω
1nF
IF OUT
15nH
1.5pF
T6
0Ω
36nH
150pF
–4
–5
–6
1nF
–7
ANAREN
BD1722J50200A00
08817-059
VCC
–3
–8
900MHz MATCH
–9 1200MHz MATCH
1600MHz MATCH
–10
0.7 0.8 0.9 1.0 1.1
Figure 57. 1600 MHz Output Matching Network (Output return loss
measured to be better than 12 dB from 1400 MHz to 1680 MHz.)
1.2
1.3
1.4
1.5
1.6
1.7
1.8
1.9
OUTPUT FREQUENCY (GHz)
ADRF6655
Figure 60. Measured Conversion Gain for 900 MHz, 1200 MHz, and 1600 MHz
Matching Networks (See Figure 54, Figure 55, and Figure 57 for Implementation)
OUTN
OUTP
GND
2100MHz OUTPUT INTERFACE
18
19
20
INPUT MATCHING
150pF
The ADRF6655 uses a balanced 50 Ω input impedance to help
simplify external connections. For low loss interfacing, the driving
source should be transformed to present a balanced 50 Ω source
impedance. An appropriate 1:1 impedance ratio input balun should
be used when attempting to interface to an unbalanced 50 Ω
source. For input frequencies below ~1.5 GHz, the TC1-1-13M+
from Mini-Circuits or similar baluns should provide good return
loss and maximum power gain. For higher frequencies, baluns,
such as the TC1-1-43A+, are recommended for lowest insertion
loss. The ac coupling capacitors can be optimized with the balun to
provide optimum input match. A few examples are provided in
Figure 61 for a range of different IF output frequencies.
VCC
27nH 3pF
0603CS
TC1-1-13M+ 1nF
3pF
IF OUT
T3
1nF
VCC
08817-060
27nH
0603CS
150pF
Figure 58. 2100 MHz Output Matching Network (Output return loss
measured to be better than 12 dB from 2000 MHz to 2200 MHz.)
35
0
25
–10
OUTPUT P1dB
S11 (dB)
10
5
0
0.7
–15
–20
–25
0.8
0.9
1.0
1.1
1.2
1.3
1.4
1.5
OUTPUT FREQUENCY (GHz)
1.6
1.7
1.8
1.9
–30
Figure 59. Measured Output Linearity for 900 MHz, 1200 MHz, and 1600 MHz
Matching Networks (See Figure 54, Figure 55, and Figure 57 for Implementation)
–35
0.5
1.0
1.5
2.0
FREQUENCY (GHz)
2.5
3.0
08817-063
15
TC1-1-43A+ WITH 10pF AC COUPLING
TC1-1-43A+ WITH 3pF AC COUPLING
TC1-1-43A+ WITH 1.8pF AC COUPLING
–5
900MHz MATCH
1200MHz MATCH
1600MHz MATCH
08817-061
OUTPUT IP3 AND OUTPUT P1dB (dBm)
OUTPUT IP3
30
20
08817-062
OUTP
18
1
1600MHz OUTPUT INTERFACE
GAIN (dB)
OUTN
ADRF6655
Figure 61. Measured RF Input Return Loss Using the TC1-1-43A+ 1:1 Balun
(Plotted for Several AC Coupling Capacitor Values)
It is also possible to use lumped element LC lattice networks to
transform an unbalanced source into a balanced source at the
mixer input pins. In either case, the mixer input pins should be
dc blocked using adequately sized series capacitors.
Rev. 0 | Page 20 of 44
ADRF6655
IP3SET LINEARIZATION FEATURE
CDAC LINEARIZATION FEATURE
The IP3SET pin (Pin 29) controls the overall current consumption
of the mixer core depending on the applied voltage. If left open,
the voltage on the IP3SET pin is ~2.3 V, and a typical input IP3 of
~25 dBm or higher can be expected across the operating frequency
range. As the IP3SET voltage is increased, the overall supply
current increases and the input IP3 can be improved from ~3 dB to
6 dB. For upconversion applications, an IP3SET voltage of ~3.2 V to
3.3 V results in very high output IP3 performance in excess of
30 dBm. Using an external resistor divider network connected
between VCC and GND, the IP3SET voltage can be derived.
Alternatively, the on-board 3.3 V LDO output (Pin 2) can be
used to derive the applied IP3SET voltage. However, it is
advisable to use good bypassing and a series inductor or ferrite
choke to ensure good high frequency isolation between Pin 1 and
Pin 29. If an auxiliary control DAC is available, the IP3SET pin can
be driven dynamically in applications where power levels are
changing over time, and it is desirable to conserve power at
lower input signal levels. Figure 62 and Figure 63 illustrate the
output linearity dependency on the IP3SET voltage. Note that
gain is independent of the IP3SET voltage.
In addition to the IP3SET broadband linearization solution, the
ADRF6655 also includes a special linearizer designed to provide
enhanced IP3 performance at higher input frequencies. At low
input frequencies, the CDAC setting offers very little influence
on input IP3, and a CDAC setting of 15 is usually recommended.
At high input frequencies, the CDAC setting can boost input
IP3 as much as 5 dB with essentially no increase in supplied
power. At a given input frequency, the ADRF6655 offers an
optimum CDAC setting to provide high input IP3 performance.
The recommended optimum CDAC setting vs. RF input frequency
is shown in Figure 64.
15
13
12
11
10
CDAC
9
4
3
2
31
OUTPUT IP3 (dBm)
0
1840
29
2040
2140
2240
2340
2440
Figure 64. Optimum CDAC Setting for Downconversion vs. RF Input Frequency
27
26
EXTERNAL LO INTERFACE
25
24
23
22
OUTPUT FREQUENCY = 1210MHz
OUTPUT FREQUENCY = 1500MHz
20
2.3 2.4 2.5 2.6 2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6 3.7
IP3SET (V)
08817-111
21
Figure 62. Output IP3 vs. IP3SET Voltage for Output Frequency
20
18
16
OUTPUT P1dB
12
The ADRF6655 provides the option to use an external signal
source for the LO into the mixer. It is important to note that the
applied LO signal is divided by 2 or divided by 3 prior to the
actual mixer core within the ADRF6655. The divider is determined
by the register settings in LO path and mixer control register,
(see the Register 5—LO Path and Mixer Control section). The
LO input pins (Pin 37 and Pin 38) present a broadband balanced
50 Ω input interface similar to the input pins (Pin 25 and Pin 26).
The LOP and LON input pins should be dc blocked and driven
from a balanced 50 Ω source. When not in use, the LOP and
LON pins may be left unconnected.
10
8
6
GAIN
0
–2
–4
–6
–8 OUTPUT FREQUENCY = 1210 MHz
OUTPUT FREQUENCY = 1500 MHz
–10
2.3 2.4 2.5 2.6 2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6 3.7
OUTPUT FREQUENCY (MHz)
08817-112
GAIN (dB)
1940
RF FREQUENCY (MHz)
28
08817-066
1
30
2
7
5
32
4
8
6
33
14
BEST CDAC AT 25°C
INTERCEPT
BEST CDAC AT 85°C
14
Figure 63. Output P1dB and Gain vs. IP3SET Voltage
Rev. 0 | Page 21 of 44
ADRF6655
+5V
USING AN EXTERNAL VCO
CHARGE PUMP
LOOP FILTER
1
VCC1
2
DECL1
3
CP
4
GND
5
RSET
6
REFIN
7
GND
RSET
EXTERNAL
REFERENCE
Rev. 0 | Page 22 of 44
39
38
37
36
35
VTUNE
LOP
LON
GND
GND
ADRF6655
Figure 65. External VCO Connections
08817-067
+5V
40
NC
DECL3
The ADRF6655 has the necessary provisions for interfacing an
external VCO. A high performance discrete VCO may be desirable
in applications that call for the very best phase noise performance.
The basic circuit connections for interfacing an external VCO
are included in Figure 65. It is important to select a VCO with a
frequency tuning voltage range that covers the available charge
pump output compliance range of 1 V to 2.8 V. The external VCO
waveform needs to pass through the on-chip divide-by-2/divideby-3 programmable dividers before reaching the mixer. As a result,
the VCO center frequency should be selected to be roughly 2×
or 3× the desired LO signal frequency. The available output power
for the selected VCO should be greater than −10 dBm to ensure
adequate signal levels into the mixer core. The charge pump loop
filter components should be designed to provide adequate phase
margin for the given KVCO tuning sensitivity of the selected VCO.
It is important to properly configure the digital registers for
external VCO operation. When using an external VCO, the
internal VCO should be disabled using DB17 in Register 6.
Other register programmable LDOs, including the VCO LDO
(DB18 in Register 6), should be enabled. For more information
on programming the ADRF6655, see the ADRF6655 Control
Software section.
EXTERNAL VCO
VTUNE LINE
ADRF6655
ADRF6655 CONTROL SOFTWARE
After launching the software, the user is prompted to select a device
from the ADRF product family. Upon selecting the ADRF6655,
the main control interface should appear as shown in Figure 66.
The main control interface allows the user to configure the device
for various modes of operation. The internal synthesizer is
controlled by clicking on any of the numeric values listed in the
RF Section. Attempting to program the REF Input Frequency,
the PFD Frequency, the VCO Frequency [2×LO], or other
values in the RF section launches the Synthesizer Settings—
ADRF6655 Broadband Mixer control module depicted in
Figure 67. From the Synthesizer Settings control interface, the
user can enter the desired Local Oscillator Frequency (MHz),
Channel Step Resolution (kHz), and External Reference
Frequency (MHz). The user can also enable the LO output buffer
and divider options from this menu. After setting the desired
values, it is important to click Upload All Registers and
Windows for the new settings to take effect.
08817-070
The ADRF6655 can be controlled from most PCs that include
a parallel port output interface. A USB adapter board is also
available from Analog Devices, Inc., to allow for control from
PCs that do not have an accessible parallel port. The USB adapter
evaluation documentation and ordering information can be found
at www.analog.com by searching for EVAL-ADF4XXXZ-USB. The
basic user interfaces are depicted in Figure 66 and Figure 67.
Figure 67. ADRF6655 Synthesizer Settings User Interface
PLL LOOP FILTER DESIGN
Designing the external loop filter, which connects between the
charge pump output and VCO tuning control pin, is easy with
the help of ADIsimPLL. ADIsimPLL is a free software application
available from Analog Devices for designing PLL loop filters.
Several passive filter topologies are support in ADIsimPLL
along with the necessary component placements on the
evaluation board.
When designing a PLL loop filter, it is important to consider
settling time and phase noise requirements. Figure 68 provides
measured phase noise performance for a typical fast and slow
loop filter design. Note that the wider loop filter offers better
close-in phase noise but degraded phase noise at greater offset
frequencies. The narrow 1.5 kHz loop filter design provides the
best phase noise at 100 kHz and 1 MHz carrier offsets but with
the penalty of decreased frequency settling time and poorer
close-in performance.
0
–20
PHASE NOISE (dBc/Hz)
08817-069
–40
ADRF6655 1.5kHz LOOP FILTER
LO = 2275MHz
–60
LO = 1100Hz
–80
–100
–120
67kHz LOOP FILTER
–140
–180
1k
10k
100k
1M
10M
OFFSET FREQUENCY (Hz)
Figure 68. Phase Noise with Different Loop Filters
Rev. 0 | Page 23 of 44
100M
08817-071
–160
Figure 66. ADRF6655 Software Control Interface
ADRF6655
REGISTER STRUCTURE
INTEGER DIVIDE CONTROL REGISTER (R0)
DIVIDE
MODE
RESERVED
DB23
DB22
DB21
DB20
DB19
DB18
DB17
DB16
DB15
DB14
DB13
DB12
0
0
0
0
0
0
0
0
0
0
0
0
DB11 DB10
0
INTEGER DIVIDE RATIO
CONTROL BITS
DB9 DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
ID6
ID4
ID3
ID2
ID1
ID0
C3(0)
C2(0)
C1(0)
DB6
DB5
DB4 DB3
DB2
DB1
DB0
MD4 MD3
MD2
MD1 MD0
C3(0)
C2(0)
C1(1)
DM
ID5
MODULUS DIVIDE CONTROL REGISTER (R1)
RESERVED
MODULUS DIVIDE VALUE
DB23
DB22
DB21
DB20
DB19
DB18
DB17
DB16
DB15
DB14
DB13
DB12
DB11
DB10
DB9
DB8
0
0
0
0
0
0
0
0
0
0
MD10
MD9
MD8
MD7
MD6 MD5
DB7
CONTROL BITS
FRACTIONAL DIVIDE CONTROL REGISTER (R2)
RESERVED
FRACTIONAL DIVIDE VALUE
CONTROL BITS
DB23
DB22
DB21
DB20
DB19
DB18
DB17
DB16
DB15
DB14
DB13
DB12
DB11
DB10
DB9
DB8
DB7
DB6
DB5
DB4 DB3
DB2
DB1
DB0
0
0
0
0
0
0
0
0
0
0
PD10
PD9
PD8
PD7
PD6
PD5
PD4
PD3
PD2
PD1
PD0
C3(0)
C2(1)
C1(0)
Σ-Δ MODULATOR DITHER CONTROL REGISTER (R3)
DITHER
DITHER
MAGNITUDE ENABLE
DB23
0
DB22
CONTROL BITS
DITHER RESTART VALUE
DB21
DB20
DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
DITH1 DITH0
DEN
DV16 DV15 DV14 DV13 DV12 DV11 DV10
DV6
DV5
DV4
DV3
DV2
DV1
DV0
C3(0)
C2(1)
C1(1)
DV9
DV8
DV7
CHARGE PUMP, PFD, AND REFERENCE PATH CONTROL REGISTER (R4)
CP
REF
DB21 DB20 DB19
DB18
DB17
DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9
DB7
DB6
DB5
CPM
CPBD
CPB4 CPB3 CPB2 CPB1 CPB0 CPP1 CPP0 CPS CPC1 CPC0
PE1
PE0
OUPUT MUX
SOURCE
DB23
DB22
PDF
PHASE
OFFSET
POLARITY
INPUT REF
PATH
SOURCE
RMS2 RMS1 RMS0 RS1
RS0
CP
CP
CURRENT CNTL
MULTIPLIER SRC
PFD PHASE OFFSET
MULTIPLIER VALUE
CHARGE
PUMP
CONTROL
DB8
PFD ANTIPFD EDGE BACKLASH
SENSITIVITY
DELAY
DB4
DB3
CONTROL BITS
DB2
DB1
DB0
PAB1 PAB0 C3(1)
C2(0)
C1(0)
LO PATH AND MIXER CONTROL REGISTER (R5)
MIXER
LO
LO OUTPUT
CDAC DISTORTION
PLL
LO
BIAS
IN/OUT
DRIVER
COMPENSATION
CONTROL BITS
ENABLE ENABLE DIV 2/3 CNTRL
ENABLE
SETTING
DB2 DB1 DB0
DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8
DB7
DB6
DB5
DB4
DB3
C3(1) C2(0) C1(1)
0
0
0
0
0
0
0
0
0
0
0
0 CDAC3 CDAC2 CDAC1 CDAC0 MBE
PLEN
LDIV
LXL
LDRV
RESERVED
VCO CONTROL AND PLL ENABLES REGISTER (R6)
RESERVED
DB23 DB22 DB21
0
0
0
CHARGE
LDO
VCO
VCO
VCO
PUMP
3.3V
LDO
SWITCH
ENABLE ENABLE ENABLE ENABLE CONTROL
DB20
CPEN
DB19
L3EN
DB18
LVEN
DB17
VCOEN
DB16
VCOSW
VCO
BS
SRC
VCO AMPLITUDE SETTING
VCO BAND SELECT
CONTROL BITS
DB15 DB14 DB13 DB12 DB11 DB10
DB9
DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
VC5 VC4 VC3 VC2 VC1 VC0 VBSRC VBS5 VBS4 VBS3 VBS2 VBS1 VBS0 C3(1) C2(1) C1(0)
EXTERNAL VCO CONTROL REGISTER (R7)
DB23
DB22
0
XVCO
CONTROL BITS
RESERVED
DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10
0
0
0
0
0
0
0
0
0
0
0
0
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
0
0
0
0
0
0
C3(1)
C2(1)
C1(1)
Figure 69. Register Maps for ADRF6655 (The three control bits determine which register is programmed.)
Rev. 0 | Page 24 of 44
08817-068
EXTERNAL
VCO
RES
ENABLE
ADRF6655
DEVICE PROGRAMMING
INITIALIZATION SEQUENCE
The device is programmed through a 3-pin SPI port. The timing
requirements for the SPI port are described in Figure 2. There
are eight programmable registers, each with 24 bits, controlling
the operation of the device. The register functions can be broken
down as follows:
To ensure proper power-up of the ADRF6655, it is important to
reset the PLL circuitry after the supply rail (VCC1, VCC2, VCCLO,
VCCV2I, and VCCMIX) has settled to 5 V ± 0.25 V. Resetting
the PLL ensures that the internal bias cells are properly configured
even under poor supply start-up conditions. To ensure that the
PLL is reset after power-up, the PLEN data bit (DB6) in Register
5 should be programmed to disable the PLL (PLEN = 0). After a
delay of >100 ms, Register 5 should be programmed to enable
the PLL (PLEN = 1). After this procedure, the registers should
be programmed as follows:
•
•
•
•
•
•
•
•
Register 0—integer divide control
Register 1—modulus divide control
Register 2—fractional divide control
Register 3—Σ-Δ modulator dither control
Register 4—charge pump, PFD, and reference path control
Register 5—LO path and mixer control
Register 6—VCO controls and PLL enables
Register 7—external VCO control
Note that the PLL has internal calibration that must run
whenever the device is programmed with a given frequency.
This calibration is automatically run whenever Register 0,
Register 1, or Register 2 is programmed. Software is available
from Analog Devices that allows easy programming from an
external PC. See the ADRF6655 Control Software section for
additional details.
1.
2.
3.
4.
5.
6.
7.
8.
Register 7
Register 6
Register 4
Register 3
Register 2
Register 1
Delay >1 ms
Register 0
When programming the frequency of the ADRF6655, normally
only Register 2, Register 1, and Register 0 are programmed. When
programming these registers, a short delay of >500 μs should be
placed before programming the last register in the sequence
(Register 0). This ensures that the VCO band calibration initiated
by the first two register writes has sufficient time to complete
before the final band calibration (for Register 0) is initiated.
Rev. 0 | Page 25 of 44
ADRF6655
REGISTER 0—INTEGER DIVIDE CONTROL
Divide Mode
With R0[2:0] set to 000, the on-chip integer divide control register
is programmed as shown in Figure 70.
Divide mode determines whether fractional mode or integer
mode is used. In integer mode, the RF VCO output frequency
(fVCO) is calculated by
Integer Divide Ratio
fVCO = 2 × fPFD × (INT)
The integer divide ratio is used to set the INT value in Equation 1.
The INT, FRAC, and MOD values make it possible to generate
output frequencies that are spaced by fractions of the PFD
frequency. The VCO frequency (FVCO) equation is
fVCO = 2 × fPFD × (INT + (FRAC/MOD))
(2)
where INT is the integer divide ratio value (21 to 123 in integer
mode).
(1)
where:
fVCO is the output frequency of the internal VCO.
fPFD is the frequency of operation of the phase-frequency
detector.
INT is the preset integer divide ratio value (24 to 119 in
fractional mode).
MOD is the preset fractional modulus (1 to 2047).
FRAC is the preset fractional divider ratio value (0 to MOD − 1).
DB23
DB22
DB21
DB20
DB19
DB18
DB17
DB16
DB15
DB14
DB13
DB12
DB11
DB10
0
0
0
0
0
0
0
0
0
0
0
0
0
DM
INTEGER DIVIDE RATIO
CONTROL BITS
DB9 DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
ID6
ID4
ID3
ID2
ID1
ID0
C3(0)
C2(0)
C1(0)
ID5
DM
DIVIDE MODE
0
1
FRACTIONAL
INTEGER
ID6
ID5
ID4
ID3
ID2
ID1
ID0
INTEGER DIVIDE RATIO
0
0
1
0
1
0
1
21 (INTEGER MODE ONLY)
0
0
1
0
1
1
0
22 (INTEGER MODE ONLY)
0
0
1
0
1
1
1
23 (INTEGER MODE ONLY)
0
0
1
1
0
0
0
24
...
...
...
...
...
...
...
...
...
...
...
...
...
...
...
...
0
1
1
1
0
0
0
56
...
...
...
...
...
...
...
...
...
...
...
...
...
...
...
...
1
1
1
0
1
1
1
119
1
1
1
1
0
0
0
120 (INTEGER MODE ONLY)
1
1
1
1
0
0
1
121 (INTEGER MODE ONLY)
1
1
1
1
0
1
0
122 (INTEGER MODE ONLY)
1
1
1
1
0
1
1
123 (INTEGER MODE ONLY)
Figure 70. Integer Divide Control Register (R0)
Rev. 0 | Page 26 of 44
08817-072
DIVIDE
MODE
RESERVED
ADRF6655
REGISTER 1—MODULUS DIVIDE CONTROL
REGISTER 2—FRACTIONAL DIVIDE CONTROL
With R1[2:0] set to 001, the on-chip modulus divide control
register is programmed as shown in Figure 71.
With R2[2:0] set to 010, the on-chip fractional divide control
register is programmed as shown in Figure 72.
The MOD value is the preset fractional modulus ranging from
1 to 2047.
The FRAC value is the preset fractional modulus ranging from
0 to MOD − 1.
RESERVED
0
0
MODULUS DIVIDE RATIO
CONTROL BITS
DB21
DB20
DB19
DB18
DB17
DB16
DB15
DB14
DB13
DB12
DB11
DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
0
0
0
0
0
0
0
MD10
MD9
MD8
MD7
MD6
MD5
MD4
MD3
MD2
MD1
MD0
C3(0)
C2(0)
C1(1)
MD10
MD9
MD8
MD7
MD6
MD5
MD4
MD3
MD2
MD1
MD0
MODULUS VALUE
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
1
0
2
...
...
...
...
...
...
...
...
...
...
...
...
...
...
...
...
...
...
...
...
...
...
...
...
0
0
0
0
1
1
0
0
0
0
0
1536
...
...
...
...
...
...
...
...
...
...
...
...
...
...
...
...
...
...
...
...
...
...
...
...
1
1
1
1
1
1
1
1
1
1
1
2047
08817-073
DB23 DB22
Figure 71. Modulus Divide Control Register (R1)
CONTROL BITS
FRACTIONAL DIVIDE VALUE
DB22
DB21
DB20
DB19
DB18
DB17
DB16
DB15
DB14
DB13
DB12
DB11
DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
0
0
0
0
0
0
0
0
0
FD10
FD9
FD8
FD7
FD6
FD5
FD4
FD3
FD2
FD1
FD0
C3(0)
C2(1)
C1(0)
FD10
FD9
FD8
FD7
FD6
FD5
FD4
FD3
FD2
FD1
FD0
FRACTIONAL VALUE
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
...
...
...
...
...
...
...
...
...
...
...
...
...
...
...
...
...
...
...
...
...
...
...
...
0
1
1
0
0
0
0
0
0
0
0
768
...
...
...
...
...
...
...
...
...
...
...
...
...
...
...
...
...
...
...
...
...
...
...
...
FRACTIONAL VALUE MUST BE LESS THAN MODULUS
Figure 72. Fractional Divide Control Register (R2)
Rev. 0 | Page 27 of 44
<MDR
08817-074
RESERVED
DB23
ADRF6655
REGISTER 3—Σ-Δ MODULATOR DITHER CONTROL
With R3[2:0] set to 011, the on-chip, Σ-Δ modulator, dither
control register is programmed as shown in Figure 73.
The dither restart value can be programmed from 0 to 217 − 1,
though a value of 1 is typically recommended.
DITHER
DITHER RESTART VALUE
ENABLE
DB20
DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5
DEN
DV16 DV15 DV14 DV13 DV12 DV11 DV10 DV9 DV8 DV7 DV6 DV5 DV4 DV3 DV2
DITH1
0
0
DITH0
0
1
DITHER MAGNITUDE
15
7
1
0
3
1
1
1 (RECOMMENDED)
DEN
0
1
CONTROL BITS
DB4 DB3 DB2 DB1 DB0
DV1 DV0 C3(0) C2(1) C1(1)
DITHER ENABLE
DISABLE (RECOMMENDED)
ENABLE
DV16 DV15 DV14 DV13 DV12 DV11 DV10 DV9
DV8
DV7
DV6
DV5
DV4
DV3
DV2
DV1
DV0
DITHER RESTART
VALUE
0
...
...
1
0
...
...
1
0
...
...
1
0
...
...
1
0
...
...
1
0
...
...
1
0
...
...
1
0
...
...
1
0
...
...
1
1
...
...
1
0x00001
...
...
0x1FFFF
0
...
...
1
0
...
...
1
0
...
...
1
0
...
...
1
0
...
...
1
0
...
...
1
0
...
...
1
Figure 73. Σ-Δ Modulator Dither Control Register (R3)
Rev. 0 | Page 28 of 44
08817-075
DB23
0
DITHER
MAGNITUDE
DB22
DB21
DITH1
DITH0
ADRF6655
The PFD phase offset multiplier (θPFD, OFS), which is set by Bit DB16
to Bit DB12 of Register 4, causes the PLL to lock with a nominally
fixed phase offset between the PFD reference signal and the
divided-down VCO signal. This phase offset is used to linearize
the PFD-to-CP transfer function and can improve fractional
spurs. The magnitude of the phase offset is determined by
REGISTER 4—CHARGE PUMP, PFD, AND
REFERENCE PATH CONTROL
With R4[2:0] set to 100, the on-chip charge pump, PFD, and
reference path control register is programmed as shown in
Figure 74.
The charge pump current is controlled by the base charge
pump current (ICP, BASE) and the value of the charge pump
current multiplier (ICP, MULT).
ΔΦ [deg] = 22 . 5
The base charge pump current can be set using an internal or
external resistor (according to DB18 of Register 4). When using an
external resistor, the value of ICP, BASE can be varied according to
⎡ 217 . 4 × I CP , BASE ⎤
RSET [Ω ] = ⎢
⎥ − 37 . 8
250
⎣
⎦
(3)
When using the internal resistor, the base charge pump current
is 250 μA. The actual charge pump current can be programmed
to be a multiple (1, 2, 3, or 4) of the charge pump base current.
The multiplying value (ICP, MULT) is equal to 1 plus the value of
Bit DB11 and Bit DB10 in Register 4.
θ PFD , OFS
I CP , MULT
Finally, the phase offset can be either positive or negative
depending on the value of DB17 in Register 4.
The reference frequency applied to the PFD can be manipulated
using the internal reference path source. The external reference
frequency applied can be internally scaled in frequency by 2×, 1×,
0.5×, or 0.25×. This allows a broader range of reference frequency
selections while keeping the reference frequency applied to the
PFD within an acceptable range.
The ADRF6655 also provides a MUXOUT pin that can be
programmed to output a selection of several internal signals.
The default mode is to provide a lock-detect output to allow the
user to verify when the PLL has locked to the target frequency.
In addition, several other internal signals may be passed to the
MUXOUT pin, as described in Figure 74.
Rev. 0 | Page 29 of 44
ADRF6655
INPUT REF
PATH
SOURCE
OUPUT MUX
SOURCE
DB23
DB22
CP
REF
DB21 DB20 DB19
RMS2 RMS1 RMS0
RS1
RS0
PDF
PHASE
OFFSET
POLARITY
CP
CP
CURRENT CNTL
MULTIPLIER SRC
PFD PHASE OFFSET
MULTIPLIER VALUE
CHARGE
PUMP
CONTROL
DB8
PFD ANTIPFD EDGE
SENSITIVITY BACKLASH
DELAY
DB18
DB17
DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9
DB7
DB6
DB5
CPM
CPBD
CPB4 CPB3 CPB2 CPB1 CPB0 CPP1 CPP0 CPS CPC1 CPC0
PE1
PE0
DB4
DB3
CONTROL BITS
DB2
DB1
DB0
PAB1 PAB0 C3(1)
C2(0)
C1(0)
PAB1 PAB0 PFD ANTI-BACKLASH
DELAY
0
0
1
1
PE1
0
1
0
1
0
1
0ns
0.5ns
0.75ns
0.9ns
PE0
REFERENCE PATH EDGE
SENSITIVITY
0
1
FALLING EDGE
RISING EDGE
DIVIDER PATH EDGE
SENSITIVITY
FALLING EDGE (RECOMMENDED)
RISING EDGE
CHARGE PUMP
CPC1 CPC0 CONTROL
BOTH ON
0
0
PUMP DOWN
0
1
PUMP UP
1
0
TRISTATE
1
1
CPS
CHARGE PUMP CONTROL SOURCE
0
1
CONTROL BASED ON STATE OF DB7/DB8 (CP CONTROL)
CONTROL FROM PFD
CHARGE PUMP
CPP1 CPP0 CURRENT MULTIPLIER
0
0
1
1
CPM
0
1
0
1
0
1
1
2
3
4
CPB4 CPB3 CPB2 CPB1 CPB0
PFD PHASE OFFSET MULTIPLIER
0
0
...
0
...
0
...
1
0 × 22.5°/ICP, MULT
1 × 22.5°/ICP, MULT
...
4 × 22.5°/ICP, MULT (RECOMMENDED)
...
10 × 22.5°/ICP, MULT
...
31 × 22.5°/ICP, MULT
0
0
...
0
...
1
...
1
0
0
...
1
...
0
...
1
0
0
...
0
...
1
...
1
0
1
...
0
...
0
...
1
CPBD
PFD PHASE OFFSET POLARITY
0
1
NEGATIVE
POSITIVE
CHARGE PUMP CURRENT
REFERENCE SOURCE
INTERNAL
EXTERNAL
RS1
RS0
INPUT REFERENCE
PATH SOURCE
0
0
1
1
0
1
0
1
2 × REFIN
REFIN
0.5 × REFIN
0.25 × REFIN
RMS2 RMS1 RMS0 OUTPUT MUX SELECT
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
LOCK DETECT
VPTAT
REFIN (BUFFERED)
0.5 × REFIN (BUFFERED)
2 × REFIN (BUFFERED)
TRISTATE
RESERVED (DO NOT USE)
RESERVED (DO NOT USE)
08817-076
0
0
0
0
1
1
1
1
Figure 74. Charge Pump, PFD, and Reference Path Control Register (R4)
Rev. 0 | Page 30 of 44
ADRF6655
When using an external frequency, stable local oscillator signal
to commutate the mixer core, it is possible to shut down the PLL
circuitry through the PLL enable address (DB6) of Register 5.
REGISTER 5—LO PATH AND MIXER CONTROL
With R5[2:0] set to 101, the LO path and mixer control register
is programmed as shown in Figure 75.
The internal mixer can be disabled using the mixer bias enable
address (DB7) of Register 5.
The LO output driver can be enabled to allow the user to review
the performance of the internally applied LO through the LOP
and LON local oscillator input/output pins. The LO input/output
control allows the user to disconnect the internal LO signal and
apply an external LO signal to the LOP and LON local oscillator
input/output pins. A divide-by-2 or divide-by-3 prescaler can be
selected to divide the frequency of the externally or internally
applied oscillator signal before the mixer.
Register 5 also provides access to the CDAC Distortion
Compensation Setting (DB11:DB8). CDAC control can allow
the user to optimize the internal linearization circuitry to enhance
IP3 performance for high frequency RF input signals.
MIXER
LO
LO OUTPUT
CDAC DISTORTION
PLL
LO
BIAS
IN/OUT
DRIVER
COMPENSATION
CONTROL BITS
ENABLE ENABLE DIV 2/3 CNTRL
ENABLE
SETTING
DB2 DB1 DB0
DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8
DB7
DB6
DB5
DB4
DB3
C3(1) C2(0) C1(1)
0
0
0
0
0
0
0
0
0
0
0
0 CDAC3 CDAC2 CDAC1 CDAC0 MBE
PLEN
LDIV
LXL
LDRV
CDAC3 CDAC2 CDAC1 CDAC0
0
0
...
...
1
0
0
...
...
1
0
0
...
...
1
0
1
...
...
1
CDAC DISTORTION
COMPENSATION
SETTLING
MINIMUM
...
...
...
MAXIMUM
MBE
MIXER BIAS ENABLE
0
1
DISABLE
ENABLE
PLEN
PLL ENABLE
0
1
DISABLE
ENABLE
LDIV
DIVIDE-BY-2 OR DIVIDE-BY-3
0
1
DIVIDE BY 3
DIVIDE BY 2
LXL
LO IN/OUT CONTROL
0
1
LO OUTPUT
LO INPUT
Figure 75. LO Path and Mixer Control Register (R5)
Rev. 0 | Page 31 of 44
LDRV
LO OUTPUT DRIVER
ENABLE
0
1
DRIVER OFF (RECOMMENDED)
DRIVER ON
08817-077
RESERVED
ADRF6655
The VCO amplitude can be controlled through Register 6. The
VCO amplitude setting can be controlled between 0 and 63.
REGISTER 6—VCO CONTROL AND PLL ENABLES
With R6[2:0] set to 110, the VCO control and PLL enables
register is programmed as shown in Figure 76.
The internal VCO can be disabled using Register 6. The internal
VCO LDO can be disabled if an external clean 2.9 V supply is
available to be applied to Pin 40. Additionally, the 3.3 V on-board
LDO can be disabled through Register 6 and an external 3.3 V
supply can be applied to Pin 2.
The VCO tuning band is normally selected automatically by the
band calibration algorithm, although the user can directly select
the VCO band using Register 6.
The VCO BS SRC bit (DB9) determines whether the result of
the calibration algorithm is used to select the VCO band, or if
the band selected is based on the value in VCO band select
(DB8 to DB3).
CHARGE
VCO
LDO
VCO
VCO
PUMP
LDO
3.3V
SWITCH
ENABLE ENABLE ENABLE ENABLE CONTROL
DB23 DB22 DB21
0
0
0
DB20
CPEN
DB19
L3EN
DB18
LVEN
DB17
VCOEN
DB16
VCOSW
VCO
BS
SRC
VCO AMPLITUDE SETTING
DB15 DB14 DB13 DB12 DB11 DB10
DB9
DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
VC5 VC4 VC3 VC2 VC1 VC0 VBSRC VBS5 VBS4 VBS3 VBS2 VBS1 VBS0 C3(1) C2(1) C1(0)
CPEN CHARGE PUMP ENABLE
0
1
VCO BAND
VBS5 VBS4 VBS3 VBS2 VBS1 VBS0 SELECT
FROM SPI
DISABLE
ENABLE
L3EN LDO 3.3V ENABLE
0
1
CONTROL BITS
VCO BAND SELECT
DISABLE
ENABLE
0
...
1
...
0
...
0
...
0
...
0
...
0
...
0
...
0
...
0
...
0
...
0
...
0
...
32
...
1
1
1
1
1
1
63
LVEN
VCO LDO ENABLE
VCO BAND CALIBRATION
VBSRC AND SW SOURCE CONTROL
0
1
DISABLE
ENABLE
0
1
VCOEN
VCO ENABLE
0
1
DISABLE
ENABLE
VCOSW
VCO SWITCH CONTROL FROM SPI
0
1
REGULAR
BAND CALIBRATION
BAND CALIBRATION
SPI
VC5
VC4
VC3
VC2
VC1
VC0
VCO AMPLITUDE
SETTING
0
...
0
...
0
...
1
...
0
...
1
...
0
...
0
...
0
...
0
...
0
...
0
...
0
...
24
...
0
...
1
1
...
0
1
...
1
1
...
1
1
...
1
1
...
1
47 (RECOMMENDED)
...
63
Figure 76. VCO Control and Enables Register (R6)
Rev. 0 | Page 32 of 44
08817-078
RESERVED
The internal charge pump can be disabled through Register 6.
Normally, the charge pump is enabled.
ADRF6655
REGISTER 7—EXTERNAL VCO CONTROL
With R6[2:0] set to 111, the external VCO control register is
programmed as shown in Figure 77.
The external VCO enable bit allows the use of an external VCO in
the PLL instead of the internal VCO. This can be advantageous in
cases where the internal VCO is not capable of providing the desired
frequency, or where the internal phase noise of the VCO is higher
than desired. By setting the external VCO enable bit (DB22) to 1,
and setting Bit DB15 to Bit DB10 of Register 6 to 0, the internal
VCO is disabled and the output of an external VCO can be fed into
the part differentially on Pin 38 and Pin 37 (LOP and LON).
Because the loop filter is already external, the output of the loop
filter simply needs to be connected to the external, tuning voltage
pin of the VCO. See the Using an External VCO section for more
information.
EXTERNAL
VCO
RESERVED
ENABLE
DB23
DB22
DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
XVCO
CONTROL BITS
RES
EXTERNAL VCO ENABLE
INTERNAL VCO
EXTERNAL VCO
DB4 DB3 DB2 DB1 DB0
0
0 C3(1) C2(1) C1(1)
08817-079
XVCO
0
1
DB7 DB6 DB5
0
0
0
Figure 77. External VCO Control Register (R7)
Rev. 0 | Page 33 of 44
ADRF6655
CHARACTERIZATION SETUPS
Figure 78 to Figure 80 show the general characterization bench
setups used extensively for the ADRF6655. The setup shown in
Figure 78 was used to do the bulk of the testing. An automated
Agilent VEE program was used to control the equipment over the
IEEE bus. This setup was used to measure gain, IP1dB, OP1dB,
IIP2, IIP3, OIP2, OIP3, LO-to-IF and LO-to-RF leakage, LO
amplitude, and supply current. The ADRF6655 was characterized
on an upconversion and downconversion evaluation board
configured for each conversion as described in the Input Matching
section and the Output Matching and Biasing section. For all
measurements of the ADRF6655, the loss of the RF input balun
was de-embedded.
To do phase noise and reference spurs measurements, see the
phase noise setup used in Figure 79. Phase noise measurements
were done on a downconversion board looking at the output at
different offsets.
Figure 80 shows the setup used to make the noise figure
measurements with no blocker present, and Figure 81 shows
the setup for making the noise figure measurements under
blocking conditions. Note that attention must be given to the
measurement setup. The RF blocker signal must be filtered
through a band-pass filter to prevent noise (which increases
when output power is increased) from contributing at the desired
RF frequency. At least 30 dB attenuation is needed at the desired
RF and image frequencies. For example, to generate a blocker
signal at the IF output of 205 MHz, the blocker signal generator
is set at 995 MHz, and the part is programmed to generate a LO
frequency of 1200 MHz that results in an output signal of 205 MHz.
This signal must be filtered out through a band reject filter on
the output so that the noise figure can be measured at 200 MHz,
which corresponds to the output frequency for LO = 1200 MHz
and RF input = 1000 MHz.
Rev. 0 | Page 34 of 44
ADRF6655
IEEE
AGILENT PSG-A SIGNAL GENERATOR
IEEE
RF
RHODE & SCHWARTZ SMT03
SIGNAL GENERATOR
3dB
AGILENT 11636A
POWER DIVIDER
(USED AS
COMBINER)
IEEE
RF
3dB
MINI-CIRCUITS ZHL-42W
AMPLIFIER
(SUPPLIED WITH +15V DC FOR
OPERATION)
3dB
2dB
REF, LO
AGILENT E4437 SIGNAL GENERATOR
RF
RF SWITCH
MARTIX
IF
RF
LO, REF
6dB
10dB
6dB
IF
IEEE
IEEE
RHODE & SCHWARTZ FSEA30
AGILENT
34980A MULTIFUNCTION
SWITCH
(WITH 34950 AND
2× 34921 MODULES)
IEEE
10-PIN
CONNECTION
(+5V VPOS,
DC MEASURE)
IEEE
AGILENT E3631A
POWER SUPPLY
ADRF6655
EVALUATION BOARD
IEEE
9-PIN D-SUB CONNECTION
(VCO AND PLL PROGRAMMING)
AGILENT 34401A DMM
(DC I MODE, USED
FOR SUPPLY CURRENT
MEASUREMENT)
08817-116
IEEE
Figure 78. General Characterization Setup
Rev. 0 | Page 35 of 44
ADRF6655
IEEE
IEEE
RHODE & SCHWARTZ
SMA100 SIGNAL
GENERATOR
RHODE & SCHWARTZ
SMA100 SIGNAL
GENERATOR
IEEE
RF
AGILENT E4440A
SPECTRUM ANALYZER
REF
RF SWITCH
MATRIX
IEEE
IF
RF
LO, REF
IEEE
IF
AGILENT E5052 SIGNAL
SOURCE ANALYZER
IEEE
ADRF6655
EVALUATION BOARD
10-PIN
CONNECTION
(+5V VPOS,
DC MEASURE)
IEEE
AGILENT E3631A
POWER SUPPLY
AGILENT
34980A MULTIFUNCTION
SWITCH
(WITH 34950 AND
2× 34921 MODULES)
IEEE
9-PIN D-SUB CONNECTION
(VCO AND PLL PROGRAMMING)
AGILENT 34401A DMM
(DC I MODE, USED
FOR SUPPLY CURRENT
MEASUREMENT)
08817-117
IEEE
Figure 79. Phase Noise Setup
Rev. 0 | Page 36 of 44
ADRF6655
IEEE
IEEE
AGILENT 34980A
MULTIFUNCTION SWITCH
(WITH 34950 AND 34921 MODULES)
REF IN
6dB
IF OUT
IEEE
RF IN
6dB
AGILENT N8974A NOISE
FIGURE ANALYZER
IEEE
AGILENT E3631A POWER
SUPPLY
AGILENT 346B NOISE
SOURCE
AGILENT 34401A DMM
(IN DC I MODE FOR SUPPLY
CURRENT MEASUREMENT)
08817-118
10MHz
REFERENCE
ADRF6655
EVALUATION BOARD
IEEE
AGILENT 8665B LOW
NOISE SIGNAL
GENERATOR
Figure 80. Noise Figure Setup
AGILENT N8974A
NOISE FIGURE
ANALYZER
AGILENT 8665B LOW
NOISE SIGNAL
GENERATOR
AGILENT 346B NOISE
SOURCE
COMBINER
RF IN
ADRF6655
EVALUATION BOARD REF IN
Figure 81. Noise Figure with Presence of Blocker Signal
Rev. 0 | Page 37 of 44
RHODE & SCHWARTZ
SMA100
SIGNAL GENERATOR
08817-119
IF OUT
ADRF6655
EVALUATION BOARD LAYOUT AND THERMAL GROUNDING
An evaluation board is available for testing the ADRF6655. The standard evaluation is configured for downconversion applications. Table 5
provides the component values and suggestions for modifying component values for various modes of operation.
VCC_RF
VCC_LO
VCC_BB
VTUNE
R9
270Ω
R65
0Ω
C13
47nF
C40
OPEN
CP
R8
0Ω
3P3V_LDO
C41
10µF
R27
OPEN
C12
100pF
C11
0.1µF
R2
OPEN
C31
1nF
REFIN
R61
49.9Ω
R16
0Ω
REFOUT
DECL1
3
CP
4
GND
5
RSET
34
33
NC
GND
GND
LOP
35
VCCLO
VCC1
2
36
37
LON
DECL3
1
38
39
VTUNE
VCO_LDO
VCC
C10
100pF
IP3SET
40
R12
OPEN
C7
0.1µF
C8
100pF
C1
C2
100pF
10µF
R72
0Ω
32
VCC
31
C3
0.1µF
GND 30
R60
OPEN
R26
0Ω
IP3SET 29
VCC_RF
C24
100pF
GND 28
C27
0.1µF
C25
0.1µF
VCCMIX 27
6
REFIN
7
GND
8
MUXOUT
9
DECL2
C37
100pF
INP 26
ADRF6655
T4, T5
RF
C38
100pF
INN 25
GND 24
GND 23
R25
0Ω
VCC_BB
C22
100pF
C23
0.1µF
VCCV2I 22
CLK
LE
GND
NC
VCCLO
OUTN
OUTP
GND
GND 21
DATA
10 VCC2
GND
11
12
13
14
15
16
17
18
19
20
IFP
2.5V
C39
10µF
R18
C17
0Ω
0.1µF
C19
0.1µF
C35
OPEN
R47
0Ω
OUT
R58
R51
1kΩ
C33
330pF
OPEN
R52
1kΩ
C34
330pF
VCC_LO
C18
100pF
CLK
R30
100Ω
C21
R57
100Ω 100pF
C32
330pF
R43
0Ω
T3, T6
LE
R17
0Ω
VCC2
R3
10kΩ
L1
OPEN
VCC
DATA
VCC
C43
150pF
C16
100pF
R24
0Ω
C20
0.1µF
R48
0Ω
R44
OPEN
R73, R74
VCC
C42
150pF
L2
OPEN
0Ω
C36
OPEN
IFN
VCC
R50
1kΩ
C29
0.1µF
R59
0Ω
R35
100Ω
1
VTUNE
3
2
6
7
5
4
8
9
R36
0Ω
Figure 82. Evaluation Board Schematic
Rev. 0 | Page 38 of 44
08817-125
C9
0.1µF
VCC
C6 C5
1nF 1nF
R13
0Ω
R1
0Ω
L3
OPEN
R6
0Ω
T7, T8
R62
0Ω
R5
OPEN
R32
0Ω
VCC
NC
R37
0Ω
R10
68Ω
C15
4.7µF
R31
0Ω
C28
10µF
GND
C14
0.1µF
R7
0Ω
LO
R63
0Ω
R38
0Ω
R29
0Ω
ADRF6655
The package for the ADRF6655 features an exposed paddle
on the underside that should be well soldered to a low thermal
and electrical impedance ground plane. This paddle is typically
soldered to an exposed opening in the solder mask on the
evaluation board. Figure 83 illustrates the dimensions used
in the layout of the ADRF6655 footprint on the ADRF6655
evaluation board (1 mil. = 0.0254 mm).
Notice the use of nine via holes on the exposed paddle. These
ground vias should be connected to all other ground layers on the
evaluation board to maximize heat dissipation from the device
package. Under these conditions, the thermal impedance of the
ADRF6655 was measured to be approximately 29°C/W in still air.
.012
.035
08817-083
.050
Figure 84. Evaluation Board Top Layer
.168
.020
.177
.232
08817-085
.025
08817-084
Figure 83. Evaluation Board Layout Dimensions for the ADRF6655 Package
Figure 85. Evaluation Board Bottom Layer
Rev. 0 | Page 39 of 44
ADRF6655
Table 5. Evaluation Board Configuration Options
Component
VCC, GND, IP3SET, CP,
VCO_LDO, VCC_LO,
VCC_RF, VCC_BB, LE,
CLK, DATA
R1, R6, R7, R8, R17,
R18, R24, R25, R26,
R29, R31, R32, R36
Function
Power supply, ground, and other test points.
Default Condition
Not applicable
Power supply decoupling. Shorts or power supply decoupling resistors.
C1, C2, C7, C8, C9,
C10, C11, C12, C16,
C17, C18, C19, C20,
C21, C22, C23, C24,
C25, C27, C28, C29,
C39, C41, C42, C43
The capacitors provide the required decoupling of the supply-related pins.
C5, C6, T7, T8
External LO path. T7 and T8 provide different footprints for different LO
path transformer selections. C5 and C6 provide the necessary ac coupling.
R61, C31, R16
REFIN input path. R61 provides a broadband 50 Ω termination followed
by C31, an ac coupling capacitor. R16 provides an external connectivity
to the MUXOUT feature described in Register 4.
Loop Filter Component Options. A variety of loop filter topologies are
supported using component placements R9, R10, R13, R37, C13, C14,
C15, R65, and C40. R2 provides resistor programmability of the charge
pump current (see Register 4 description). R5, R38, R62, R63, and R72
provide connectivity options to numerous test points for engineering
evaluation purposes.
IF output path. This is the default configuration of the evaluation board
for downconversion applications. R73 and R74 are populated for
appropriate balun interface. The default values support a TC4-1W+ 4-to-1
impedance ratio transformer with center tap bias connection through
R59. A differential IF output interface can be configured by populating C35
and C36 and omitting R47 and R48. When configuring for differential output
operation or when using an ac-coupled transformer, it is important to use L1
and L2 to provide dc bias to the IF output pins. For additional information,
see the Output Matching and Biasing section.
RF input interface. T4 and T5 provide different footprints for different
RF path transformer selections. C37 and C38 provide the necessary ac
coupling. See the Input Matching section for additional information.
Serial port interface. A 9-pin D-sub connector is provided for connecting to a
host PC or control hardware. RC filter networks are provided on CLK, DATA,
and LE lines to help clean up PC control signal wave shape. Test points are
provided for control interface debug. R3 provides a connection to the
MUXOUT for sensing lock detect through the P1 connector. See the Digital
Interfaces section for additional information.
IP3SET linearization feature. R27 and R60 provision for a resistive divider
network for providing nominal IP3SET voltage. Alternatively, the IP3SET
pin can be externally driven via the test point or directly connected to
the 3.3 V LDO (Pin 2, DECL1) using a 0 Ω resistor for R12 and a ferrite chip
inductor for L3. For additional information regarding this feature, see the
IP3SET Linearization Feature section.
R1, R6, R7, R8 = 0 Ω (0402),
R17, R18 = 0 Ω (0402),
R24, R25, R26 = 0 Ω (0402),
R29, R31, R32 = 0 Ω (0402),
R36 = 0 Ω (0402)
C1, C8, C10 = 100 pF (0402),
C2, C39, C41 = 10 μF (0603),
C7, C9, C11 = 0.1 μF (0402),
C12, C16, C18 = 100 pF (0402),
C21, C22, C24 = 100 pF (0402),
C17, C19, C20 = 0.1 μF (0402),
C23, C25, C27 = 0.1 μF (0402),
C28 = 10 μF (3216),
C29 = 0.1 μF (0402),
C42, C43 = 150 pF (0402)
C5, C6 = 1 nF (0402),
T7 = open (generic footprint),
T8 = TC1-1-13M+ (Mini-Circuits)
R61 = 49.9 Ω (0402),
C31 = 1 nF (0402), R16 = 0 Ω (0402)
R2, R5, R9, R10, R13,
R37, R38, R62, R63,
R65, R72, C13, C14,
C15, C40
L1, L2, R43, R44,
R47, R48, R58, R59,
R73, R74, T3, T6,
C35, C36
C37, C38, T4, T5
P1, R3, R30, R35,
R50, R51, R52,
R57, C32, C33, C34
C3, R12, R27, R60, L3
Rev. 0 | Page 40 of 44
R2 = R5 = open, R9 = 270 Ω (0402),
R10 = 68 Ω (0402), R13 = 0 Ω (0402)
C13 = 47nF, C14 = 0.1μF,
C15 = 4.7μF (0805),
C40 = open (0402),
R37, R38, R62, R63, R65, R72 = 0 Ω (0402)
L1, L2 = open, R44, R58, = open,
R43, R47, R48 = 0 Ω (0402),
R59, R73, R74 = 0 Ω (0402),
T3 = TC4-1W+ (Mini-Circuits),
T6 = open, C35, C36 = open
C37, C38 = 100 pF (0402),
T4 = TC1-1-13M+ (Mini-Circuits),
T5 = open
P1 = 9-pin D-sub male,
R3 = 10 kΩ (0402),
R30, R35, R57 = 100 Ω (0402),
R50, R51, R52 = 1 kΩ (0402),
C32, C33, C34 = 330 pF (0402)
C3 = 0.1 μF (0402), R12 = open,
R27, R60 = open, L3 = open
ADRF6655
OUTLINE DIMENSIONS
6.00
BSC SQ
0.60 MAX
0.60 MAX
TOP
VIEW
0.50
BSC
5.75
BSC SQ
0.50
0.40
0.30
12° MAX
0.80 MAX
0.65 TYP
0.30
0.23
0.18
1
4.25
4.10 SQ
3.95
EXPOSED
PAD
(BOT TOM VIEW)
21
20
11
10
0.25 MIN
4.50
REF
0.05 MAX
0.02 NOM
SEATING
PLANE
40
0.20 REF
COPLANARITY
0.08
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
COMPLIANT TO JEDEC STANDARDS MO-220-VJJD-2
072108-A
PIN 1
INDICATOR
1.00
0.85
0.80
PIN 1
INDICATOR
31
30
Figure 86. 40-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
6 mm × 6 mm Body, Very Thin Quad
(CP-40-1)
Dimensions shown in millimeters
ORDERING GUIDE
Model 1
ADRF6655ACPZ-R7
ADRF6655-EVALZ
1
Temperature
−40°C to +85°C
Package Description
40-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
Evaluation Board
Z = RoHS Compliant Part.
Rev. 0 | Page 41 of 44
Package Option
CP-40-1
Quantity
750
ADRF6655
NOTES
Rev. 0 | Page 42 of 44
ADRF6655
NOTES
Rev. 0 | Page 43 of 44
ADRF6655
NOTES
©2010 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D08817-0-2/10(0)
Rev. 0 | Page 44 of 44