SAMSUNG S1M8837

FRACTIONAL-N RF/INTEGER-N IF DUAL PLL
S1M8836/37
INTRODUCTION
24-QFN-3.5×4.5
The S1M8836/37 is a Fractional-N frequency synthesizer with integrated
prescalers, designed for RF operation up to 1.0GHz/2.5GHz and for IF
operation up to 520MHz. The fractional-N synthesizer allows fast-locking, low
phase noise phase-locked loops to be built easily, thus having rapid channel
switching and reducing standby time for extended battery life. The S1M8836/37
based on Σ - ∆ fractional-N techniques solves the fractional spur problems in
other fractional-N synthesizers based on charge pump compensation. The
synthesizer also has an additional feature that the PCS/CDMA channel
frequency in steps of 10kHz can be accurately programmed.
The S1M8836/37 contains quadruple-modulus prescalers. The S1M8836 RF
synthesizer adopts an 8/9/12/13 prescaler(16/17/20/21 for the S1M8837) and the IF synthesizer adopts an 8/9
prescaler. Phase detector gain is user-programmable for maximum flexibility to address IS-95 CDMA and
IMT2000. Various program-controlled power down options as well as low supply voltage help the design of
wireless cell phones having minimum power consumption.
Using the Samsung's proprietary digital phase-locked-loop technique, the S1M8836/37 has a linear phase
detector characteristic and can be used for very stable, low noise PLL's. Supply voltage can range from 2.7V to
4.0V. The S1M8836/37 is available in a 24-QFN package.
FEATURES
•
High operating frequency dual synthesizer
•
Operating voltage range : 2.7 to 4.0V
•
Low current consumption(S1M8836: 5.5mA, S1M8837: 7.5mA)
•
Selectable power saving mode (Icc = 1uA typical @3V)
•
Quadruple-modulus prescaler and Fractional-N/Integer-N:
 S1M8836
(RF) 8/9/12/13
Fractional-N
 S1M8837
(RF) 16/17/20/21
Fractional-N
 S1M8836/37
(IF) 8/9
Integer-N
•
S1M8836: 250MHz to 1.0GHz(RF) / 45MHz to 520MHz(IF)
•
S1M8837: 500MHz to 2.5GHz(RF) / 45MHz to 520MHz(IF)
•
Excellent in-band phase noise ( – 85dBc/Hz @ PCS, – 90dBc/Hz @ CDMA)
•
Improved fractional spurious performance ( < 80dBc )
•
Frequency resolution (= 10kHz/64 @ fref = 9.84MHz)
•
Fast channel switching time: <500us
•
Programmable charge pump output current: from 50µA to 800µA in 50µA steps
•
Programmability via on-chip serial bus interface
1
S1M8836/37
FRACTIONAL-N RF/INTEGER-N IF DUAL PLL
APPLICATIONS
•
High-rate data-service cellular telephones (for CDMA) : S1M8836, S1M8837
•
High-rate data-service portable wireless communications : S1M8837
•
Other wireless communications systems
ORDERING INFORMATION
Device
Package
Operating Temperature
+ S1M8836X01-G0T0
24-QFN-3.5×4.5
-40 to +85C
+ S1M8837X01-G0T0
+: New Product
2
FRACTIONAL-N RF/INTEGER-N IF DUAL PLL
S1M8836/37
BLOCK DIAGRAM
VDDRF
1
VPRF
2
OUT0
OUT1
VDDIF
24
23
22
RF
LD
3
DGND
4
RF
Phase
Detector
IF
Phase
Detector
fin RF
6
IF Prescaler
+-
- +
RF
Programmable
Counter
Prescaler
Control
5
IF
Charge
Pump
20 CPOIF
RF Prescaler
fin RF
IF
LD
21 VPIF
RF
Charge
Pump
CPORF
foLD Data Out
Multiplexer
IF
Programmable
Counter
RF N-Latch
19 DGND
Prescaler
Control
18 finIF
17 finIF
IF N-Latch
2-Bit
Control
GNDRF
7
VDDRFa
8
OSCin
9
Frac-N Latch &
Σ −∆ Modulator
20-Bit Shift Register
RF R-Latch
IF R-Latch
RF Reference
Counter
IF Reference
Counter
16 GNDIF
15 LE
14 DATA
13 CLOCK
10
11
12
foLD
RF_EN
IF_EN
3
S1M8836/37
FRACTIONAL-N RF/INTEGER-N IF DUAL PLL
PIN DIAGRAM
OUT0
OUT1
VDDIF
24
23
22
VDDRF
1
21 VPIF
VPRF
2
20 CPOIF
CPORF
3
19 DGND
DGND
4
18 finIF
finRF
5
finRF
6
16 GNDIF
GNDRF
7
15 LE
VDDRFa
8
14 DATA
OSCin
9
13 CLCOK
10
11
12
foLD
RF_EN
IF_EN
24-QFN
4
17 finIF
S1M8836/37
FRACTIONAL-N RF/INTEGER-N IF DUAL PLL
S1M8836/37
PIN DESCRIPTION
Pin No.
Symbol
I/O
Descriptions
1
VDDRF
–
RF PLL power supply (2.7V to 4.0V). Must be equal to VDDIF.
2
VpRF
–
Power supply for RF charge pump. Must be ≥ VDDRF and VDDIF.
3
CPoRF
O
RF charge pump output. Connected to an external loop filter.
4
DGND
–
Ground for RF PLL digital circuitry.
5
finRF
I
RF prescaler input. Small signal input from the external VCO.
I
6
finRF
RF prescaler complementary input. For a single-ended output RF VCO, a bypass
capacitor should be placed as close as possible to this pin and be connected
directly to the ground plane.
7
GNDRF
–
Ground for RF PLL analog circuitry.
8
VDDRFa
–
PLL power supply (2.7V to 4.0V) for RF analog (prescaler). Must be equal to VDDRF
9
OSCin
I
Oscillator input to drive both the IF and RF R counter inputs.
10
foLD
O
Multiplexed output of N or R divider and RF/IF lock detect.
11
RF_EN
I
RF PLL Enable (Enable when HIGH, Power down when LOW). Controls the RF PLL
to power down directly, not depending on a program control. Also sets the charge
pump output to be in TRI-STATE when LOW. Powers up when HIGH depends on
the state of RF_CTL_WORD.
12
IF_EN
I
IF PLL Enable (Enable when HIGH, Power-down when LOW). Controls the IF PLL
to power down directly. The same as RF_EN except that power-up depends on the
state of IF_CTL_WORD.
13
CLOCK
I
CMOS clock input. Data for the various counters is clocked into the 22-bit shift
register on the rising edge.
14
DATA
I
Binary serial data input. Data entered MSB (Most Significant Bit) first.
15
LE
I
Load enable when LE goes HIGH. High impedance CMOS input.
16
GNDIF
–
Ground for IF analog circuitry.
17
finIF
I
IF prescaler complementary input. For a single-ended output IF VCO, a bypass
capacitor should be placed as close as possible to this pin.
18
finIF
I
IF prescaler input. Small signal input from the VCO.
19
DGND
–
Ground for IF PLL digital circuitry.
20
CPoIF
O
IF charge pump output. Connected to an external loop filter.
21
VpIF
–
Power supply for IF charge pump. Must be ≥ VDDRF and VDDIF.
22
VDDIF
–
IF PLL power supply (2.7V to 4.0V). Must be equal to VDDRF.
23
OUT1
O
Programmable CMOS output. Level of the output is controlled by W2[19] bit.
24
OUT0
O
Programmable CMOS output. Level of the output is controlled by W2[18] bit.
In the Speedy Lock mode, the OUT0 and OUT1 pins can be utilized as synchronous
switches between active low and tri-state.
5
FRACTIONAL-N RF/INTEGER-N IF DUAL PLL
S1M8836/37
EQUIVALENT CIRCUIT DIAGRAM
CLOCK, DATA, LE
foLD
OSCin
CPORF, CPOIF
finRF, finRF, finIF, finIF
finRF, finIF
finRF, finIF
Vbias
6
FRACTIONAL-N RF/INTEGER-N IF DUAL PLL
S1M8836/37
ABSOLUTE MAXIMUM RATINGS
Characteristics
Symbol
Value
Unit
VDD
0.0 to 4.0
V
Voltage on any pin with GND = 0 volts
VI
-0.3 to VDD + 0.3
V
Power dissipation
PD
600
mW
Operating temperature
Ta
-40 to +85
°C
TSTG
-65 to +150
°C
Pin No.
ESD level
Unit
Human Body Model
All
<± 2000
V
Machine Model
All
<± 300
V
Charge Device Model
All
<± 800
V
Power supply voltage
Storage temperature
ELECTROSTATIC CHARACTERISTICS
Characteristics
NOTE: These devices are ESD sensitive. These devices must be handled in an ESD protected environment.
7
S1M8836/37
FRACTIONAL-N RF/INTEGER-N IF DUAL PLL
ELECTRICAL CHARACTERISTICS
(VDD=3.0V, Vp=3.0V, Ta = 25°C, unless otherwise specified.)
Characteristic
Power supply voltage
Power supply
S1M8836
RF+IF
current
Symbol
Min.
Typ.
Max.
Unit
VDD
2.7
3.0
4.0
V
VP
VDD
3.0
4.0
IDD
Test Conditions
Fractional-N mode
5.5
S1M8837
RF+IF
(fosc=19.68MHz, RF R=2)
7.5
S1M8836
RF+IF
Quiescent State
4.0
S1M8837
RF+IF
6.0
IF only
1.5
Power down current
IPWDN
VDD=3.0V
1
mA
10
µA
Digital Inputs: CLOCK, DATA and LE
High Level Input Voltage
VIH
VDD=2.7V to 4.0V
0.7VD
V
D
Low Level Input Voltage
VIL
VDD=2.7V to 4.0V
0.3VD
V
D
High Level Input Current
IIH
VIH=VDD=4.0V
-1.0
+1.0
µA
Low Level Input Current
IIL
VIL=0V, VDD=4.0V
-1.0
+1.0
µA
IIHR
VIH=VDD=4.0V
+100
µA
IILR
VIL=0V, VDD=4.0V
-100
µA
High Level Output Voltage
VOH
Iout=-500µA
VDD-0.4
V
Low Level Output Voltage
VOL
Iout=+500µA
Reference Oscillator Input: OSCin
Input Current
Digital Output: foLD
8
0.4
V
FRACTIONAL-N RF/INTEGER-N IF DUAL PLL
S1M8836/37
ELECTRICAL CHARACTERISTICS (Continued)
(VDD=3.0V, Vp=3.0V, Ta = 25°C, unless otherwise specified.)
Characteristic
Symbol
Charge Pump Outputs: CPoRF, CPoIF
RF Charge Pump Output
Current
ICPRF
SOURCE_min
ICPRFSINK_min
ICPRFSOURCE_max
ICPRFSINK_max
IF Charge Pump Output Current
ICPRF
Test Conditions
Min.
Typ.
Max.
Unit
-50
µA
+50
µA
-800
µA
+800
µA
-100
µA
VCP=VP/2,CP_GAIN_8=0
+100
µA
VCP=VP/2,CP_GAIN_8=1
-800
µA
VCP=VP/2,CP_GAIN_8=1
+800
µA
VCP=VP/2,
RF_CP_WORD=0000
VCP=VP/2,
RF_CP_WORD=0000
VCP=VP/2,
RF_CP_WORD=1111
VCP=VP/2,
RF_CP_WORD=1111
VCP=VP/2,CP_GAIN_8=0
SOURCE_min
ICPRF
SINK_min
ICPRF
SOURCE_max
ICPRF
SINK_max
ICPL
0.5V ≤ VCP ≤ VP-0.5V
Sink vs. Source Mismatch
ICP-SINK vs
ICP-SOURCE
VCP=VP/2
Output Current Magnitude
Variations. Voltage
Output Current vs. Temperature
ICP VS VCP
ICP VS Ta
Charge Pump Leakage Current
+2.5
nA
3
10
%
0.5V ≤ VCP ≤ VP-0.5V
10
15
%
VCP=VP/2
10
Operating Frequency, Input Sensitivity (Programmable Divider, PFD)
f inRF
RF Operating
S1M8837
Fractional-N mode
(fosc=19.68MHz, RF R=2)
Frequency
S1M8836
IF Operating Frequency
Reference Oscillator Input
Frequency
Phase Detector Operating
Frequency
RF Input Sensitivity
f inIF
-2.5
0.5
2.5
GHz
Fractional-N mode
(fosc=19.68MHz, RF R=2)
0.25
1.0
GHz
VDD=3.0V
45
520
MHz
2
40
MHz
10
MHz
OSCin
f PD
PfinRF
IF Input Sensitivity
PfinIF
Reference Oscillator Input
Sensitivity
VOSCin
%
VDD=3.0V
-15
0
dBm
VDD=4.0V
-10
0
dBm
VDD=2.7V to 4.0V
-10
0
dBm
0.5
VDD
VPP
9
S1M8836/37
FRACTIONAL-N RF/INTEGER-N IF DUAL PLL
ELECTRICAL CHARACTERISTICS (Continued)
(VDD=3.0V, Vp=3.0V, Ta = 25°C, unless otherwise specified.)
Characteristic
Symbol
Test Conditions
Min.
Typ.
Max.
Unit
10
MHz
Serial Data Control
CLOCK Frequency
f CLOCK
CLOCK Pulse Width High
tCWH
50
ns
CLOCK Pulse Width Low
tCWL
50
ns
DATA Set Up Time to CLOCK
Rising Edge
tDS
50
ns
DATA Hold Time after CLOCK
Rising Edge
tDH
10
ns
LE Pulse Width
tLEW
50
ns
CLOCK Rising Edge to LE Rising Edge
tCLE
50
ns
10
FRACTIONAL-N RF/INTEGER-N IF DUAL PLL
S1M8836/37
FUNCTIONAL DESCRIPTION
finRF
finRF
RF
Prescaler
+
-
RF
N Counter
RF
Phase
Detector
Serial Data Control
RF
R Counter
finIF
finIF
+
-
IF
Prescaler
IF
N Counter
CMOS
Output
MUX
OUT0
foLD
Data Out
Multiplexer
foLD
CMOS
Output
MUX
IF
R Counter
OSC in
CP oRF
RF
LD
∑-∆
Modulator
CLOCK
DATA
LE
RF
Charge
Pump
OUT1
IF
LD
IF
Phase
Detector
IF
Charge
Pump
CP oIF
The Samsung S1M8836/37 is RF/IF dual frequency synthesizer IC which supports Fractional-N mode for RF PLL
and Integer-N mode for IF PLL depending on a program control. S1M8836/37 combined with an external LPF and
an external VCO forms PLL frequency synthesizer. The frequency synthesizer consists of prescalers, pulseswallowed programmable N counters, programmable reference R counters, phase detectors, programmable
charge pumps, analog LD(lock detector), serial data control, etc.
An input buffer in the prescaler amplifies the RF input power of -10dBm from the external RF/IF VCO to the
sufficient ECL switching level to drive the following ECL divider so that it can be normally operated even in a
smaller input power less than -10dBm. The amplified VCO output signal is divided by the prescaler with a predetermined divide ratio (div. 8/9/12/13 for S1M8836, div. 16/17/20/21 for S1M8837, div. 8/9 for IF), the N counter
and the Fractional-N circuitry( Σ - ∆ modulator). External reference signal is divided by the R counter to set the
comparison frequency of the PFD. The divide ratios of the programmable counters can be programmed via the
serial bus interface. These two signals drive the both inputs of the phase detector. The phase detector drives the
charge pump by comparing frequencies and phases of the above two signals. The charge pump and the external
LPF make the control voltage for the external VCO and finally the VCO generates the appropriate frequency
signal.
11
S1M8836/37
FRACTIONAL-N RF/INTEGER-N IF DUAL PLL
When the PLL is in the locked state, the RF VCO's frequency will be NINT + NFRAC times the comparison
frequency, where NINT is the integer divide ratio and NFRAC is the fractional component.
The S1M8836/37 has new improved features compared to conventional Integer-N PLLs.
The fractional-N PLL is available for the RF. The fractional synthesis frequency as is AMPS and IS-95A/B/C.
This makes it possible to widen the loop bandwidth as wide as 20kHz or wider for a faster lock-up time and to
improve the in-band phase noise performance due to the reduced divide ratio N. Such S1M8836/37 in the
fractional-N mode is suitable for CDMA, GSM and PCS band applications.
Also, from the programmability of the charge pump, the users can easily design a stable loop by free selection of
loop components and reach to the low spurious, the low power PLL by an optimized current selection.
Prescaler
The RF/IF prescaler consists of a differential input buffer and ECL frequency dividers. The input buffer amplifies
the input signal from the external VCO to the required level set by sensitivity requirements. The output of the
amplifier delivers a differential signal to the divider with the correct DC level. The buffer may be either singleended or differentially driven. The single-ended operation is preferred in typical applications due to external VCO.
In this case, we recommend that the complementary input /fin of the input buffer be AC coupled to ground
through external capacitors, even though it is internally coupled to ground via an internal 10pF capacitor. The
other input pin fin of the buffer also needs external capacitor for decoupling the DC component and controlling
the input power level.
The RF prescalers of S1M8836 and S1M8837 provide 8/9/12/13 and 16/17/20/21 prescaler ratio, respectively.
The IF prescaler of S1M8836/37 contains 8/9 dual modulus prescaler.
Reference Oscillator Inputs
The reference oscillator frequency is provided by an external reference such as TCXO through the OSCin.
It drives both the IF R and RF R counters.
Programmable Dividers (RF/IF N Counters)
The RF N counter can be configured as a fractional counter. The fractional-N counter is selected when the
Frac-N_SEL bit becomes HIGH.
In the fractional mode, the S1M8836 is capable of offering a continuous integer divide range from 25 to 1023 and
the S1M8837 offering a continuous integer divide range from 49 to 2047.
The S1M8836/37 IF N counter supports an integer counter mode only, not including fractional counter, and is
capable of operating from 45MHz to 520MHz offering a continuous integer divide range from 72 to 32767.
12
FRACTIONAL-N RF/INTEGER-N IF DUAL PLL
S1M8836/37
Σ - ∆ modulator
The RF part of S1M8836/37 adopts the Σ - ∆ modulator as a core of the fractional counter that makes it possible
to obtain divide ratio N to be a fractional number between two contiguous integers. The Σ - ∆ modulator
effectively randomizes the quantization noise generated from digitizing process and results in extreme
suppression of in-band noise power by pushing it out to out-of-band as in conventional Σ - ∆ data converter.
This technique eliminates the need for compensation current injection into the loop filter and improves fractional
spurious performance, suitable for high-tier applications.
The Σ - ∆ modulator operates only for fractional-N mode, when the Frac-N_SEL is HIGH.
For proper use of the fractional mode, the user should be kept in mind that
1. A fractional number should be set in the range from -0.5 to 0.5 in step of 1/62976.
2. For S1M8836/7, R can be selected 1-3. The clock frequency fixed at 9.84MHz (=19.68MHz/2, R=2) is
recommended for the Σ - ∆ modulator which is an optimum condition for achieving good electrical
performances related to the fractional noise and power consumption. Only when using this clock frequency,
the S1M8836/37 guarantees the exact frequency resolutions: 10kHz for CDMA PCS and 30kHz for CDMA
cellular.
Note that the clock frequency much lower than 9.84MHz can deteriorate the fractional noise performance.
Users can use R=1 or R=3, too. For the case of R=1 or R=3, users must ask SAMSUNG for details.
Fractional noise performance may become better for R=1 (clock frequency=19.68MHz/1=19.68MHz). But the
RF operating frequency range may be shrinked for that case of R=1.
Phase-Frequency Detector (PFD) and Charge Pump (CP)
The RF/IF phase detector composed of PFD and CP outputs pump current into an external loop filter in
proportional to the phase difference between outputs of N and R counter. The phase detector has a better linear
transfer characteristic due to a feedback loop to eliminate dead zone. The polarity of the PFD can be
programmed using RF_PFD_POL/IF_PFD_POL depending on whether RF/IF VCO characteristics are positive or
negative. (Programmable descriptions for phase detection polarity)
Power-Down(or Power-Save) Control
Each PLL is individually power controlled by the enable pins (RF_EN and IF_EN pins) or program control bits
(PWDN, PWDN_RF/IF). The enable pins override the program control bits. When both enable pins are HIGH, the
program control bits determine the state of power control. Power down forces all the internal blocks to be
deactivated and the charge pump output to be in the TRISTATE. The control register, however, remains active
for serial programming and is capable of loading and latching in data during the power down.
13
S1M8836/37
FRACTIONAL-N RF/INTEGER-N IF DUAL PLL
Programming Description
The S1M8836/37 can be programmed via the serial bus interface. The interface is made of 3 functional signals:
clock, data, and latch enable(LE). Serial data is moved into the 22-bit shift register on the rising edge of the
clock. These data enters MSB first. When LE goes HIGH, data in the shift register is moved into one of the 4
latches (by the 2-bit control).
MSB
LSB
Data Flow (MSB First)
DATA[21:2]
CTL[1:0]
Control Bit Map (CTL[1:0])
Control Bits
DATA Location
CTL2(CTL[1])
CTL1(CTL[0])
0
0
WORD1
0
1
WORD2
1
0
WORD3
1
1
WORD4
Data Bit Map (DATA[21:2])
First Bit
REGISTER BIT LOCATION
21 20 19 18 17 16 15 14 13 12 11 10
WORD1(W1)
IF_CTL_
WORD
RF_R
(2Bit)
WORD2(W2)
CMOS
IF_CP_
WORD
WORD3(W3)
FoLD(4Bit)
9
8
Last Bit
7
6
5
4
3
2
IF _R_CNTR(15Bit)
RF_CP_WORD
IF_NB_CNTR(12Bit)
RF_NB_CNTR(7Bit)
1
0
0 0
IF_NA_
CNTR(3Bit)
0 1
RF_NA_CNTR
(36:3Bit)
1 0
RF_NA_CNTR
(37:4Bit)
WORD4(W4)
14
RF_CTL_
WORD
FRAC_CNTR(17Bit)
1 1
FRACTIONAL-N RF/INTEGER-N IF DUAL PLL
S1M8836/37
Data Bit Map (DATA[21:2]) (Continued)
Control Words
Control
bits
IF_CTL_WORD
W1[21]
IF_CNT_RST
normal operation
IF counter reset
IF
W1[20]
PWDN_IF
power up
power down
IF
W1[19]
PWDN
asynchronous
power down
synchronous
power down
RF and IF
W2[21]
Speedy_Lock
CMOS output
Speedy_Lock
mode
W2[20]
OUT1
voltage LOW
voltage HIGH
pin #23
W2[19]
OUT0
voltage LOW
voltage HIGH
pin #24
W2[18]
IF_CP_GAIN
1X
8X
IF charge
pump
W2[17]
IF_PFD_POL
negative slope
positive slope
IF PFD
CMOS
IF_CP_WORD
foLD
W3[21:18]
RF_CP_WORD
W3[17:14]
RF_CTL_WORD
Acronym
foLD
LOW (0)
HIGH (1)
Comments
select LDs and monitoring mode of
internal counters. (FoLD control for
control codes in detail)
Lock
Detector(LD),
Test mode
RF_CP_LVL
select 16-level charge pump current (RF
charge pump gain for control codes in
detail)
RF charge
pump
W3[13]
RF_PFD_POL
negative slope
positive slope
RF PFD
W4[21]
RF_CNT_RST
normal operation
RF counter reset
RF
W4[20]
PWDN_RF
power up
power down
RF
W4[19]
Frac-N_SEL
Integer-N mode
Fractional-N
mode
RF; PLL mode
selection
— Counter Reset mode resets R & N counters.
— IF charge pump current can be selected to high current(8X) or low current(1X) mode.
— In the Speedy_Lock mode, the OUT0 and OUT1 pins can be utilized as synchronous switches between active
low and tri-state. The Speedy_Lock mode activates the OUT0 and OUT1 pins to be connected to GROUND
with a low impedance(< 150Ω) while a high charge pump gain( ≥ 8X) is selected and otherwise to the
TRISTATE.
— For using a programmable CMOS output, the CMOS output bit(W2[21]=L) should be activated and then the
desired logic level should be programmed with the control bits W2[19] for OUT0 and W2[20] for OUT1.
15
S1M8836/37
FRACTIONAL-N RF/INTEGER-N IF DUAL PLL
Programmable Reference Counter(W1[18:2])
If the Control Bit is 00, data is moved from the 22-bit shift register into the R-latch which sets the IF reference
counter. Serial data format is shown in the table below.
MSB
W1[21:0]
IF_CTL_WORD[21:19]
21
LSB
RF_R_CNTR[[18:17]: 1~3
19 18
Program Code
IF_R_CNTR[16:2]: 3~32767
0
17 16
21
Division Ratio of the RF R
Counter,RF_R_CNTR
0
0
Division Ratio of the
IF R Counter, IF_R_CNTR
Control Bits
•
15-Bit IF R Counter Division Ratio
Division ratio : 3 to 32767(The divide ratios less than 3 are prohibited)
Data are shifted in MSB first.
Division
Ratio
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
3
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
4
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
32767
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
•
RF R Counter Division Ratio
Division ratio : 1 to 3
16
Division Ratio
1
0
1
0
0
1
0
1
2
1
0
3
1
1
FRACTIONAL-N RF/INTEGER-N IF DUAL PLL
S1M8836/37
Programmable Counter(N Counter)
If the Control Bits are 01(IF), 10, and 11(RF), data is transferred from the 22-bit shift register into the N/Fraclatch. N Counter consists of swallow counter(A counter; 3-bit for IF & S1M8836RF and 4-bit for S1M8837RF),
main counter(B counter; 7-bit for S1M8836/37 RF and 12-bit for IF), and fractional counter(F counter; 17-bit for
S1M8836/37 RF). Serial data format is shown below.
IF N Counter
MSB
W2[21:0]
IF_CP_WORD
[18:17]
CMOS
19 18
21
LSB
IF_NA_CNTR[4:2] :
0-7
IF_NB_CNTR[16:5] : 3 - 4095
0
54
17 16
Program Code
21
1
0
Division Ratio of the IF N Counter
Control Bits
•
IF Main Counter Division Ratio(B Counter)
IF_NB_ CNTR[16:5] ; for S1M8836/37
Division
Ratio(B)
11
10
9
8
7
6
5
4
3
2
1
0
3
0
0
0
0
0
0
0
0
0
0
1
1
4
0
0
0
0
0
0
0
0
0
1
0
0
•
•
•
•
•
•
•
•
•
•
•
•
•
4095
1
1
1
1
1
1
1
1
1
1
1
1
Division ratio: 3 to 4095 (The division ratios less than 3 are prohibited)
•
Swallow Counter Division Ratio (A Counter)
IF_NA_CNTR[4:2] ; for S1M8836/37
Division Ratio(A)
2
1
0
0
0
0
0
1
0
0
1
•
•
•
•
7
1
1
1
Division Ratio: 0 to 7, B>A
17
S1M8836/37
FRACTIONAL-N RF/INTEGER-N IF DUAL PLL
RF N Counter
MSB
W3[21:0]
RF_CP_WORD
[17:13]
FoLD[21:18]
18 17
21
LSB
RF_NA_CNTR[5:2]
RF_NB_CNTR[12:6] : 3 ~ 127
13 12
65
1
0
21
0
Division Ratio of the
RF N Counter
Program Code
Control Bits
•
RF Main Counter Division Ratio (B Counter)
RF_NB_ CNTR[12:6] ; for S1M8836/37
Division
Ratio(B)
6
5
4
3
2
1
0
3
0
0
0
0
0
1
1
4
0
0
0
0
1
0
0
•
•
•
•
•
•
•
•
7
1
1
1
1
1
1
1
Division ratio : 3 to 127 (The division ratios less than 3 are prohibited)
•
RF Swallow Counter Division Ratio (A Counter)
RF_NA_CNTR[5:2] ; for S1M8836
Division Ratio(A)
3
2
1
0
0
X
0
0
0
1
X
0
0
1
•
•
•
•
•
7
X
1
1
1
Division Ratio(A)
3
2
1
0
0
0
0
0
0
1
0
0
0
1
•
•
•
•
•
15
1
1
1
1
Division Ratio : 0 to 7
X = Don't care condition
RF_NA_CNTR[5:2] ; for S1M8837
NOTE: Division Ratio: 0 to 15
X = Don't care condition
18
FRACTIONAL-N RF/INTEGER-N IF DUAL PLL
S1M8836/37
RF Fractional Counter
MSB
W4[21:0]
LSB
RF_CTL_WORD[21:19]
FRAC_CNTR[18:2]
21
1
19 18
1
21
0
Division Ratio of the RF Fractional
Counter
Program Code
Control Bits
•
RF Fractional Counter Value (F Counter)
FRAC_ CNTR[18:2] ; for S1M8836/37 RF
Counter Value (F)
F
16
F
15
F
14
F
13
F
12
F
11
F
10
F9 F8 F7 F6 F5 F4 F3 F2 F1 F0
31488
0
0
1
1
1
1
0
1
1
0
0
0
0
0
0
0
0
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
2
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
-1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
-2
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
-31488
1
1
0
0
0
0
1
0
1
0
0
0
0
0
0
0
0
F Counter Value: -31488(2's complementary) to 31488
NOTE: For a negative integer, the counter value should be inputted as the corresponding 2's complementary binary
code.
For instance, the 2's complementary binary code of -2 is 1 1111 1111 1111 1110.
19
S1M8836/37
FRACTIONAL-N RF/INTEGER-N IF DUAL PLL
Programmable PFD and Charge Pump
IF Charge Pump Gain ( IF_CP_WORD; W2[18] )
Control Words
Control bits
Acronym
LOW (0)
HIGH (1)
Comments
IF_CP_WORD
W2[18]
IF_CP_GAIN
1x (100µA)
8x (800µA)
IF charge pump
LOW (0)
HIGH (1)
Comments
RF Charge Pump Gain ( RF_CP_WORD; W3[17:14] )
Control Words
Control bits
Acronym
RF_CP_WORD
W3[17:14]
RF_CP_LVL
Icpo (µ
µA)
select 16-level charge pump current
RF charge pump
8X
4X
2X
1X
W3[17]
W3[16]
W3[15]
W3[14]
50
0
0
0
0
100
0
0
0
1
•
•
•
•
•
200
0
0
1
1
250
0
1
0
0
•
•
•
•
•
400
0
1
1
1
450
1
0
0
0
•
•
•
•
•
800
1
1
1
1
Phase Detector Polarity ( RF_CP_WORD/IF_CP_WORD; W3[13]/W2[17] )
Depending on VCO characteristics, W2[17] and W3[13] bits should be set as follows :
20
Control bits
LOW (0)
HIGH (1)
Comments
W2[17]
Negative Slope
Positive Slope
IF PFD
W3[13]
Negative Slope
Positive Slope
RF PFD
FRACTIONAL-N RF/INTEGER-N IF DUAL PLL
S1M8836/37
VCO Characteristics
(1)
VCO
Output
Frequency
(2)
VCO Input
Voltage
Program Mode Control
Power down mode operation
Control Words
Control bits
Acronym
LOW (0)
HIGH (1)
Comments
IF_CTL_WORD
W1[20]
PWDN_IF
power up
power down
IF
W1[19]
PWDN
asynchronous
power down
synchronous power
down
RF and IF
W4[20]
PWDN_RF
power up
power down
RF
RF_CTL_WORD
Each PLL is individually power controlled by the enable pins (RF_EN and IF_EN pins) or program control bits
(PWDN, PWDN_RF/IF). The enable pins override the program control bits. When both enable pins are HIGH, the
program control bits determine the state of power control. Power down forces all the internal analog blocks to be
deactivated and the charge pump output to be in a TRISTATE. The oscillator buffer is powered down when the
power down bits (W4[20] and W1[20]) become HIGH. The control register and R/N counters, however, remains
active for permitting serial programming and is capable of loading and latching in data during the power down.
There are synchronous and asynchronous power-down modes for S1M8836/37. The power-down bit W1[19] is
used to select between synchronous and asynchronous power-down. Synchronous power-down mode occurs if
W1[19] bit is HIGH and then the power down bit (W4[20] or W1[20]) becomes HIGH. In the synchronous power
down mode, the power-down function will go into power-down mode upon the completion of a charge pump pulse
event because it is synchronized with the charge pump and thus can diminish undesired frequency jumps.
Asynchronous power down mode occurs if W1[19] bit is LOW and then the power down bit (W4[20] or W1[20])
becomes HIGH. Activation of the asynchronous function will go into power-down mode immediately.
RF Power down mode table
W4[20]
W1[19]
Power down mode status
0
0
RF PLL active
0
1
RF PLL active, only charge pump to TRISTATE
1
1
Asynchronous power down
1
1
Synchronous power down
21
S1M8836/37
FRACTIONAL-N RF/INTEGER-N IF DUAL PLL
IF Power down mode table
W1[20]
W1[19]
Power down mode status
0
0
IF PLL active
0
1
IF PLL active, only charge pump to TRISTATE
1
0
Asynchronous power down
1
1
Synchronous power down
Programmable Counter Reset Control
Control Words
Control bits
Acronym
LOW (0)
HIGH (1)
Comments
IF_CTL_WORD
W1[21]
IF_CNT_RST
normal operation
IF counter reset
IF
RF_CTL_WORD
W4[21]
RF_CNT_RST
normal operation RF counter reset
RF
Counter Reset mode resets R & N counters.
RF Fractional-N selection
Control Words
Control bits
Acronym
LOW (0)
HIGH (1)
RF_CTL_WORD
W4[19]
Frac_N_SEL
reserved
Fractional-N mode
Comments
RF;PLL mode
selection
CMOS Output Control
Control Words
Control bits
Acronym
LOW (0)
HIGH (1)
Comments
CMOS
W2[21]
Speedy Lock
CMOS output
Speedy Lock
mode
W2[20]
OUT1
voltage LOW
voltage HIGH
pin #23
W2[19]
OUT0
voltage LOW
voltage HIGH
pin #24
In the Speedy Lock mode, the OUT0 and OUT1 pins can be utilized as synchronous switches between active low
and a tri-state. The Speedy Lock mode activates the OUT0 and OUT1 pins to be connected to GROUND with a
low impedance(< 150Ω) while a high charge pump gain(≥ 8X) is selected and otherwise to a tri-state. For using a
programmable CMOS output, the CMOS output bit(W2[21]= LOW) should be activated and then the desired logic
level should be programmed with the control bits W2[19] for OUT0 and W2[20] for OUT1.
22
FRACTIONAL-N RF/INTEGER-N IF DUAL PLL
S1M8836/37
foLD Control
Control Words
Control bits
Acronym
foLD
W3[21:18]
foLD
LOW (0)
HIGH (1)
select LDs monitoring mode of
internal counters.
Comments
Lock Detector
(LD), Test mode
foLD[3]
foLD[2]
foLD[1]
foLD[0]
foLD Output State
0
0
0
0
Disabled(default LOW)
0
0
0
1
RF and IF Analog Lock Detect
0
0
1
0
Reserved Test Mode
0
0
1
1
Reserved Test Mode
X
1
0
0
Reserved Test Mode
X
1
0
1
IF R Counter Output
X
1
1
0
IF N Counter Output
X
1
1
1
RF R Counter Output
1
0
0
0
RF N Counter Output
1
0
0
1
Reserved Test Mode
1
0
1
0
Reserved Test Mode
1
0
1
1
Reserved Test Mode
 When the PLL is locked and the analog lock detect mode is selected, the foLD output is HIGH, with narrow
pulses LOW.
Lock Detector(LD)
There is analog mode for S1M8836/37. The foLD bits, W3[21:18], are used to select the lock detection mode and
to output the selected lock signal through the foLD pin.
The foLD output becomes HIGH with narrow pulsed LOW while both RF and IF PLLs are locked and thereby the
output should be low-pass filtered for a DC locked voltage HIGH.
23
S1M8836/37
FRACTIONAL-N RF/INTEGER-N IF DUAL PLL
PULSE SWALLOW FUNCTION
The RF VCO′ frequency fVOC becomes NINT + NFRAC times the comparison frequency(fOSC/R) where
NINT is the integer divide ratio and NFRAC is the fractional component;
fVCO = (NINT + NFRAC) × fOSC/R = N × fOSC/R
where NINT = P × B + A
RF PLL: NFRAC = F/62976, -31488 ≤ F ≤ 31488, and R = 1, 2, 3 (typically 2)
IF PLL: NFRAC = 0, B > A and 3 ≤ R ≤ 32767
f VCO: External VCO output frequency
f OSC: External reference frequency(From external oscillator)
R: Preset divide ratio of programmable R counter (RF: 1, 2, 3(typically 2), IF: 3 to 32767);
P: Preset modulus of quadruple modulus prescaler (S1M8836 RF:P=8, S1M8837 RF:P=16, IF:P=8)
B: Preset value of main counter (S1M8836/37 RF: 3 to 127, IF: 3 to 4095)
A: Preset value of swallow counter division ratio
(S1M8836 RF: 0 ≤ A ≤ 7, S1M8837 RF: 0 ≤ A ≤ 15. IF: 0 ≤ A ≤ 7, A<B)
NFRAC: Fractional component of Pulse-swallowed division ratio N (for IF: NFRAC = 0)
F: Preset value of fractional register(-31488 ≤ F ≤ 31488 ); For a negative integer, F should be inputted as its 2's
complementary binary code.
For examples in S1M8836 fractional-N mode (fOSC=19.68MHz, R=2, P=8)
1) for fvco = 955.02MHz; N = 97.05487805, B=12, A=1, F=3456 (= 0 0000 1101 1000 0000)
2) for fvco = 955.03MHz; N = 97.05589431, B=12, A=1, F=3520
3) for fvco = 956.25MHz; N = 97.17987805, B=12, A=1, F=11328
4) for fvco = 979.35MHz; N = 99.52743902, B=12, A=4, F=-29760
For examples in S1M8837 fractional-N mode (fosc=19.68MHz, R=2, P=16)
1) for fvco = 1620.87MHz(CH25) ; N = 164.722561, B=10, A=5, F=-17472 (= 1 1011 1011 1100 0000)
2) for fvco = 1620.88MHz
; N = 164.7235772, B=10, A=5, F=-17408
3) for fvco = 1622.12MHz(CH50) ; N = 164.8495935, B=10, A=5, F=-9472
4) for fvco = 1632.12MHz(CH250) ; N = 165.8658537, B=10, A=6, F=-8448
5) for fvco = 1648.37MHz(CH575) ; N = 167.5172764, B=10, A=8, F=-30400
24
FRACTIONAL-N RF/INTEGER-N IF DUAL PLL
S1M8836/37
Serial Data Input Timing
MSB
DATA
LSB
DATA[21]
DATA[20]
DATA[10]
DATA[9]
CTL[1]
CTL[0]
CLOCK
tDH
tDS
tLEW
tCWH
LE
tDH
tCLE
OR
LE
Phase Detector and Charge Pump Characteristics
Phase difference detection Range : -2π to +2π
When the positive-slope polarity of PFD is selected, W2[17]=HIGH or W3[13]=HIGH;
fr
fp
LD
CPo
fr > fp
fr = fp
fr < fp
fr < fp
fr < fp
25
S1M8836/37
FRACTIONAL-N RF/INTEGER-N IF DUAL PLL
SIMPLIFIED SCHEMATIC DIAGRAM FOR RF SENSITIVITY TEST
2.7V - 4.0V
RF
Signal
Generator
50Ω
Microstrip 100pF
10dB ATTN
VDD
fin
VP
fin
51Ω
100pF
OSCin
foLD
100pF
LE
DATA
PC Parallel
Port
12kΩ
39kΩ
 Sensitivity limit is determined when the error of the divided RF output (foLD) becomes 10Hz.
 f VCO = 1.0GHz, N = 100, P = 8, R = 2 in S1M8836 Integer-N test mode
f VCO = 2.1GHz, N = 210, P = 16, R = 2 in S1M8837 Integer-N test mode Typical Application Example
26
2.2µF
S1M8836/37
CLOCK
Frequency
Counter
2.2µF
100pF
FRACTIONAL-N RF/INTEGER-N IF DUAL PLL
S1M8836/37
TYPICAL APPLICATION CIRCUIT
VDD
100pF 0.01µF
VP
22Ω
R3
VCO
0.1µF
100pF 0.01µF
10pF
C3
RF Out
C2
R1
VDD
C1
Reference
Input 1000pF
100pF 0.01µF
10pF
51Ω
100pF
22Ω
Rin
9
OSCin
foLD
8
7
VDDRFa GNDRF
6
5
4
3
2
1
fin RF
fin RF
DGND
CPORF
VPRF
VDDRF
0.1µF
10 foLD
OUT0 24
11 RF_EN
OUT1 23
12 IF_EN
VDDIF 22
VDD
CLCOK
DATA
LE
GNDIF
finIF
fin IF
DGND
CPOIF
VPIF
13
14
15
16
17
18
19
20
21
From
Controller
22Ω
VDD
Rin
1000pF
0.1µF
100pF
0.01µF
56pF
IF Out
56pF
VP
<RF VCO Module : ALPS Part No>
. CDMA : UCVA4X103A
. K-PCS : UCVW4X102A
. US-PCS : UCVA3X120A
VCO
R13
100pF
C13
C12
0.01µF
R11
C11
 The role of Rin : Rin makes a large portion of VCO output power go to the load rather than the PLL. The value
of Rin depends on the VCO power level
27
FRACTIONAL-N RF/INTEGER-N IF DUAL PLL
S1M8836/37
PCB LAYOUT GUIDE
In doing PCB layouts for S1M8836/37, we recommend that you apply the following design guide to your
handsets, thus improving the phase noise and reference spurious performances of the phones.
1. The S1M8836/37 has external four power supply pins to supply on-chip bias, each for analog and digital
blocks of RF and IF PLLs. Basically in doing PCB layout, it is important that power supply lines should be
separated from one another and thus coupling noises through the voltage supply lines can be minimized. If
you have some troubles with the direction to separate, you can choose the following recommendations for
your convenience;
•
Tying analog power lines, VDDRF and VDDIF, is possible.
•
Tying digital power lines, VP1 and VP2, is possible.
•
A point connecting the analog and digital power lines should be near to battery line as close as possible.
It minimizes coupling noise effects from a digital switching noise into analog blocks. We also
recommend that a passive RC low pass filter(R(22Ω),C(100nF)) be utilized for suppressing high
frequency noise on the analog power supply line and reducing any digital noise couplings.
2. VCO power lines should be well separated from those of PLL because VCO is generally a very sensitive
device from power line noises and PLL is a digital noise generator.
3. For more improvement of reference spurious performance, it is recommended that the LPF ground be tied to
the PLL ground, not the VCO ground.
28
FRACTIONAL-N RF/INTEGER-N IF DUAL PLL
S1M8836/37
PACKAGE DIMENSIONS
1.00MAX
0.27 + 0.05
0.70 + 0.05
4.50 + 0.10
#1 INDEX AREA
B
3.50 + 0.10
C
A
(0.05)
(0.05)
0.08
C
4X0.50 + 0.10
#24
#1
2X4.00
#1 ID MARK
2X
0.10
20X0.50
C
24X0.30 + 0.05
2X1.00
2X
0.10
C
0.10 M
C B
C S
29