DEM-DSP102/202 Evaluation Fixture ® FEATURES DESCRIPTION ● DUAL ANALOG INPUTS WITH The DEM-DSP102/202 is an evaluation fixture for Burr-Brown’s DSP101/102 and DSP201/202 series of DSP processor compatible analog interface components. The DEM-DSP102/202 incorporates digital DSP interfaces, a selectable sample rate generator, a bit clock generator, and prototyping area to install analog signal conditioning components so that the board can be used as a complete analog I/O system for a DSP design prototype. 18-BIT, 200kHz ANALOG-TO-DIGITAL CONVERTERS ● DUAL ANALOG OUTPUTS WITH 18-BIT, 500kHz DIGITAL-TO-ANALOG CONVERTERS ● SELECTABLE SAMPLE RATE GENERATOR ● PROTOTYPE AREA FOR USER The DEM-DSP102/202 facilitates evaluating the flexibility of the DSP101/102 ADCs and DSP201/202 DACs, including the cascade modes and synch formats for various DSP ICs. The board is shipped with one DSP102 and one DSP202, but it can also be used to evaluate the single channel DSP101 and DSP201. INSTALLED SIGNAL CONDITIONING ● REMOVABLE 20kHz 6 POLE LOWPASS FILTERS APPLICATIONS For more detailed information about the parts, please check the data sheets for the DSP101/102 and the DSP201/202. ● EVALUATE DSP101/102 AND DSP201/202 PERFORMANCE ● BREADBOARD COMPLETE ANALOG I/O SYSTEM ● TEST DSP SOFTWARE ROUTINES ● REDUCE SYSTEM BOARD LAYOUT TIME . International Airport Industrial Park • Mailing Address: PO Box 11400 Tel: (602) 746-1111 • Twx: 910-952-1111 • Cable: BBRCORP • © 1991 Burr-Brown Corporation • Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd. • Tucson, AZ 85706 Telex: 066-6491 • FAX: (602) 889-1510 • Immediate Product Info: (800) 548-6132 LI-408A Printed in U.S.A. June, 1992 CONTENTS Basic Operation ............................................................................................................................................................. 2 Factory Setting .............................................................................................................................................................. 3 DSP102/202 .................................................................................................................................................................. 4, 5 Connectors .................................................................................................................................................................... 6 - 8 Headers .......................................................................................................................................................................... 9 - 12 Programmable Clock Generator, Potentiometers and Reset Button ............................................................................. 12, 13 Breadboard Area ........................................................................................................................................................... 15 Filter Module ................................................................................................................................................................. 16, 17 Board Layers ................................................................................................................................................................. 18 - 21 Parts List ....................................................................................................................................................................... 22, 23 BASIC OPERATION No DSP processor is required to check the basic operation of the DSP102 and DSP202. To simply verify the operation of the DEM-DSP102/202, the digital output of the ADC can be connected to the digital input of the DAC in a loopback fashion. In this condition, the analog signal that is connected to the channel A input will be digitized by the ADC, transmitted to the DAC, converted to an analog signal by the DAC and output on channel A. Likewise, what is input on the channel B input will be output on the channel B output. 8) Set HDR12 to be SOUT B 9) Set the internal convert command generator for a frequency of 99kHz. Using the standard 12.288MHz oscillator, set switch SW2 as follows: SW2 128 — 64 — 32 — 16 — 8 — 4 — 2 — 1 — To achieve this loopback: 1) Remove CASC jumper from both the DSP102 and DSP202 to enable Cascade mode (Headers HDR9 and HDR10). 2) Set the SSF jumpers on the DSP102 and DSP202 to match each other (HDR9 and HDR10). 4) Install the /ENABLE jumper for the DSP202 (HDR10). 5) Remove DSP202 SWL jumper (HDR10). 6) Set HDR13 jumper to INT. SIN A With these connections made and power applied, analog signals applied to the input connectors will be reconstructed on the respective output connectors. SIN B 1 2 3 ® DEM-DSP102/202 off off off on on on on off 10) Connect pin 1 of connector P1 to pin 1 of connector P2, and connect pin 2 of P1 to pin 2 of the P2. This will connect the differential data output lines to the differential data input lines. Both P1 and P2 clock pins and load lines are outputs from the board. Therefore, do not connect the clock and load lines from one serial port connector to another serial port connector on the DEMDSP102/202. For this test, only the two lines described can be connected together. 3) Enable the internal convert command by installing the INT CC jumpers for the ADC and DAC (HDR9 and HDR10). 7) Set HDR11 to be SOUT A 2 J2 J1 J6 J5 VIN A VIN B VOUT B VOUT A 21 21 12 HDR5A HDR5B 12 HDR8A HDR8B Breadboard Area (0.1" Center) 1 R5 RV5 OSB OSC HDR9 R12 R11 R18 C10 C11 DSP102 C16 SSF SWL /ENABLE CASC INT CC EXT CC DSP CC TP1 X1 C15 RESET SW1 + 1 2 3 SSF CASC COM CC INT CC EXT CC DSP CC ( ) + C28 J4 EXT DAC/COM CC HDR13 U9 HDR11 + ( ) ( ) P1 + U5 DSP1 Input 1 + U7 + C23 + C27 R19 R20 + DSP2 Input 8 1 + C25 U8 Off Off Off On On On On Off + C24 128 64 32 16 8 4 2 1 Programmable Clock Generator U3 C21 U11 RN1 SW2 1 ( ) HDR12 U4 RV4 OSA +C18 TP2 U10 INT EXT ( ) 1 2 DSP101/102/201/202 Evaluation Fixture DSP1 Output C20 8 1 RV3 MSBA DSP202 C26 U12 P5 R7 1 HDR2 2 R8 J7 EXT CLK ® –5V GND +5V +15V GND –15V U2 + + DAC FUNC ADC FUNC J3 EXT ADC CC ( ) R6 MSBB RV2 1 HDR1 OSB RV1 2 10 ( ) RV6 Digital I/O MSBB C19 8 P2 U6 + ( ) + + HDR4 1 2 ( ) C3 C9 C8 PIN 1 + ( ) ( ) + U1 11 ( ) C2 C7 C6 + HDR14 C17 R3 R4 12 HDR10 RN2 OSA RV8 20 R9 + C1 ( ) ( )( ) HDR3 MSBA RV7 1 2 ( ) R10 ( ) PIN 1 R2 R1 HDR7B 21 ( )( ) 12 –5V GND +5V +5V GND –5V 21 +5V GND –5V HDR7A HDR6B –5V GND +5V HDR6A DSP2 Output C22 8 1 P3 P4 FIGURE 1. Factory Setting. FACTORY SETTING XCLK Frequency: 6.144MHz Conversion Rate: 99.1kHz Internal Convert Command: DSP102: SSF = 0, CASC = 0 DSP202: SSF = 0, SSL = 0, /ENABLE = 0, CASC = 0 Inputs and outputs go straight to the DSP102/202 (no analog filtering installed). DEM-DSP102/202 tested using Burr-Brown ZPB34 DSP boards in this configuration before shipping. ® 3 DEM-DSP102/202 VIN B J1 OPTIONAL 3 1 VIN VOUT 2 GND 1 2 1 2 HDR5/B 4 +V 5 GND 6 –V +5 –5 C3 220pF R9 154Ω HDR6/B MOD1 VIN A J2 2 1 2 1 OPTIONAL 3 1 VIN VOUT 2 GND HDR5/A HDR6/A C2 220pF R10 154Ω 4 +V 5 GND 6 –V +5 –5 MOD2 OSA MSBA + RV8 20kΩ C4 10µF R2 47.5kΩ R1 47.5kΩ MSBB RV7 20kΩ U1 DSP102 1 2 HDR3 –5 C7 +5 0.1µF C6 0.1µF +5 HDR15 3 2 1 R13 1MΩ 1 2 3 4 5 6 7 8 9 10 11 12 13 14 VPOTA VINA MSBA VOSA VA– VA+ DGND DGND VD+ CLKIN CLKOUT SSF OSC1 OSC2 AGND REF VPOTB VINB MSBB VOSB CASC /CONV SOUTA TAGB TAGA SOUTB XCLK SYNC 28 27 26 25 24 23 22 21 20 19 18 17 16 15 C5 10µF C1 0.1µF R3 47.5kΩ RV6 20kΩ C9 0.1µF C8 0.1µF 1 2 HDR4 SOUTA TAGB TAGA SOUTB XCLK SYNCH-X OSC XCLK XI 12.288MHz C11 22pF C10 22pF BUS:1 ADSP CC EXT ADC CC J3 SSF CASC COM CC INT CC EXT CC DSP CC HDR9 ADC FUNC R12 10kΩ TP1 R11 10kΩ +5 INT CC COM CC FIGURE 2. DSP102 Circuit. ® DEM-DSP102/202 4 OSB R4 47.5kΩ RV5 20kΩ VOUT A J5 OPTIONAL 1 3 VOUT VIN 2 GND 1 2 HDR8/B 1 2 HDR7/B +5 –5 4 +V 5 GND 6 –V MOD3 VOUT B J6 2 1 2 1 OPTIONAL 1 3 VOUT VIN 2 GND HDR8/A +5 –5 HDR7/A 4 +V 5 GND 6 –V MOD4 OSB +5 MSBB RV1 100kΩ –5 R5 3.32kΩ MSBA RV2 100kΩ –5 R6 3.32kΩ SW1 Reset Reset U2 DSP202 1 –5 2 2 1 3 4 HDR1 5 6 +5 7 8 9 10 SYNCH-R 11 12 XCLK 13 SINA 14 SINB VA– MSBB VOSB AGNDB VOUTB VD+ VD+ /RESET SSF SWL SYNC XCLK SINA SINB AGND DGND VA+ VPOT MSBA VOSA AGNDA VOUTA VD– DGND DGND /ENABLE CASC /CONV 28 27 26 25 24 23 22 21 20 19 18 17 16 15 OSA +5 RV3 100kΩ RV4 100kΩ R7 –5 3.32kΩ R8 –5 3.32kΩ +5 2 1 HDR2 –5 INT CC EXT DAC/COM CC J4 DAC FUNC SSF SWL /ENABLE CASC INT CC EXT CC DSP CC 2 1 +5 3 TP2 4 HDR10 RN2 10kΩ 5 6 COM CC DDSP CC BUS:1 FIGURE 3. DSP202 Circuit. ® 5 DEM-DSP102/202 J2 J1 J6 J5 VIN A VIN B VOUT B VOUT A 21 12 21 HDR5A HDR5B 12 HDR8A HDR8B Breadboard Area (0.1" Center) 1 R5 RV5 OSB OSC HDR9 R12 R11 R18 C10 C11 DSP102 C16 SSF SWL /ENABLE CASC INT CC EXT CC DSP CC TP1 X1 C15 RESET SW1 + 1 2 3 SSF CASC COM CC INT CC EXT CC DSP CC ( ) + C28 J4 EXT DAC/COM CC U12 DSP1 Out 1 SOUTA 2 SOUTB + + ( ) ( ) U5 DSP1 Input 1 P1 + U7 + C23 + C27 HDR13 U9 DSP1 In SINA SINB 1 2 3 R19 R20 DSP2 Input 8 1 U11 + C25 U8 + SW2 C24 Programmable Clock Generator + U3 C21 RN1 1 HDR11 HDR12 U4 RV4 OSA +C18 TP2 U10 INT EXT ( ) 1 2 DSP101/102/201/202 Evaluation Fixture DSP1 Output C20 8 1 RV3 MSBA DSP202 C26 ( ) P5 R7 1 HDR2 2 R8 J7 EXT CLK ® –5V GND +5V +15V GND –15V U2 + + DAC FUNC ADC FUNC J3 EXT ADC CC ( ) R6 MSBB RV2 1 HDR1 OSB RV1 2 10 ( ) RV6 Digital I/O MSBB C19 8 U6 DSP2 Output C22 8 1 P3 P2 + ( ) + + HDR4 1 2 ( ) C3 C9 C8 PIN 1 + ( ) ( ) + U1 11 ( ) C2 C7 C6 + HDR14 C17 R3 R4 12 HDR10 RN2 OSA RV8 20 R9 + C1 ( ) ( )( ) MSBA RV7 HDR3 1 2 ( ) R10 ( ) PIN 1 R2 R1 HDR7B 21 ( )( ) 12 –5V GND +5V HDR7A +5V GND –5V 21 +5V GND –5V HDR6B –5V GND +5V HDR6A P4 FIGURE 4. Connectors. POWER CONNECTOR (P5) The power connector on the DEM-DSP102/202 board is as follows: Top View Maximum power requirements are: 400mA on +5V and 100mA on –5V. –5V GND +5V +15V GND –15V The DEM-DSP102/202 comes with the female connector to allow simple use with various power supplies. A linear supply is the best choice for noise. This board does not use ±15V. (This is a standard connector used on various Burr-Brown demo boards.) ® DEM-DSP102/202 6 CONNECTORS Input to DSP102 channel B. ±2.75V input range. J1 VIN B J2 VIN A J3 EXT ADC CC External ADC convert command input. A falling edge on this TTL input begins an ADC conversion. The jumper EXT CC on the ADC FUNC header must be installed to use an external convert command. J4 EXT DAC/COM CC External DAC/Common Convert Command. A falling-edge on this TTL input begins a DAC conversion. The jumper EXT CC on the DAC FUNC header must be installed when using this input. This convert command may be jumpered to the ADC for simultaneous conversion by installing COM CC on the ADC FUNC header. J5 VOUTB Input to DSP102 channel A. ±2.75 V input range. Also the input for testing a DSP101. Output from DSP202 channel B. ±3.0V output range. Output from DSP202 channel A. ±3.0V output range. Also the output for testing a DSP201. J6 VOUTA J7 EXT CLK P1 DSP1 OUTPUT P2 DSP1 INPUT Differential I/O driver to the DSP202 DAC. P3 DSP2 INPUT Differential input driver to the DSP202 DAC SINB. Install SINB jumper at HDR11 when using this connector. Not used when testing the DSP201. P4 DSP2 OUTPUT Differential output driver from the DSP102 ADC SOUTB. Not used when testing the DSP101. P5 POWER INPUT ±5V only is required for normal operation. External clock input. A TTL input that can drive the programmable clock and bit-transfer XCLK generators. HD13 should be jumpered in the EXT position when using EXT CLK. Differential output from the DSP102. Header HD12 selects whether SOUTA or SOUTB data is sent to the DSP. These connectors are compatible with the Burr-Brown ZPB34 DSP processor boards. SERIAL INPUT CONNECTOR PINOUT SERIAL OUTPUT CONNECTOR PINOUT The pinouts for P2 and P3 are given below: The pinouts for P1 and P4 are given below: SIGNAL DESCRIPTION PINS ON P2 AND P3 SIGNAL DESCRIPTION PINS ON P1 AND P4 DI+ DI– Data Input 1 2 DO+ DO– Data Output 1 2 CK+ CK– Bit Clock (Output from board) 3 4 OCK+ OCK– Bit Clock (Output from board) 3 4 ILD+ ILD– Synch output from board 5 6 OLD+ OLD– Synch output from board 5 6 GND Ground 15 GND Ground 15 NC No Connection 7-14 NC No Connection 7-14 NC GND NC OLD– 8 NC OCK– OLD+ NC 9 NC 9 NC NC DO– DO+ DI+ NC DI– ICK+ 15 OCK+ 1 1 NC ICK– NC ILD+ NC ILD– NC NC NC GND NC 8 DSP1 Input P2 (Pin Contacts) NC DSP1 Output P1 (Socket Contacts) 15 NC = No Internal Connections NC NC DI– DI+ 1 ICK+ NC ICK– ILD– ILD+ NC 15 NC 15 NC NC NC 8 GND NC NC NC OLD– OLD+ NC NC OCK– OCK+ 8 GND 9 NC NC DO– DO+ 1 DSP2 Output P4 (Socket Contacts) NC DSP2 Input P3 (Pin Contacts) 9 FIGURE 5. I/O Connectors Viewed From Connector Side of the Board. ® 7 DEM-DSP102/202 +5 DSP1 OUT SOUTA SOUTB XCLK 75ALS194 4 EN 12 EN 1 2 1 HDR12 7 SOUTA SOUTB 9 SYNCH-X 15 +5 SYNCH-R 1 XCLK HDR12 7 9 15 HDR11 3 2 1 SINA SINA 3 BUS:1 5 SINB DSP1 IN +5 11 SOUT B 1 XCLK 7 SYNCH-X 9 XCLK IND INA INB INC IND OUTA OUTB OUTC OUTD 75ALS194 4 EN 12 EN 15 XCLK INC 75ALS195 4 OE 12 OE 13 SINB INB 75ALS194 4 EN 12 EN SYNCH-R +5 INA INA INB INC IND XCLK TAGA TAGB SOUTA SOUTB SYNCH-X ADSP CC DDSP CC SYNCH-R SINB SINA RESET 1 2 3 4 5 6 7 8 9 10 U4 SOUT A/B from DSP102 to DSP SIO Input Port P1 +OUTA –OUTA +OUTB –OUTB +OUTC –OUTC +OUTD –OUTD 2 3 6 5 10 11 14 13 1 2 3 4 5 6 15 U5 +OUTA –OUTA +OUTB –OUTB +OUTC –OUTC +OUTD –OUTD SIN A/B to DSP202 from DSP SIO Output Port P2 2 3 6 5 10 11 14 13 5 6 3 4 1 2 15 U3 R19 100Ω +INA –INA +INB –INB +INC –INC +IND –IND 2 1 14 15 6 7 10 9 U6 +OUTA –OUTA +OUTB –OUTB +OUTC –OUTC +OUTD –OUTD P3 3 4 5 6 1 2 15 R20 100Ω 2 3 6 5 10 11 14 13 Digital I/O FIGURE 6. These Connectors (P1 through P4) Will Interface Directly to Burr-Brown ZPB34 DSP Boards. 8 OCK+ OCK– OLD+ OLD– DO+ DO– GND SOUT B from DSP102 to DSP SIO Input Port P4 HDR14 DEM-DSP102/202 OLD+ OLD– OCK+ OCK– DO+ DO– GND SIN A/B to DSP202 from DSP SIO Output Port 20 19 18 17 16 15 14 13 12 11 ® DI+ DI– ICK+ ICK– ILD+ ILD– GND 1 2 3 4 5 6 15 DI+ DI– ICK+ ICK– ILD+ ILD– GND J2 J1 J6 J5 VIN A VIN B VOUT B VOUT A 21 12 21 HDR5A HDR5B 12 HDR8A HDR8B Breadboard Area (0.1" Center) 1 R5 RV5 OSB OSC HDR9 R12 R11 R18 C10 C11 DSP102 C16 SSF SWL /ENABLE CASC INT CC EXT CC DSP CC TP1 X1 C15 RESET SW1 + 1 2 3 SSF CASC COM CC INT CC EXT CC DSP CC ( ) + C28 J4 EXT DAC/COM CC DSP1 Out 1 SOUTA 2 SOUTB HDR13 + ( ) U5 ( ) P1 U9 DSP1 In SINA SINB 1 2 3 DSP1 Input 1 R19 R20 U7 + C23 + C27 + U3 C21 DSP2 Input 8 1 P2 RN1 U11 + C25 U8 + SW2 C24 Programmable Clock Generator ( ) + + 1 HDR11 HDR12 U4 RV4 OSA +C18 TP2 U10 INT EXT ( ) 1 2 DSP101/102/201/202 Evaluation Fixture DSP1 Output C20 8 1 RV3 MSBA DSP202 C26 U12 P5 R7 1 HDR2 2 R8 J7 EXT CLK ® –5V GND +5V +15V GND –15V U2 + + DAC FUNC ADC FUNC J3 EXT ADC CC ( ) R6 MSBB RV2 1 HDR1 OSB RV1 2 10 ( ) RV6 Digital I/O MSBB C19 8 U6 + ( ) + + HDR4 1 2 ( ) C3 C9 C8 PIN 1 + ( ) ( ) + U1 11 ( ) C2 C7 C6 + HDR14 C17 R3 R4 12 HDR10 RN2 OSA RV8 20 R9 + C1 ( ) ( )( ) MSBA RV7 HDR3 1 2 ( ) R10 ( ) PIN 1 R2 R1 HDR7B 21 ( )( ) 12 –5V GND +5V HDR7A +5V GND –5V 21 +5V GND –5V HDR6B –5V GND +5V HDR6A DSP2 Output C22 8 1 P3 P4 FIGURE 7. Headers. HEADERS HDR1 Select OSB (DSP202 offset adjust, channel B) by installing position 1. Select MSBB (DSP202 MSB adjust, channel B) by installing position 2. HDR2 Select MSBA (DSP202 MSB adjust, channnel A or DSP201 MSB adjust) by installing position 1. Select OSA (DPS202 offset adjust, channel A or DSP201 MSB adjust) by installing position 2. HDR3 Select MSBA (DSP102 MSB adjust, channel A or DSP101 MSB adjust) by installing position 1. Select OSA (DSP102 offset adjust, channel A or DSP101 offset adjust) by installing position 2. HDR4 Select MSBB (DSP102 MSB adjust, channel B) by installing position 1. Select OSB (DSP102 offset adjust, channel B) by installing position 2. HDR5/A* Input is connected directly from J2 to VINA of DSP102 by installing position 2 on both headers. HDR6/A* Also directly drives DSP101 input. ® 9 DEM-DSP102/202 HDR5/B* Input is connected directly from J1 to VINB of DSP102 by installing position 2 on both headers. HDR6/B* HDR7/A* VOUT B from the DSP202 is connected directly to J6 by selecting position 2. HDR8/A* HDR7/B* VOUT A from the DSP202 is connected directly to J5 by selecting position 2. Also provides the direct HDR8/B* output from the DSP201. * When using with filter module, install both jumpers in position 1. HDR9 (DSP102) Located beside the DSP102 socket. Unless otherwise noted, an open jumper creates a high input and an installed jumper creates a low. A row of jumpers which configure several signals are as follows: SSF Controls the SSF pin (pin 12). Selects synch format. Logic “0” when jumper is installed. Logic “1” when not installed. CASC Controls the DSP102 CASC pin (pin 22). In the cascade mode when not installed. Outputs data from both DSP102 channels simultaneously when installed. In Cascade mode the 32-bit data stream is transmitted from the SOUTA pin. Install only one of the following four jumpers at any one time! COM CC Common Convert Command. Install when using EXT DAC/COM CC BNC input. INT CC Internal Convert Command. Install to use the on-board programmable clock generator. (PROGRAMMABLE CLOCK GENERATOR, see page 11). Conversion frequency is deter mined by the dip switches and the oscillator frequency. EXT CC External Convert Command. Install to use with EXT ADC CC, input J3. DSP CC External Convert Command. Install to use an external convert command driven into the Digital I/O HDR14 pin 6. Labeled on schematic as “ADSPCC”. HDR10 (DSP202) Located beside the DSP202 socket. Unless otherwise noted, an open jumper creates a high input and an installed jumper creates a low. A row of jumpers which configure several signals are as follows: SSF Controls the SSF pin (pin 12). Selects synch format. Logic “0” when jumper is installed. Logic “1” when not installed. SWL Controls the SWL pin (pin 10). Selects word length. /ENABLE Must be driven low for the DAC to update. Jumper must be installed for operation. CASC Controls the DSP202 CASC pin (pin 16). In the cascade mode when not installed. Clocks in data to both DSP202 channels simultaneously when installed. When using the differential I/O drivers install a jumper on HDR11 at position 1 to use the cascade mode. This will jumper the SINA and SINB from the same input. Either the P1 or P4 connector may be used. When the jumper is installed, data clocked into both input pins on the DSP202 (SINA pin and SINB pin) simultaneously. This jumper has no effect when testing a DSP201. Install only one of the following three jumpers at any one time! INT CC Internal Convert Command. Install this jumper when using the convert command from the on board programmable clock generator. EXT CC External Convert Command. Install to use with EXT DAC/COM CC. DSP CC External Convert Command. Install to use an external convert command driven into the Digital I/O HDR14 pin 7. Labled on schematic as “DDSPCC”. ® DEM-DSP102/202 10 SIN A HDR 11 SIN B 1 2 SIN A SIN B 1 2 SIN B 2 SIN B 1 2 Input to both SINA + SINB comes from P2 (Used in DSP202 cacade mode) 3 Install one and only one jumper. SOUT A SOUT B SOUT A SOUT B HDR13 Input to SINA comes from P2 and SINB from P3 3 SIN A HDR 12 Input to SINB comes from P3 3 SIN A 1 Input to SINA comes from P2 3 Output of SOUTA goes to P1 and SOUTB to P4 Output of SOUTB goes to P1 and P4 Part of Programmable Clock Generator. Install one and only one jumper. Install 1 (INT) for direct use of on board clock generator. Install 2 (EXT) for external clock (J7). ® 11 DEM-DSP102/202 HDR14 This header is a TTL I/O. The pinout is as follows: PINS INPUT OR OUTPUT TAGA Input Channel A User Tag In. Data clocked into this pin is appended to the conversion results of SOUTA. User Tag In for DSP101. TAGB Input Channel B User Tag In. Data clocked into this pin is appended to the conversion results of SOUTB. SOUTA Output SOUTB Output SYNCH-X Output ADSPCC DDSPCC SEE ALSO DESCRIPTION HDR9 Serial output of DSP102 channel A. Serial data for both DSP102 channels in cascade mode. Serial output for DSP101. Serial output of DSP102 channel B. HDR9 Data valid for DSP102. Input HDR9 ADC DSP Convert Command Input HDR10 DAC DSP Convert Command SYNCH-R Output HDR10 Data valid for DSP202. SINB Input* HDR11 Serial input for DSP202 channel B. SINA Input* HDR11 Serial input for DSP202 channel A. Serial input for DSP201. RESET Input Reset input. (Do not use reset button when using this pin). Hold high for normal operation. Bring low to drive DSP201 or DSP202 outputs to 0V. GND Ground, signal return path. XCLK Output HDR13 Data transfer clock to which serial input and output data is synchronized. * Remove all jumpers on HDR11 in order to use these pins as inputs. The header connects these inputs to an output of a logic device on the differential I/O lines. HDR15 Three position jumper by the DSP102 socket which determines the source of the OSC1 input. Two options are provided: 1) Install jumper 1 and XCLK signal is connected to OSC1 (pin13) of the DSP102 or DSP101. 2) Install jumpers 2 and 3 and the crystal oscillator is connected to OSC1 (jumper 3) and OSC2 (jumper 2). Jumper 1 must be removed in this case. PROGRAMMABLE CLOCK GENERATOR A synchronous counter divides the U12 or EXT CLK (J7) by 4 and then provides an 8-bit counter to further divide the clock to produce a conversion rate. Whether jumper 1 or 2 is installed on HDR13 determines whether the oscillator U12 or the clock input on J7 is used as the Master Clock for the clock generator. Where N is the value set in switch SW2. i.e. 128 (ON), 32 (ON), 16 (ON) 128 + 32 + 16 = 176 Convert Rate = 12.288MHz 12.288MHz = = 17.356kHz 4 (176 + 1) 708 A socketed 12.288MHz crystal is provided (U12). It is not soldered in, so that other crystal frequencies may be used. A dip switch “ON” is a logic 1. XCLK = Master Clock Frequency / 2 A dip switch “OFF” is a logic 0. An external XCLK is not an option on this board. The DEM-DSP102/202 is shipped set for divide by 124. (Thirty (30) is set in the dip switch.) This yields a conversion frequency of 99kHz. Conversion rate is selected by the dip switch using the formula: The conversion rate MUST be at least 24 times slower than the conversion clock on the DSP102 (72 times slower than XCLK, which is used to drive OSC1 on the DSP102). See DSP101/102 data sheet. Convert Rate = Master Clock / (4 X (N + 1)) ® DEM-DSP102/202 12 J2 J1 J6 J5 VIN A VIN B VOUT B VOUT A 21 12 21 HDR5A HDR5B 12 HDR8A HDR8B Breadboard Area (0.1" Center) 1 Digital I/O DSP102 SSF CASC COM CC INT CC EXT CC DSP CC ( ) + C28 J4 EXT DAC/COM CC DSP1 Out 1 SOUTA 2 SOUTB HDR12 + ( ) U5 ( ) P1 U9 DSP1 In SINA SINB 1 2 3 HDR11 + DSP1 Input 1 ( ) + U7 + C23 + C27 R19 R20 DSP2 Input 8 1 U11 + C25 U8 + SW2 C24 Programmable Clock Generator + U3 C21 RN1 1 HDR13 DSP101/102/201/202 Evaluation Fixture U4 RV4 OSA +C18 TP2 U10 INT EXT ( ) 1 2 ® DSP1 Output C20 8 1 RV3 MSBA J7 EXT CLK ( ) P5 R8 DSP202 C26 U12 –5V GND +5V +15V GND –15V R7 HDR2 DAC FUNC ADC FUNC J3 EXT ADC CC U2 + + ( ) OSC HDR9 R12 R11 R18 X1 C16 SSF SWL /ENABLE CASC INT CC EXT CC DSP CC TP1 C10 C11 R5 C15 Reset SW1 + 1 2 3 HDR1 OSB RV1 RV6 MSBB RV5 OSB C8 R6 MSBB RV2 10 C19 8 P2 U6 + ( ) C9 R3 R4 ( ) + + HDR4 1 2 ( ) ( ) C3 PIN 1 + ( ) + + U1 11 12 HDR10 RN2 C2 C7 C6 HDR14 C17 C1 ( ) ( )( ) HDR3 MSBA RV7 1 OSA RV8 2 20 R9 + ( ) R10 ( ) PIN 1 R2 R1 HDR7B 21 ( )( ) 12 –5V GND +5V HDR7A +5V GND –5V 21 +5V GND –5V HDR6B –5V GND +5V HDR6A DSP2 Output C22 8 1 P3 P4 FIGURE 8. Programmable Clock Generator, Potentiometers and Reset Button . POTENTIOMETERS RESET BUTTON The MSB and Offset adjust pots are available for both the DSP102 and DSP202. These pots may be enabled through their associated headers. In most application adjusting offset and MSBs has no significant impact on dynamic performance. The reset button forces the output of the D/A converter to 0V, after two convert commands are received. When using Reset pin on HDR14 do not use this button! Remove all jumpers on HDR1, HDR2, HDR3, and HDR4 to observe no-trim operation. All DSP101/102 and DSP 201/ 202 data sheet specs are without external adjustment. (See section on Headers for description of HDR1 to HDR4). ® 13 DEM-DSP102/202 U10 74HCT74 4 S1 3 C1 2 D1 1 R1 +5 +5 +5 +5 5 Q1 6 /Q1 10 S2 11 C2 12 D2 13 R2 74HCT163 1 /CLR 9 /LOAD +5 8 /Q2 /16 /32 /64 /128 3 A 4 B 5 C 6 D +5 74HCT163 1 /CLR 9 /LOAD XCLK /1 /2 /4 /8 3 A 4 B 5 C 6 D SW2 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 /128 /64 /32 /16 /8 /4 /2 /1 /128 /64 /32 /16 /8 /4 /2 /1 2 3 4 5 6 7 8 9 10 1 +5 RN1 10kΩ U12 +5 14 8 1 2 CLK CLK INT EXT VCC NC OUT GND 12.2880MHz 1 7 EXT CLK J7 HDR13 INT CC FIGURE 9. Programmable Clock Generator Circuit. ® DEM-DSP102/202 +5 QA QB QC QD RCO 14 13 12 11 15 14 +5 +5 4 S1 3 C1 2 D1 1 R1 Q1 /Q1 10 S2 11 C2 12 D2 13 R2 Q2 /Q2 5 6 9 8 U8 10 ENT 7 ENP 2 CLK +5 128 64 32 16 8 4 2 1 +5 10 ENT 7 ENP 2 CLK +5 9 Q2 U9 74HCT74 U7 U11 74HCT00 +5 QA QB QC QD RCO 14 13 12 11 15 1 2 4 5 9 10 12 13 1A 2B 2A 2B 3A 3B 4A 4B & /1Y /2Y /3Y /4Y 3 6 8 11 J2 J1 J6 J5 VIN A VIN B VOUT B VOUT A 12 21 HDR5B 12 HDR8A Breadboard Area (0.1" Center) Install filter here. (Jumpers in position 1 on HDR5 and HDR6). HDR8B Install filter here. (Jumpers in position 1 on HDR7 and HDR8). Pin 1 Pin 1 Pin 1 Pin 1 HDR6B HDR7A 1 R6 MSBB RV2 1 HDR1 OSB RV1 2 10 R5 RV5 OSB RESET SW1 + OSC HDR9 C10 C11 R12 R11 R18 X1 DSP102 C16 SSF SWL /ENABLE CASC INT CC EXT CC DSP CC TP1 1 2 3 C15 SSF CASC COM CC INT CC EXT CC DSP CC ( ) + C28 J4 EXT DAC/COM CC DSP1 Out 1 SOUTA 2 SOUTB HDR13 + ( ) U5 ( ) P1 U9 DSP1 In SINA SINB 1 2 3 DSP1 Input 1 R19 R20 U7 + C23 + C27 + U3 C21 DSP2 Input 8 1 P2 RN1 U11 + C25 U8 + SW2 C24 Programmable Clock Generator ( ) + + 1 HDR11 HDR12 U4 TP2 U10 INT EXT ( ) 1 2 DSP101/102/201/202 Evaluation Fixture DSP1 Output C20 8 1 RV4 OSA +C18 DSP202 C26 U12 P5 RV3 MSBA J7 EXT CLK ® –5V GND +5V +15V GND –15V R7 1 HDR2 2 R8 DAC FUNC ADC FUNC J3 EXT ADC CC U2 + + ( ) RV6 Digital I/O MSBB ( ) + + HDR4 1 2 ( ) C3 C9 C8 PIN 1 + ( ) ( ) + U1 11 ( ) R10 ( ) C2 C7 C6 + HDR14 C17 R3 R4 12 HDR10 RN2 OSA RV8 20 R9 + C1 ( ) ( )( ) MSBA RV7 HDR3 1 2 HDR7B 21 ( )( ) 12 PIN 1 R2 R1 Filter Mod –5V GND +5V 21 +5V GND –5V –5V GND +5V HDR6A Filter Mod +5V GND –5V Filter Mod ( ) Filter Mod C19 8 U6 + ( ) 21 HDR5A DSP2 Output C22 8 1 P3 P4 FIGURE 10. Breadboard Area and How Filters Should be Installed. BREADBOARD AREA This demoboard provides a breadboard area to evaluate different circuits that will be interfaced to the DSP102 and 202. The filter modules plug into this area. (See diagram for proper orientation.) ® 15 DEM-DSP102/202 GND Filter Mod Comp Side V5+ Filter Mod Ground Plane V5- Filter Mod Power Plane Filter Mod Solder Side 1 1 2 U3 C2 R1 R2 C6 C4 R8 R6 R4 R3 R5 U1 R9 R7 U2 R10 C3 HDR1 Filter Mod Silk Screen FIGURE 11. Filter Board. FILTER MODULE PIN NO. DESCRIPTION ±10 Vpp in (±3Vpp with 5V supplies) The filter module is set for audio operation (flat to 20kHz, –3dB = 53kHz) with linear phase. VIN 1 GND 2(1) Refer to Applications Bulletin AB-026A (A low noise, low distortion design for antialiasing and anti-imaging filters) for more information on these GIC filters. (The GIC circuit used here is slightly different than that presented in the Application Bulletin. This circuit works better with ±5V supplies and offers higher out-of-band attenuation.) VOUT 3 Gain of +1V/V +VS 4 +5 to +15V (board only provides +5V) GND 5(1) –VS 6 Ground return(1) Ground return(1) –5 to –15V (board only provides –5V) NOTE: (1) These pins connected together on the filter module. Filter Module The filter module values for 100kHz cutoff are: 267Ω R5, R10 1.324kΩ C1-C6 2200pF (NPO) 1 2 3 4 5 6 3rd Order FIGURE 12. Filter Module. ® DEM-DSP102/202 6th Order –VS 762Ω R4, R9 +VS 762Ω R3, R8 GND R2, R7 Component Side GND 762Ω VOUT VALUE R1, R6 VIN REF 16 2 R10 2.74kΩ 1 R9 511Ω VIN 2 GND 3 U2A 1/2 5532 3 1 6 2 5 R8 1.5kΩ 7 1/2 5532 U1A C6 2200pF C5 2200pF R7 1.5kΩ 1 1/2 5532 U2B R6 1.5kΩ 4 C4 2200pF +VS 5 GND 6 –VS HDR1 3 VOUT 6 R4 511Ω R5 2.74kΩ 1/2 5532 U3B 1/2 5532 U3A 3 Power Pins for the 5532: +V Pin 8 –V Pin 4 1 6 2 5 R3 1.5kΩ 7 1/2 5532 U1B C3 2200pF C2 2200pF R2 1.5kΩ 7 5 R1 1.5kΩ C1 2200pF FIGURE 13. Filter Diagram. ® 17 DEM-DSP102/202 U1 R3 R4 HDR4 RV6 MSBB OSB HDR9 TP1 P5 J7 U12 EXT DAC/COM CC EXT CLK BURR-BROWN HDR13 INT 1 EXT 2 HDR11 U4 U5 75ALS194 C20 DSP1 OUTPUT 1 1 75ALS195 C21 DSP1 INPUT P2 R19 R20 1 SILK SCREEN (AA293-4SS) JOB: 1341 L2 FIGURE 14. Silk Screen. ® DEM-DSP102/202 18 +5V GND -5V U11 C23 C27 RN1 SW2 1 C25 128 64 32 16 8 4 2 1 C24 PROGRAMMABLE CLOCK GENERATOR U3 8 U6 74ALS194 C19 DSP2 INPUT P3 8 U7 C26 U8 DSP1 IN SINA SINB 1 2 3 DSP1 OUT SOUTA SOUTB HDR12 1 2 8 DSP202 U9 74HCT74 R P1 RV4 TP2 RN2 U10 C28 74ALS194 OSA R8 C18 DAC FUNC J4 EXT ADC CC MSBA 1 2 C15 HDR2 C16 HDR10 SSF SWL /ENABLE CASC INT CC EXT CC DSP CC RV3 R7 HDR1 R5 RESET SW1 RV5 J3 -5V GND +5V SPARE GND SPARE U2 C17 1 2 OSB RV1 SSF CASC COM CC INT CC EXT CC DSP CC ADC FUNC DSP102 VOUT A MSBB R12 R11 HDR15 C10 1 2 3 C11 OSC 1 2 HDR7/B RV2 R6 C13 X1 R18 2 1 HDR7/A PIN 1 HDR14 1 2 HDR8/B 1 2 74HCT00 RV8 C1 C5 C3 C9 C8 HDR8/A 2 1 74HCT163 1 2 OSA DIGITAL I/O R9 C4 C2 C7 C6 C14 C12 HDR3 MSBA VOUT B 74HCT163 1 2 HDR6/B J5 -5V GND +5V 2 1 HDR6/A PIN 1 VIN B 74HCT74 R2 R1 RV7 HDR5/B 1 2 XCLK GND GND GND GND GND GND GND GND RESET R10 HDR5/A 2 1 J6 TAGA TAGB SOUTA SOUTB SYNCH-X ADSPCC DDSPCC SYNCH-R SINB SINA -5V GND +5V VIN A J1 +5V GND -5V J2 C22 DSP2 OUTPUT P4 8 1 COMPONENT SIDE (AA293-4) FIGURE 15. Component Side. ® 19 DEM-DSP102/202 GROUND PLANE (AA293-3) FIGURE 16. Ground Plane. ® DEM-DSP102/202 20 POWER PLANE (AA293-2) FIGURE 17. Power Plane. ® 21 DEM-DSP102/202 V5V5+ ERAPS ERAPS C VER 392AA NOITAROPROC NWORB-RRUB ASU NI EDAM 202/201PSD-MED SOLDER SIDE (AA293-1) FIGURE 17. Solder Side. ® DEM-DSP102/202 22 PARTS LIST - MAIN BOARD PART NUMBER DESCRIPTION ON BOARD MANUFACTURER(1) 1 DSP102 U1 BURR-BROWN 1 DSP202 U2 BURR-BROWN 3 74ALS194 U4, U5, U6 ANY 1 74ALS195 U3 ANY 1 74HCT00 U11 ANY 2 74HCT74 U9, U10 ANY 2 74HC163 U7, U8 ANY 1 VF150A12.288000 U12 VALPEY-FISHER PART DESCRIPTION COMPONENTS Oscillator 12.288 MHz CONNECTORS AND SOCKETS 2 828-AG11D (U1/U2) AUGAT 28 Pin Socket 0.3 714-93-120-31-007 (U12) PRECI-DIP Strip Socket Carrier 7 KC-79-274-M06 J1-J7 KINGS BNC 2 4711-15-41-P1 P2, P3 TEX-TECHS DB15PR (Male) 2 4731-15-41-P1 P1, P4 TEX-TECHS DB15SR (Female) 1 207-8 SW2 1 EVQ-QS205K SW1 PANASONIC Push Button Switch 1 4610X-101-103 RN1 BOURNS RSIP10 10k 10 Pin PU 1 4606X-101-103 RN2 BOURNS RSIP6 10k 6 Pin PU 4 RJR26FW104M RV1-4 BOURNS Trimpot 100k 4 RJR26FW203M RV5-8 BOURNS Trimpot 20k 2 5063JD100R0F R19, R20 PHILIPS 100Ω 1/3W 2 5063JD154R0F R9, R10 PHILIPS 154Ω 1/3 W 4 5063JD3K320F R5, R6, R7, R8 PHILIPS 3.32k 1/3W 2 5063JD10K00F R11, R12 PHILIPS 10k 1/3W 4 5063JD47K50F R1, R2, R3, R4 PHILIPS 47.5k 1/3W 1 5063JD1M000F R18 PHILIPS 1M 1/3W 17 ECS-F1EE225K C12-C28 PANASONIC TANT 2.2µF 25V 2 ECS-F1AE106K C5, C4 PANASONIC TANT 10µF 10V 2 C315C220J2G5CA C10, C11 KEMET CERC 22pF 2 C315C221J2G5CA C2, C3 KEMET CERC 220pF 5 C320C104K5G5CA C1, C6, C7, C8, C9 KEMET CERC .1µF HDR1, 2, 3, 4, 5A, 5B SAMTEC HDR 2X2 GLD CON TIN TAIL DIPSW 8 POS RESISTORS CAPACITORS MECHANICAL HARDWARE 14 TSW-102-07-S-D 6A, 6B, 7A, 7B, 8A 8B, 12, 13 2 TSW-103-07-S-D HDR11, HDR15 SAMTEC HDR 2X3 2 TSW-108-07-S-D HDR10, 9 SAMTEC HDR 2X8 1 TSW-110-07-S-D HDR14 SAMTEC HDR 2X10 1 102203-3 P5 AMP RA 6 Pin Connector 9 312-6473-032 N/A EF JOHNSON STANDOFFS 1" 9 1/4" Screws N/A EF JOHNSON Phillips Stainless 4-40 21 N/A H&T COMP 1 N/A Shunts Power Cable ® 23 DEM-DSP102/202 PARTS LIST - FILTERS (2) PART PART NUMBER DESCRIPTION ON BOARD MANUFACTURER DESCRIPTION NE5532N U1, U2, U3 SIGNETICS Dual Low Noise Op Amp COMPONENTS 3 RESISTORS 2 5063JD511ROF R4, R9 PHILIPS 511k 1/3W 2 5063JD2K740F R5, R10 PHILIPS 2.74k 1/3W 6 5063JD1K500F R1, R2, R3, R6, R7, R8 PHILIPS 1.50k 1/3W C315C222J1G5CA C1-C6 KEMET Ceramic 2200pF HDR1 SAMTEC HDR 2X2 GLD CON TIN TAIL SAMTEC HDR 1X3 RT ANGL H&T COMP Shunt CAPACITORS 6 MECHANICAL HARDWARE 1 TSW-102-07-S-D 2 TSW-103-08-S-S 1 N/A NOTE: (1) For reference only. Equivalent parts may be substituted. (2) Four completed boards shipped with each DEM-DSP102/202 plus four empty boards. ® DEM-DSP102/202 24