ETC DS1221S

DS1221
DS1221
Nonvolatile Controller x 4 Chip
FEATURES
• Converts CMOS RAMs into nonvolatile memories
PIN ASSIGNMENT
VCCO
1
16
VCCI
• Data is automatically protected during power loss
VBAT1
2
15
VBAT2
• 2-to-4 decoder provides for up to 4 CMOS RAMs
*RST
3
14
CE
A
4
13
• Provides for redundant batteries
• Test battery condition on power-up
• Full ±10% operating range
• Unauthorized access can be prevented with optional
security feature
• 16-pin 0.3-inch DIP saves PC board space
• Optional 16-pin SOIC surface mount package
• Optional industrial temperature range of
-40°C to +85°C available
VCC0
CE0 VBAT1
1
16
VCCI
2
15
VBAT2
*RST
A
3
14
13
CE
12
CE1
CE2
CE3
*D/Q
B
5
12
CE1
*RD
6
11
CE2
*WE
7
10
CE3
GND
8
9
*D/Q
DS1221 16–Pin DIP (300 MIL)
B
*RD
4
5
6
*WE
7
11
10
GND
8
9
CE0
DS1221 16–Pin SOIC (300 MIL)
PIN DESCRIPTION
A, B
CE
CE0 - CE3
VBAT1
VBAT2
*RST
VCCI
VCCO
*RD
*WE
*D/Q
–
–
–
–
–
–
–
–
–
–
–
Address Inputs
Chip Enable Input
Chip Enable Outputs
+ Battery 1
+ Battery 2
Reset
+5V Supply
RAM Supply
Read Input
Write Input
Data Input/Output
*Used with optional security circuit only and must be
connected to ground in all other cases.
DESCRIPTION
The DS1221 Nonvolatile Controller x 4 Chip is a CMOS
circuit which solves the application problem of converting CMOS RAMs into nonvolatile memories. Incoming
power is monitored for an out-of-tolerance condition.
When such a condition is detected , the chip enable outputs are inhibited to accomplish write protection and the
battery is switched on to supply RAMs with uninterrupted power. An optional security code prevents unau-
Copyright 1995 by Dallas Semiconductor Corporation.
All Rights Reserved. For important information regarding
patents and other intellectual property rights, please refer to
Dallas Semiconductor databooks.
thorized users from obtaining access to the memory
space. The nonvolatile controller/decoder circuitry uses
a low-leakage CMOS process which affords precise
voltage detection at extremely low battery consumption.
By combining the DS1221 with up to four CMOS memories and lithium batteries, nonvolatile operation can be
achieved.
022194 1/8
DS1221
CONTROLLER /DECODER OPERATION
The DS1221 nonvolatile controller performs six circuit
functions required to decode and battery back up a bank
of up to four CMOS RAMs. First, a 2-to-4 decoder provides selection of one of four RAMs (see Figure 1). Second, a switch is provided to direct power from the battery
or VCCI supply, depending on which is greater, to the
VCCO pin. This switch has a voltage drop of less than
0.2V. The third function which the nonvolatile controller
provides is power-fail detection. The DS1221 constantly monitors the VCCI supply. When VCCI falls below 4.5
volts, a precision comparator detects the condition and
inhibits the RAM chip enables (CE0 through CE3). The
fourth function of write protection is accomplished by
holding all chip enable outputs (CE0 through CE3) to
within 0.2 volts of VCCI or battery supply. If the Chip Enable Input (CE) is low at the time power-fail detection occurs, the chip enable outputs are kept in their present
state until CE is driven high. The delay of write protection until the current memory cycle is completed prevents the corruption of data. Power failure detection occurs in the range of 4.5 to 4.25 volts. During nominal
supply conditions the chip enable outputs follow the logic of a 2-to-4 decoder. The fifth function the DS1221 performs is to check battery status to warn of potential data
loss. Each time that VCCI power is restored the battery
voltage is checked with a precision comparator. If the
connected battery voltage is less than 2 volts, the second memory cycle is inhibited. Battery status can, therefore, be determined by performing a read cycle after
power-up to any location in memory, verifying that
memory location content. A subsequent write cycle can
then be executed to the same memory location, altering
the data. If the next read cycle fails to verify the written
data, the contents of the memories are questionable.
The sixth function of the nonvolatile controller provides
for battery redundancy. In many applications, data integrity is paramount. In these applications it is often desirable to use two batteries to ensure reliability. The
DS1221 provides an internal isolation switch which provides for connection of two batteries. During battery
back-up operation the battery with the highest voltage is
selected for use. If one battery should fail, the other will
automatically take over. The switch between batteries is
transparent to the user. A battery status warning will occur if both batteries are less than 2.0 volts. If only one
battery is used, the second battery input must be
grounded. Figure 2 illustrates the connections required
for the DS1221 in a typical application.
NONVOLATILE CONTROLLER/DECODER Figure 1
INPUTS
OUTPUTS
VCCI
CE
B
A
CE0
CE1
CE2
CE3
>=4.5
H
X
X
H
H
H
H
< 4.25
X
X
X
H
H
H
H
>=4.5
L
L
L
L
H
H
H
>=4.5
L
L
H
H
L
H
H
>=4.5
L
H
L
H
H
L
H
>=4.5
L
H
H
H
H
H
L
H = High Level
L = Low Level
X = Irrelevant
022194 2/8
DS1221
TYPICAL APPLICATION Figure 2
VCCO
VCCI
A DS1221
B
CE
WE CE0
RD
D/Q CE3
RST
VBAT1
+
RAM1
CE
RAM2
CE
RAM3
RAM4
CE
CE
VBAT2
+
Battery Backup Current Drain
DS1221:
.1 µA @ 25°C
RAM-5564 x 4:
.8 µA @ 25°C
TOTAL:
.9 µA @ 25°C
SECURITY SEQUENCE Figure 3
OUTPUT LOAD Figure 4
+5 VOLTS
READ CYCLE
1.1K
WRITE ONLY
REGISTER OPEN
D.U.T.
64 WRITE CYCLES
680 OHM
50pF
NO
MATCH
YES
READ ONLY
REGISTER OPEN
64 READ CYCLES
MEMORY OPEN
YES
VCC<4.5V
OR RESET
NO
022194 3/8
DS1221
ABSOLUTE MAXIMUM RATINGS*
Voltage on any Pin Relative to Ground
Operating Temperature
Storage Temperature
Soldering Temperature
Short Circuit Output Current
-0.3V to +7.0V
0°C to 70°C
-55°C to +125°C
260°C for 10 seconds
20 mA
* This is a stress rating only and functional operation of the device at these or any other conditions above
those indicated in the operation sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability.
(0°C to 70°C)
RECOMMENDED DC OPERATING CONDITIONS
PARAMETER
SYMBOL
MIN
TYP
Supply Voltage
VCCI
4.5
5.0
Logic 1 Input
VIH
2.2
Logic 0 Input
VIL
-0.3
Battery Input
VBAT1
VBAT2
2.0
SYMBOL
Supply Current
ICCI
Supply Voltage
VCCO
Supply Current
ICCO1
Input Leakage
IIL
Output Leakage
CE0-CE3, DQ Output @ 2.4V
CE0-CE3, DQ Output @ 0.4V
UNITS
NOTES
5.5
V
1
VCC+0.3
V
1
+0.8
V
1
4.0
V
1, 2
(0°C to 70°C; VCC= 4.5 to 5.5V)
DC ELECTRICAL CHARACTERISTICS
PARAMETER
MAX
MIN
TYP
MAX
UNITS
NOTES
5
mA
3
V
1
80
mA
4, 10
-1.0
+1.0
µA
ILO
-1.0
+1.0
µA
IOH
-1.0
VCC-0.2
IOL
mA
5
4.0
mA
5
VCC Trip Point
VCCTP
4.25
4.37
4.50
V
1
PARAMETER
SYMBOL
MIN
TYP
MAX
CE0-CE3 Output
VOHL
VCC-0.2
VBAT-0.2
VBAT1 or VBAT2 Battery Current
IBAT
0.1
µA
3
ICCO2
100
µA
6, 7, 10
(0°C to 70°C; VCC< 4.25V)
Battery Backup Current
@ VCCO = VBAT - 0.5V
022194 4/8
UNITS
NOTES
V
DS1221
(tA = 25°C)
CAPACITANCE
PARAMETER
Input Capacitance
Output Capacitance
SYMBOL
MAX
UNITS
CIN
MIN
TYP
5
pF
COUT
7
pF
(0°C to 70°C; VCC= 4.5 to 5.5V)
AC ELECTRICAL CHARACTERISTICS
PARAMETER
NOTES
SYMBOL
MIN
TYP
MAX
UNITS
NOTES
CE Propagation Delay
tPD
5
10
20
ns
5
CE High to Power-Fail
tPF
0
ns
Address Setup
tAS
20
ns
9
(0°C to 70°C; VCC< 4.5V)
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS
tREC
2
5
10
ms
VCC Slew Rate 4.5 - 4.25V
tF
300
µs
VCC Slew Rate 4.25 - 3V
tFB
10
µs
VCC Slew Rate 4.25 - 4.5V
tR
0
µs
CE Pulse Width
tCE
Recovery at Power Up
1.5
µs
NOTES
7, 8
NOTES:
1. All voltages are referenced to ground.
2. Only one battery input is required.
3. Measured with VCCO and CE0 - CE3 open.
4. ICCO1 is the maximum average load which the DS1221 can supply to the memories.
5. Measured with a load as shown in Figure 4.
6. ICCO2 is the maximum average load current which the DS1221 can supply to the memories in the battery
back-up mode.
7. Chip enable outputs CE0 - CE3 can only sustain leakage current in the battery back-up mode.
8. tCE max. must be met to ensure data integrity on power loss.
9. tAS is only required to keep the decoder outputs glitch-free. While CE is low, the outputs (CE0 - CE3) will be
defined by inputs A and B with a propagation delay of tPD from an A or B input change.
10. For applications where higher currents are required, please see the DS1259 Battery Manager Chip data
sheet.
022194 5/8
DS1221
SECURITY OPTION
part of the security sequence begins by reading a 64-bit
read only register. This register consists of 64 bits also
defined by the user and programmed into the DS1221
by Dallas Semiconductor at the time of manufacture.
For each of the 64 read cycles, one bit of the user-defined read only register is driven onto the DQ line. This
phase also requires that the 64 read cycles be consecutive. The data being read from the read only register can
be used by software to determine if the DS1221 will be
permitted to be used with that particular system. After
the 64th read cycle has been executed the DS1221 is
unlocked and all subsequent memory cycles will be
passed through and will become actual memory accesses based upon address inputs. If VCC falls below
4.5 volts or the reset line is driven low, the entire security
sequence must be executed again in order to access
memory locations.
When activated by Dallas Semiconductor, the security
option prevents unauthorized access. A sequence of
events must occur to gain access to the memories
(Figure 3). First, a dummy read cycle or a 200 ns active
low reset pulse is executed to initialize the sequence.
Second, a 64-bit access code must be consecutively
written to the DS1221 using the write enable signal
(WE), the chip enable signal (CE), and the data input/
output signal (DQ). The code is written to the DS1221
without regard to the address. Actual RAM locations are
not written, as the security option is intercepting the data
path until access is granted. Instead, a special 64-bit
write only register is written. Following the 64 write
cycles, the register is compared to a 64-bit pattern
uniquely defined by the user and programmed into the
DS1221 by Dallas Semiconductor at the time of manufacture. This pattern can only be interrogated by an intelligent controller within the DS1221 and cannot be
read by the user. If a read cycle occurs before 64 write
cycles are completed, the security sequence is aborted.
When a correct match for 64 bits is received, the third
NOTE:
Contact Dallas Semiconductor sales office for code assignments.
SECURITY OPTION
AC ELECTRICAL CHARACTERISTICS
PARAMETER
(0°C to 70°C; VCC = 5V ± 10%)
SYMBOL
MIN
TYP
MAX
UNITS
Read Cycle Time
tRC
250
CE Access Time
tCO
200
ns
RD Access Time
tOE
100
ns
CE to Output Low Z
tCOE
10
ns
RD to Output Low Z
tOEE
10
ns
CE to Output High Z
tOD
RD to Output High Z
tODO
ns
100
ns
100
ns
Read Recovery
tRR
50
ns
Write Cycle
tWC
250
ns
Write Pulse Width
tWP
170
ns
Write Recovery
tWR
50
ns
Data Setup
tDS
100
ns
Data Hold Time
tDH
0
ns
CE Pulse Width
tCW
170
ns
Reset Pulse Width
tRST
200
ns
022194 6/8
NOTES
DS1221
POWER-DOWN Figure 5
VIH
A,B
VALID
VIL
tAS
VIH
CE
VIL
tPF
tPD
VBAT–0.2V
tCE
CE0 – CE3
VIL
tF
4.5V
VCCI
4.25
tFB
3V
POWER-UP Figure 6
VIH
A,B
VALID
VIL
tAS
VIH
CE
VIL
VBAT–0.2V
CE0 – CE3
VIL
tREC
tPD
4.5V
4.25V
VCCI
tR
022194 7/8
DS1221
READ CYCLE TO SECURITY OPTION Figure 7
WE=VIH
tRC
tPR
tCO
CE
tOD
tOE
RD
tODO
tOEE
tCOE
OUTPUT DATA VALID
DQ0
WRITE CYCLE TO SECURITY OPTION Figure 8
CE=VIH
tWC
tWR
tWP
WE
tWR
tCW
CE
tDH
tDS
DQ0
tDH
DATA VALID
NOTES:
1. tDH and tDS are functions of the first occurring edge of WE or CE.
2. tWR is a function of the latter occurring edge of WE or CE.
RESET FOR SECURITY OPTION Figure 9
tRST
RST
022194 8/8