ETC DSP56852EVMUM

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DSP56852EVMUM/D
Rev. 2.0, 10/07/2002
DSP56852 Evaluation Module
User’s Manual
© Motorola, Inc., 2002. All rights reserved.
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Table of Contents
Preface
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Chapter 1
Introduction
1.1
1.2
1.3
DSP56852EVM Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1
DSP56852EVM Configuration Jumpers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2
DSP56852EVM Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4
Chapter 2
Technical Summary
2.1
DSP56852 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2
2.2
Program and Data Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3
2.2.1
SRAM Bank 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3
2.2.2
SRAM Bank 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3
2.3
SPI Serial EEPROM/Data FLASH Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5
2.4
RS-232 Serial Communications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6
2.5
Clock Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7
2.6
Operating Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7
2.7
Debug LEDs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8
2.8
Debug Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9
2.8.1
JTAG Connector. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10
2.8.2
Parallel JTAG Interface Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11
2.9
External Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-12
2.10 Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-13
2.11 Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-14
2.12 Stereo Codec . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-15
2.12.1
Analog Input/Output. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-15
2.12.2
Digital Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-16
2.13 Daughter Card Connectors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-18
2.13.1
Memory Daughter Card Expansion Connector . . . . . . . . . . . . . . . . . . . . . . 2-18
2.13.2
Peripheral Daughter Card Expansion Connector . . . . . . . . . . . . . . . . . . . . . 2-19
2.14 Test Points . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-20
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Table of Contents
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Appendix A
DSP56852EVM Schematics
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Appendix B
DSP56852EVM Bill of Material
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List of Figures
1-1
Block Diagram of the DSP56852EVM. . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2
1-2
DSP56852EVM Jumper Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3
1-3
Connecting the DSP56852EVM Cables . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4
2-1
Schematic Diagram of the External CS0 Memory Interface . . . . . . . . . . 2-3
2-2
Schematic Diagram of the External CS1/CS2 Memory Interface . . . . . . 2-4
2-3
SPI EEPROM Memory Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5
2-4
Schematic Diagram of the RS-232 Interface . . . . . . . . . . . . . . . . . . . . . . 2-6
2-5
Schematic Diagram of the Clock Interface . . . . . . . . . . . . . . . . . . . . . . . . 2-7
2-6
Schematic Diagram of the Debug LED Interface . . . . . . . . . . . . . . . . . . . 2-8
2-7
Block Diagram of the Parallel JTAG Interface. . . . . . . . . . . . . . . . . . . . 2-11
2-8
Schematic Diagram of the User Interrupt Interface . . . . . . . . . . . . . . . . 2-12
2-9
Schematic Diagram of the RESET Interface . . . . . . . . . . . . . . . . . . . . . 2-13
2-10
Schematic Diagram of the Power Supply . . . . . . . . . . . . . . . . . . . . . . . . 2-14
2-11
Codec Analog Connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-16
2-12
CS4218 Stereo Audio Codec . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-17
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List of Figures
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List of Tables
1-1
DSP56852EVM Default Jumper Options . . . . . . . . . . . . . . . . . . . . . . . . . 1-3
2-1
SPI Port Connector Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5
2-2
RS-232 Serial Connector Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6
2-3
Operating Mode Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7
2-4
LED Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8
2-5
JTAG Connector Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10
2-6
Parallel JTAG Interface Disable Jumper Selection. . . . . . . . . . . . . . . . . 2-10
2-7
Parallel JTAG Interface Connector Description . . . . . . . . . . . . . . . . . . . 2-11
2-8
Codec Sample Rate Selector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-15
2-9
SSI Port Connector Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-17
2-10
GPIO Port Connector Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-17
2-11
Memory Daughter Card Connector Description. . . . . . . . . . . . . . . . . . . 2-18
2-12
Peripheral Daughter Card Connector Description . . . . . . . . . . . . . . . . . 2-19
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List of Tables
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Preface
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This reference manual describes in detail the hardware on the DSP56852 Evaluation
Module.
Audience
This document is intended for application developers who are creating software for
devices using the Motorola DSP56852 part.
Organization
This manual is organized into two chapters and two appendixes.
•
Chapter 1, Introduction - provides an overview of the EVM and its features.
•
Chapter 2, Technical Summary - describes in detail the DSP56852 hardware.
•
Appendix A, DSP56852EVM Schematics - contains the schematics of the
DSP56852EVM.
•
Appendix B, DSP56852EVM Bill of Material - provides a list of the materials used on
the DSP56852EVM board.
Suggested Reading
More documentation on the DSP56852 and the DSP56852EVM kit may be found at URL:
http://www.mot.com/SPS/DSP/documentation/index.html
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Conventions
This manual uses the following notational conventions:
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Term or Value
Symbol
Examples
Active High Signals
(Logic One)
No special symbol
attached to the signal
name
A0
CLKO
Active Low Signals
(Logic Zero)
Noted with an
overbar in text and in
most figures
WE
OE
Hexadecimal Values
Begin with a “$” symbol
$0FF0
$80
Decimal Values
No special symbol
attached to the
number
Binary Values
Begin with the letter
“b” attached to the
number
b1010
b0011
Numbers
Considered positive
unless specifically
noted as a negative
value
5
-10
Blue Text
Linkable on-line
Bold
Reference sources,
paths, emphasis
Exceptions
In schematic drawings,
Active Low Signals may be
noted by a backslash: /WE
10
34
Voltage is often shown as
positive: +3.3V
...refer to Chapter 7,
License
...see:
http://www.mot.com/
SPS/DSP...
Definitions, Acronyms, and Abbreviations
Definitions, acronyms and abbreviations for terms used in this document are defined
below for reference..
Codec
COder/DECoder; a part used to convert analog signals to digital (coder)
and digital signals to analog (decoder)
DSP
Digital Signal Processor or Digital Signal Processing
EEPROM
Electrically Erasable Programmable Read-Only Memory
EOnCE
Enhanced On-Chip Emulation; a debug bus and port created by Motorola
to enable a designer to create a low-cost hardware interface for a
professional-quality debug environment
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DSP56852EVM User’s Manual
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EVM
Evaluation Module; a hardware platform which allows a customer to
evaluate the silicon and develop his application
GPIO
General Purpose Input and Output port on Motorola’s family of DSPs;
does not share pin functionality with any other peripheral on the chip and
can only be set as an input, output or level-sensitive interrupt input
IC
Integrated Circuit
ISSI
Improved Synchronous Serial Interface port on Motorola’s family of
DSPs
JTAG
Joint Test Action Group; a bus protocol/interface used for test and debug
LED
Light Emitting Diode
MBGA
MAP Ball Grid Array package
MPIO
Multi Purpose Input and Output port on Motorola’s family of DSPs;
shares package pins with other peripherals on the chip and can function
as a GPIO
PCB
Printed Circuit Board
PLL
Phase Locked Loop
RAM
Random Access Memory
ROM
Read Only Memory
SCI
Serial Communications Interface port on Motorola’s family of DSPs
SPI
Serial Peripheral Interface port on Motorola’s family of DSPs
SRAM
Static Random Access Memory
SSI
Synchronous Serial Interface port on Motorola’s family of DSPs
WS
Wait State
References
The following sources were referenced to produce this manual:
[1] DSP56800E Reference Manual, Motorola
[2] DSP56852 Digital Signal Processor User’s Manual, Motorola
[3] DSP56852 Digital Signal Processor Technical Data, Motorola
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Chapter 1
Introduction
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The DSP56852EVM is used to demonstrate the abilities of the DSP56852 and to provide a
hardware tool allowing the development of applications that use the DSP56852.
The DSP56852EVM is an evaluation module board that includes a DSP56852 part, 16-bit
stereo codec, external memory and a daughter card expansion interface. The daughter
card expansion connectors are for signal monitoring and user feature expandability.
The DSP56852EVM is designed for the following purposes:
•
Allowing new users to become familiar with the features of the 56800E
architecture. The tools and examples provided with the DSP56852EVM facilitate
evaluation of the feature set and the benefits of the family.
•
Serving as a platform for real-time software development. The tool suite enables
the user to develop and simulate routines, download the software to on-chip or
on-board RAM, run it, and debug it using a debugger via the JTAG/Enhanced
OnCE (EOnCE) port. The breakpoint features of the EOnCE port enable the user
to easily specify complex break conditions and to execute user-developed software
at full speed until the break conditions are satisfied. The ability to examine and
modify all user-accessible registers, memory and peripherals through the EOnCE
port greatly facilitates the task of the developer.
•
Serving as a platform for hardware development. The hardware platform enables
the user to connect external hardware peripherals. The on-board peripherals can be
disabled, providing the user with the ability to reassign any and all of the DSP's
peripherals. The EOnCE port's unobtrusive design means that all memory on the
board and on the DSP chip is available to the user.
1.1 DSP56852EVM Architecture
The DSP56852EVM facilitates the evaluation of various features present in the DSP56852
part. The DSP56852EVM can be used to develop real-time software and hardware
products based on the DSP56852. The DSP56852EVM provides the features necessary
for a user to write and debug software, demonstrate the functionality of that software and
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interface with the customer’s application-specific device(s). The DSP56852EVM is
flexible enough to allow a user to fully exploit the DSP56852’s features to optimize the
performance of their product, as shown in Figure 1-1.
DSP56852
RESET
LOGIC
RESET
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MODE
LOGIC
MODE
CS0
(Program Memory)
128Kx16-bit SRAM
SPI
SPI Data FLASH
1M-bit
IRQ
IRQ Interface
SCI
RS-232
Interface
DSub
9-Pin
Address,
Data &
Control
Peripheral
Daughter Card
Connector
CS1/CS2
(Data Memory)
128Kx16-bit SRAM
Memory
Daughter Card
Connector
JTAG
Connector
DSub
25-Pin
JTAG/EOnCE
Stereo 16-bit
Codec
Amp
Parallel
JTAG
Interface
4.00MHz
Crystal
ISSI
GPIO
XTAL/EXTAL
+1.8V, +3.3V
& GND
Stereo Line In
Stereo Line Out
Headphone Jack
Debug LEDs
Power Supply
+1.8V, +3.3V & +5.0V
Figure 1-1. Block Diagram of the DSP56852EVM
1.2 DSP56852EVM Configuration Jumpers
Ten jumper groups, (JG1-JG10), shown in Figure 1-2, are used to configure various
features on the DSP56852EVM board. Table 1-1 describes the default jumper group
settings.
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DSP56852EVM Configuration Jumpers
2 4
8
2
JG3
JG5
JG6
7
1
JG2
3
1
JG8
1 3
JG7
JG1
1
3
P6
P1
S3
JG7
TB1
P2
JG8
JTAG
RESET
JG6
JG4
JG5
Y1
J3
J2
JG2
JG3
JG4
JG9
U2
S1
U1
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IRQA
5
6
2
1
2
4
1
3
S2
U3
DSP56852EVM
RE10520B REV
S/N
1
2
9
10
HEADPHONE
IRQB
JG1
P5
J1
S5
JG9
JG10
S5
JG10
S4
P3
LEDS
U7
P4
U5
LINE
IN
LINE
OUT
Figure 1-2. DSP56852EVM Jumper Reference
Table 1-1. DSP56852EVM Default Jumper Options
Jumper
Group
Comment
Jumpers
Connections
JG1
Enable on-board Byte selectable SRAM via CS1/CS2 (U3)
JG2
Enable on-board Word selectable SRAM via CS0 (U2)
1–2
JG3
Use on-board XTAL crystal input for DSP oscillator
1–2
JG4
Use on-board EXTAL crystal input for DSP oscillator
2–3
JG5
Enable SCI Port to RS-232 transceiver
JG6
Enable SPI Port to Serial EEPROM/Data FLASH
JG7
Enable on-board Parallel JTAG Host/Target Interface
NC
JG8
Enable RS-232 output
NC
JG9
Enable SSI Port for CODEC data.
1-2, 3-4, 5-6, 7-8,
9-10
JG10
Enable GPIO for CODEC control.
1-2, 3-4, 5-6
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1–2, 3-4
1–2, 3–4, 5–6 & 7–8
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1.3 DSP56852EVM Connections
An interconnection diagram is shown in Figure 1-3 for connecting the PC and the external
+12.0V DC/AC power supply or external +5.0V DC lab power supply to the
DSP56852EVM board.
Parallel Extension
Cable
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DSP56852EVM
PC-compatible
Computer
P1
Connect cable
to Parallel/Printer port
P2
TB1
External
with 2.1mm, +12.0V
receptacle
Power
connector
+5.0V
Lab
Supply
Figure 1-3. Connecting the DSP56852EVM Cables
Perform the following steps to connect the DSP56852EVM cables:
1. Connect the parallel extension cable to the Parallel port of the host computer.
2. Connect the other end of the parallel extension cable to P1, shown in Figure 1-3,
on the DSP56852EVM board. This provides the connection which allows the host
computer to control the board.
3. Make sure that the external +12.0V DC 1.2A switching power supply or the
external +5.0V DC 1A lab power supply is not plugged into a +120V AC power
source.
4. Connect the 2.1mm output power plug from the external switching power supply
into P2, shown in Figure 1-3, on the DSP56852EVM board. Optionally, attach an
external +5.0V DC lab power supply via the 2-pin terminal block, TB1.
5. Apply power to the external power supply. The green Power-On LED, LED7, will
illuminate when power is correctly applied.
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Chapter 2
Technical Summary
The DSP56852EVM is designed as a versatile Digital Signal Processor, (DSP),
development card for developing real-time software and hardware products to support a
new generation of applications in digital and wireless messaging, digital answering
machines, feature phones, modems, and digital cameras. The power of the 16-bit
DSP56852 DSP, combined with the on-board 128K × 16-bit external program/data static
RAM (SRAM), 128K × 16-bit external data/program SRAM, RS-232 interface, stereo
16-bit codec interface, Daughter Card Expansion interface and parallel JTAG interface,
makes the DSP56852EVM ideal for developing and implementing many audio and voice
algorithms, as well as for learning the architecture and instruction set of the DSP56852
processor.
The main features of the DSP56852EVM, with board and schematic reference designators
include:
•
DSP56852 16-bit +1.8V/+3.3V Digital Signal Processor operating at 120MHz [U1]
•
External fast static RAM (FSRAM) memory, configured as:
— 128K×16-bit of memory [U2] with 1 wait state at 120MHz via CS0
— 128K×16-bit of memory [U3] with 1 wait state at 120MHz via CS1/CS2
•
1M-bit Serial EEPROM/Data FLASH [U4]
•
4.00MHz crystal oscillator for DSP frequency generation [Y1]
•
Optional external oscillator frequency input connectors [JG3 and JG4]
•
Joint Test Action Group (JTAG) port interface connector for an external debug
Host Target Interface [J3]
•
On-board Parallel JTAG Host Target Interface, with a connector for a PC printer
port cable [P1]
•
RS-232 interface for easy connection to a host processor [U6 and P6]
•
16-bit stereo codec interface [U5, JG9, JG10, P3 and P4]
•
Stereo headphone interface [U12 and P5]
•
Codec sample rate selector [S4]
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•
Peripheral Daughter Card Expansion Connector, to allow the user to connect his
own SCI, ISSI, SPI or GPIO-compatible peripheral to the DSP [J2]
•
Memory Daughter Card Expansion Connector, to allow the user to connect his own
memory or memory device to the DSP [J1]
•
On-board power regulation from an external +12V DC-supplied power input [P2]
•
On-board power regulation from an optional +5V DC-supplied power input [TB1]
•
Light Emitting Diode (LED) power indicator [LED7]
•
Six on-board real-time user debugging LEDs [LED1-6]
•
Boot MODE selector [S5]
•
Manual RESET push-button [S3]
•
Manual interrupt push-button for IRQA [S1]
•
Manual interrupt push-button for IRQB [S2]
2.1 DSP56852
The DSP56852EVM uses a Motorola DSP56852VF120 part, designated as U1 on the
board and in the schematics. This part will operate at a maximum speed of 120MHz. A full
description of the DSP56852, including functionality and user information, is provided in
these documents:
•
DSP56852 Technical Data, (DSP56852/D): Provides features list and
specifications, including signal descriptions, DC power requirements, AC timing
requirements and available packaging
•
DSP56852 User’s Manual, (DSP56852UM/AD): Provides an overview description
of the DSP and detailed information about the on-chip components, including the
memory and I/O maps, peripheral functionality, and control/status register
descriptions for each subsystem
•
DSP56800E Reference Manual, (DSP56800ERM/D): Provides a detailed
description of the core processor, including internal status and control registers and
a detailed description of the family instruction set
Refer to these documents for detailed information about chip functionality and operation.
They can be found on this URL:
http://www.motorola.com/semiconductors
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Program and Data Memory
2.2 Program and Data Memory
The DSP56852EVM contains two 128Kx16-bit Fast Static RAM banks. SRAM bank 0 is
controlled by CS0 and SRAM bank 1 is controlled by CS1 and CS2.
2.2.1 SRAM Bank 0
This memory bank will operate with one wait state access while the DSP56852 is running
at 120MHz and can be disabled by removing the jumper at JG2.
GS72116
DSP56852
A0-A16
A0-A16
D0-D15
DQ0-DQ15
RD
OE
WR
WE
CS0
+3.3V
Jumper Pin 1-2:
Enable SRAM
Jumper Removed:
Disable SRAM
JG2
1
2
Freescale Semiconductor, Inc...
SRAM bank 0, which is controlled by CS0, uses a 128K×16-bit Fast Static RAM (GSI
GS72116, labelled U2) for external memory expansion; see the FSRAM schematic
diagram in Figure 2-1. CS0 can be configured to use this memory bank as 16-bit program
memory, data memory, or both. Additionally, CS0 can be configured to assign this
memory’s size and starting address to any modulo address space.
CE
Figure 2-1. Schematic Diagram of the External CS0 Memory Interface
2.2.2 SRAM Bank 1
SRAM bank 1, which is controlled by CS1 and CS2, uses a 128K×16-bit Fast Static RAM
(GSI GS72116, labelled U3) for external memory expansion; see the FSRAM schematic
diagram in Figure 2-2. Using CS1 and CS2, this memory bank can be configured as byte
(8-bit) or word (16-bit) accessable program memory, data memory, or both. Additionally,
CS1 and CS2 can be configured to assign this memory’s size and starting address to any
modulo address space.
MOTOROLA
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This memory bank will operate with one wait state access while the DSP56852 is running
at 120MHz and can be disabled by removing the jumpers at JG1.
GS72116
DSP56852
A0-A16
A0-A16
D0-D15
DQ0-DQ15
OE
RD
WR
Freescale Semiconductor, Inc...
JG1
CS1
1 2
CS2
3 4
WE
LB
HB
CE
Jumper Pin 1-2:
Enable SRAM Low Byte
Jumper Pin 3-4:
Enable SRAM High Byte
Figure 2-2. Schematic Diagram of the External CS1/CS2 Memory Interface
2-4
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SPI Serial EEPROM/Data FLASH Memory
2.3 SPI Serial EEPROM/Data FLASH Memory
Freescale Semiconductor, Inc...
A 1M-bit +3.3V SPI serial EEPROM/Data FLASH Memory, Atmel AT45DB011B-SC, is
provided on the DSP56852EVM, reference Figure 2-3. This memory connects directly to
the SPI Port through a header on the DSP56852. It can be used to load program code and
data into the DSP56852’s internal or external memory spaces. Jumper block JG6 is
provided to allow the user to disconnect the on-board SPI EEPROM/Data FLASH from
the SPI port and allow him to connect his own SPI port peripheral. Since the SPI port and
ISSI port are multiplexed on the DSP56852, the SPI port jumpers need to be removed to
use the ISSI port. The header details are shown in Table 2-1.
Data FLASH Enable
DSP56852
(SPI Port Connector)
Serial EEPROM /
Data FLASH
MOSI/SRFS
SDI
MISO/SRCK
SDO
SCLK/STCK
SCK
SS/STFS/PC3
CS
Figure 2-3. SPI EEPROM Memory Block Diagram
.
Table 2-1. SPI Port Connector Description
JG6
MOTOROLA
Pin #
Signal
Pin #
Signal
1
SS/STFS/PC3
2
CS
3
MISO/SRCK
4
SDO
5
MOSI/SRFS
6
SDI
7
SCLK/STCK
8
SCK
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2.4 RS-232 Serial Communications
Freescale Semiconductor, Inc...
The DSP56852EVM provides an RS-232 interface by the use of an RS-232 level
converter, (Maxim MAX3245EEAI, designated as U6). Refer to the RS-232 schematic
diagram in Figure 2-4. The RS-232 level converter transitions the SCI UART’s +3.3V
signal levels to RS-232-compatible signal levels and connects to the host’s serial port via
connector P6. Flow control is not provided, but could be implemented using uncommitted
GPIO signals. The pinout of connector P6 is listed in Table 2-2. The RS-232 level
converter/transceiver can be disabled by placing a jumper at JG8.
RS-232
Level Converter
Interface
DSP56852
P6
1
6
TXD
T1in
RXD
R1out
T1out
2
R1in
3
7
8
+3.3V
x
FORCEOFF
Jumper Removed:
Enable RS-232
Jumper Pin 1-2:
Disable RS-232
4
9
5
JG8
1
2
Figure 2-4. Schematic Diagram of the RS-232 Interface
.
Table 2-2. RS-232 Serial Connector Description
P6
2-6
Pin #
Signal
Pin #
Signal
1
Jumper to 6 & 4
6
Jumper to 1 & 4
2
TXD
7
Jumper to 8
3
RXD
8
Jumper to 7
4
Jumper to 1 & 6
9
N/C
5
GND
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Operating Mode
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2.5 Clock Source
The DSP56852EVM uses a 4.00MHz crystal, Y1, connected to its External Crystal Inputs,
EXTAL and XTAL. To achieve its 120MHz maximum operating frequency, the
DSP56852 uses its internal PLL to multiply the input frequency by 30. An external
oscillator source can be connected to the DSP by using the oscillator bypass connectors,
JG3 and JG4; see Figure 2-5. If the input frequency is above 4MHz, then the EXTAL
input should be jumpered to ground by adding a jumper between JG4 pins 1 and 2. The
input frequency would then be injected on JG3’s pin 2. If the DSP needs to be
synchronized to the codec’s sample frequency, then the DSP’s input frequency should be
jumpered using the 12.2280MHz codec frequency. If the input frequency is below 4MHz,
then the input frequency can be injected on JG4’s pin 2.
EXTERNAL
OSCILLATOR
HEADERS
DSP56852
JG4
3
2
EXTAL
1
4.00MHz
JG3
1
2
3
12.2880MHz
XTAL
Figure 2-5. Schematic Diagram of the Clock Interface
2.6 Operating Mode
The DSP56852EVM provides a boot-up MODE selection switch, S5. This switch is used
to select the operating mode of the DSP as it exits RESET. Refer to the DSP56852 User’s
Manual for a complete description of the chip’s operating modes. Table 2-3 shows the
two operation modes available on the DSP56852.
Table 2-3. Operating Mode Selection
MOTOROLA
Operating Mode
S5 (ON)
Comment
0
1–2, 3-4 & 5-6
1
3-4 & 5-6
Bootstrap from SPI
2
1-2 & 5-6
Normal Expanded mode
3
5-6
Bootstrap from External byte-wide memory
Development Expanded mode
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2.7 Debug LEDs
Six on-board Light-Emitting Diodes, (LEDs), are provided to allow real-time debugging
for user programs. These LEDs will allow the programmer to monitor program execution
without having to stop the program during debugging; refer to Figure 2-6. Table 2-4
describes the control of each LED.
Table 2-4. LED Control
Freescale Semiconductor, Inc...
Controlled by
User LED
Port
Signal
LED1
Port A
PA2
LED2
Port C
PC4
LED3
Port C
PC5
LED4
Port C
PC3
LED5
Port E
PE1
LED6
Port E
PE0
Setting PA2, PC4, PC5, PC3, PE1 or PE0 to a Logic One value will turn on the associated
LED.
DSP56852
INVERTING BUFFER
+3.3V
RED LED
PA2
YELLOW LED
PC4
GREEN LED
PC5
RED LED
PC3
YELLOW LED
PE1
GREEN LED
PE0
Figure 2-6. Schematic Diagram of the Debug LED Interface
2-8
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Debug Support
2.8 Debug Support
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The DSP56852EVM provides an on-board Parallel JTAG Host Target Interface and a
JTAG interface connector for external Target Interface support. Two interface connectors
are provided to support each of these debugging approaches. These two connectors are
designated the JTAG connector and the Host Parallel Interface Connector.
MOTOROLA
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2.8.1 JTAG Connector
The JTAG connector on the DSP56852EVM allows the connection of an external Host
Target Interface for downloading programs and working with the DSP56852’s registers.
This connector is used to communicate with an external Host Target Interface which
passes information and data back and forth with a host processor running a debugger
program. Table 2-5 shows the pin-out for this connector.
Table 2-5. JTAG Connector Description
Freescale Semiconductor, Inc...
J3
Pin #
Signal
Pin #
Signal
1
TDI
2
GND
3
TDO
4
GND
5
TCK
6
GND
7
NC
8
KEY
9
RESET
10
TMS
11
+3.3V
12
NC
13
DE
14
TRST
When this connector is used with an external Host Target Interface, the parallel JTAG
interface should be disabled by placing a jumper in jumper block JG7. Reference
Table 2-6 for this jumper’s selection options.
Table 2-6. Parallel JTAG Interface Disable Jumper Selection
2-10
JG7
Comment
No jumpers
On-board Parallel JTAG Interface Enabled
1–2
Disable on-board Parallel JTAG Interface
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Debug Support
2.8.2 Parallel JTAG Interface Connector
The Parallel JTAG Interface Connector, P1, allows the DSP56852 to communicate with a
Parallel Printer Port on a Windows PC; reference Figure 2-7. Using this connector, the
user can download programs and work with the DSP56852’s registers. Table 2-7 shows
the pin-out for this connector. When using the parallel JTAG interface, the jumper at JG7
should be removed, as shown in Table 2-6.
Parallel JTAG Interface
DB-25 Connector
IN OUT
OUT IN
IN OUT
TDI
TDO
TRST
TMS
IN
OUT
TMS
TCK
IN
OUT
TCK
P_RESET
IN
OUT
RESET
P_DE
IN
OUT
DE
TDI
TDO
Freescale Semiconductor, Inc...
DSP56852
P_TRST
+3.3V
Jumper Removed:
Enable JTAG I/F
EN
JG7
1
2
Jumper Pin 1-2:
Disable JTAG I/F
Figure 2-7. Block Diagram of the Parallel JTAG Interface
Table 2-7. Parallel JTAG Interface Connector Description
P1
MOTOROLA
Pin #
Signal
Pin #
Signal
1
NC
14
NC
2
PORT_RESET
15
PORT_IDENT
3
PORT_TMS
16
NC
4
PORT_TCK
17
NC
5
PORT_TDI
18
GND
6
PORT_TRST
19
GND
7
PORT_DE
20
GND
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Table 2-7. Parallel JTAG Interface Connector Description
Freescale Semiconductor, Inc...
P1
Pin #
Signal
Pin #
Signal
8
PORT_IDENT
21
GND
9
PORT_VCC
22
GND
10
NC
23
GND
11
PORT_TDO
24
GND
12
NC
25
GND
13
PORT_CONNECT
2.9 External Interrupts
Two on-board push-button switches are provided for external interrupt generation, as
shown in Figure 2-8. S1 allows the user to generate a hardware interrupt for signal line
IRQA. S2 allows the user to generate a hardware interrupt for signal line IRQB. These two
switches allow the user to generate interrupts for his user-specific programs.
+3.3V
DSP56852
10K
S1
IRQA
0.1µF
+3.3V
10K
S2
IRQB
0.1µF
Figure 2-8. Schematic Diagram of the User Interrupt Interface
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Reset
2.10 Reset
Logic is provided on the DSP56852 to generate an internal Power-On RESET. Additional,
reset logic is provided to support the RESET signals from the JTAG connector, the
Parallel JTAG Interface and the user RESET push-button; refer to Figure 2-9.
JTAG_RESET
RESET
RESET
PUSHBUTTON
Freescale Semiconductor, Inc...
MANUAL RESET
TRST
JTAG_TAP_RESET
Figure 2-9. Schematic Diagram of the RESET Interface
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Freescale Semiconductor, Inc...
2.11 Power Supply
The main power input, +12.0V DC/AC, to the DSP56852EVM is through a 2.1mm coax
power jack. An optional +5.0V DC power supply input is available through a 2-pin
terminal block, TB1. A +12.0V DC 1.2A power supply is provided with the
DSP56852EVM; however, less than 500mA is required by the EVM. The remaining
current is available for user daughter card applications when connected to the daughter
card interface. The power regulation on the DSP56852EVM provides +5.0V DC voltage
regulation for the codec’s analog circuits and to the additonal voltage regulation logic on
the EVM. The additonal voltage regulation logic provides +1.8V DC voltage regulation
for the DSP’s core and +3.3V DC voltage regulation for the DSP’s I/O, memory, parallel
JTAG interface and supporting logic; refer to Figure 2-10. Power applied to the
DSP56852EVM is indicated with a Power-On LED, referenced as LED7.
P2
+12.0V DC
+5.0V
Regulator
Power
Condition
+5.0V DC
Analog
+3.3V
Regulator
+3.3V DC
CODEC
TB1
+5.0V DC
DSP56852
GND
DSP56852EVM
PARTS
+1.8V
Regulator
+1.8V DC
DSP56852
CORE
Figure 2-10. Schematic Diagram of the Power Supply
2-14
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Stereo Codec
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2.12 Stereo Codec
A 16-bit audio quality stereo codec, Crystal Semiconductor CS4218, is connected to the
DSP56852’s ISSI port to support audio, voice and signal analysis applications. The codec
is clocked with a 12.288MHz oscillator. This allows the codec to operate between a
sample frequency of 8KHz and 48KHz. The sample rate can be manually set by setting the
appropriate switch positions on DIP switch S4. The sample rate selections possible using
this three-position DIP switch are detailed in Table 2-8. The codec supports +3.3V digital
levels, eliminating the need for voltage level translation circuitry. Additionally, a set of
zero ohm resistors are provided on the EVM to allow a user to disconnect the on-board
codec from the ISSI port and allow him to connect his own codec to the ISSI port; see
Figure 2-12. The on-board codec has analog signal conditioning logic, allowing direct
connection to its line level input and line level output signals through two 1/8” stereo
jacks; reference Figure 2-11.
Table 2-8. Codec Sample Rate Selector
SW 4
Position 3
(MF6)
SW 4
Position 2
(MF7)
SW 4
Position 3
(MF8)
Sample Rate
ON
ON
ON
48.00KHz
ON
ON
OFF
32.00KHz
ON
OFF
ON
24.00KHz
ON
OFF
OFF
19.20KHz
OFF
ON
ON
16.00KHz
OFF
ON
OFF
12.00KHz
OFF
OFF
ON
9.60KHz
OFF
OFF
OFF
8.00KHz
2.12.1 Analog Input/Output
The DSP56852EVM uses jacks for line-level stereo input, line-level stereo output and
stereo headphone output. A National Semiconductor LM4880 provides the drive required
for the use of headphones. This device offers a THD, which is superior by a factor of two
to the CS4218’s on-chip headphone drive circuitry. The basic Analog codec connections
are shown in Figure 2-11.
MOTOROLA
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CS4218
P3
Line-Level
Input
P4
RIN1
LOUTL
LIN1
LOUTR
Line-Level
Output
A
A
LM4880
P5
Headphone
Output
A
Freescale Semiconductor, Inc...
Figure 2-11. Codec Analog Connections
2.12.2 Digital Interface
The serial interface of the codec transfers digital audio data and control data into and out
of the device. The ISSI port, which is multiplexed with the SPI port, consists of
independent transmitter and receiver sections and is used for serial communication with
the codec.
On the DSP side, the Serial Transmit Data pin, STXD, is an output when data is being
transmitted to the codec. The Serial Receive Data pin, SRXD, is an input when data is
being received from the codec. These two pins are connected to the codec’s Serial Data
Input, SDIN, and Serial Data Output, SDOUT, pins.
The DSP’s Transmit Serial Clock pin, STCK, provides the serial bit rate clock for the ISSI
interface. It is connected to the CODEC’s Serial Port Clock pin, SCLK. Data is
transmitted on the rising edge of SCLK and is received on the falling edge of SCLK.
The DSP’s GPIO PORT C Bit 4 pin, PC4, is programmed to control the codec’s Active
Low Reset signal, RESET.
The Serial Transmit Frame Sync pin, STFS, is programmed to control the codec’s Frame
Sync signal, FSYNC. This signal is sampled by SCLK, with a rising edge indicating a new
frame is about to start. The FSYNC frequency is always the system’s sample rate. It may
be an input to the codec, or it may be an output from the codec in data mode.
The basic codec digital connections are shown in Figure 2-12, Table 2-9 and Table 2-10.
The codec’s MODE is set by the three MODE selection resistors, R66-R68. In the factory
default setting of MODE 4, the codec is set to be the Master of the ISSI bus with its data
word set at 32 bits per frame; i.e., 16 bits Left channel and 16 bits Right channel. The
sample rate is selected on the Sample Rate Selector switch S4; see Table 2-8 for selection
options. Codec control information is sent over a separate serial port using: PC5 as the
Control Chip Select signal, CCS; PE0 as the Control Data Input signal, CDIN; and PE1 as
the Control Clock signal, CCLK.
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Stereo Codec
DSP56852
CODEC Enable Logic
CS4218
JG9
STXD
1
2
SDIN
SRXD
3
4
SDOUT
STCK
5
6
SCLK
STFS
7
8
FSYNC
PC4
9
10
RESET
PC5
1
2
CCS
PE0
3
4
CDIN
PE1
5
6
CCLK
Freescale Semiconductor, Inc...
JG10
Figure 2-12. CS4218 Stereo Audio Codec
.
Table 2-9. SSI Port Connector Description
JG9
.
Pin #
DSP Signal
Pin #
Codec Signal
1
STXD
2
SDIN
3
SRXD
4
SDOUT
5
STCK
6
SCLK
7
STFS
8
FSYNC
9
PC4
10
RESET
Table 2-10. GPIO Port Connector Description
JG10
MOTOROLA
Pin #
DSP Signal
Pin #
Codec Signal
1
PC5
2
CCS
3
PE0
4
CDIN
5
PE1
6
CCLK
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2.13 Daughter Card Connectors
The EVM board contains two daughter card expansion connectors. One connector, J1,
contains the DSP’s external memory bus signals. The other connector, J2, contains the
DSP’s peripheral port signals.
2.13.1 Memory Daughter Card Expansion Connector
The DSP’s external memory bus signals are connected to the Memory Daughter Card
Expansion connector, J1. Table 2-11 shows the port signal-to-pin assignments.
Freescale Semiconductor, Inc...
Table 2-11. Memory Daughter Card Connector Description
J1
2-18
Pin #
Signal
Pin #
Signal
1
A10
2
A11
3
A9
4
CS1
5
A8
6
A15
7
A7
8
A14
9
A20
10
A19
11
WR
12
A13
13
D0
14
A12
15
D1
16
D8
17
D2
18
D9
19
GND
20
GND
21
D3
22
D10
23
D4
24
D11
25
D5
26
D12
27
D6
28
D13
29
A18
30
A17
31
D7
32
D14
33
CS0
34
D15
35
A0
36
RD
37
A1
38
A6
39
A16
40
GND
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Daughter Card Connectors
Freescale Semiconductor, Inc...
J1
Pin #
Signal
Pin #
Signal
41
A2
42
A5
43
A3
44
A4
45
A19/CS3
46
CS2
47
+3.3V
48
+3.3V
49
GND
50
GND
51
+5.0V
2.13.2 Peripheral Daughter Card Expansion Connector
The DSP’s peripheral port signals are connected to the Peripheral Daughter Card
Expansion connector, J2. Table 2-12 shows the port signal-to-pin assignments.
Table 2-12. Peripheral Daughter Card Connector Description
J2
MOTOROLA
Pin #
Signal
Pin #
Signal
1
CS0/PA0
2
CS1/PA1
3
A20/CLKO
4
CS2/PA2
5
A17/TIO0
6
A18/TIO1
7
GND
8
GND
9
GND
10
GND
11
GND
12
GND
13
GND
14
GND
15
SRXD
16
CS0/PA0
17
MOSI/SRFS
18
CS1/PA1
19
SCK/SCLK
20
CS2/PA2
21
GND
22
GND
23
MOSI
24
GND
25
MISO
26
GND
27
GND
28
GND
29
SS
30
GND
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Table 2-12. Peripheral Daughter Card Connector Description (Continued)
Freescale Semiconductor, Inc...
J2
Pin #
Signal
Pin #
Signal
31
MISO/SRCK
32
GND
33
SS/STFS
34
GND
35
RESET
36
GND
37
GND
38
GND
39
STXD
40
GND
41
SCK/STCK
42
GND
43
IRQB
44
RXD
45
IRQA
46
TXD
47
+3.3V
48
+3.3V
49
GND
50
GND
51
+5.0V
2.14 Test Points
The DSP56852EVM board has a total of seven test points. Three digital GND test points
are located in corners of the board. The +5.0VA and AGND test points are located in the
analog corner of the board. The +1.8V and +3.3V test points are located in the power
supply section of the board.
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Freescale Semiconductor, Inc...
Appendix A
DSP56852EVM Schematics
MOTOROLA
DSP56852EVM Schematics
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A-1
A-2
A
B
C
D
E
U1
DSP56852EVM User’s Manual
3
2
1
Freescale Semiconductor, Inc...
4
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
E4
F2
F3
F4
F1
G3
G2
J1
H2
H3
J2
H4
G4
J3
F5
H5
E5
F6
G5
H6
J8
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
G7
H7
H8
G8
H9
F8
F7
G6
E8
E7
E6
D8
D7
D9
C8
A9
XTAL
A0
EXTAL
A1
A2
IRQA
A3
A4
IRQB
A5
A6
STXD/PC0
A7
SRXD/PC1
A8
SCK/STCK/PC2
A9
SS/STFS/PC3
A10
MISO/SRCK/PC4
A11
MOSI/SRFS/PC5
A12
A13
A14
RXD/PE0
A15
TXD/PE1
A16
A17/TIO0
A18/TIO1
A19/CS3
A20/CLKOUT
VDDC1
VDDC2
VDDC3
D0
D1
D2
VSSC1
D3
VSSC2
D4
VSSC3
D5
D6
D7
D8
D9
VDD1
D10
D11
VDD2
D12
VDD3
D13/MODEA
VDD4
D14/MODEB
VDD5
D15/MODEC
VDD6
/CS0
/CS1
/CS2
D2
D3
C3
CS0/PA0
CS1/PA1
CS2/PA2
/RD
/WR
E2
E3
RD
WR
TDI
TDO
TCK
/TRST
TMS
/DE
B7
A8
C6
D6
C7
B8
TDI
TDO
TCK
TRST
TMS
DE
/ R E S ET
D5
RESET
A7
A6
XTAL
EXTAL
A1
C2
/IRQA
/IRQB
+3.3V
4
U 1 4A
L E D1
B2
A2
A3
B3
C4
C5
STXD
S R XD
SCK
/SS
MISO
MOSI
/CS2
B4
D4
RXD
TXD
MISO
PA2
1
R72
2
M C 74AC04AD
RED LED
270
U 1 4B
L E D2
PC4
3
R73
4
YELLOW LED
270
M C 74AC04AD
E1
J5
E9
U14C
+1.8V
L E D3
MOSI
PC5
5
R74
6
GREEN LED
270
M C 74AC04AD
D1
J4
F9
3
U14D
L E D4
/SS
C1
H1
J7
G9
B9
A4
B5
VSSA
B6
R75
8
RED LED
270
M C 74AC04AD
U 1 4E
L E D5
TXD
PE1
11
R76
10
M C 74AC04AD
YELLOW LED
270
U14F
L E D6
RXD
VDDA
9
+3.3V
B1
G1
J6
J9
C9
A5
VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
PC3
PE0
13
M C 74AC04AD
+ 3 .3V
R77
12
GREEN LED
270
2
DSP56852VF120
DSP Standard Products Division
2100 East Elliot Road
Tempe, Arizona 85284
(480) 413-5090
Title
MOTOROLA
Size
B
A
B
C
1
FAX: (480) 413-2510
DSP56852 Processor and DEBUG LEDS
Document
Number
Rev.
DSP56852EVM.DSN
Date: Thursday, January 10, 2002
D
Figure A-1. DSP56852 Processor and DEBUG LEDS
Designer: DSPD Design
Sheet 1
E
of
10
1.4
MOTOROLA
A
B
C
D
E
+3.3V
JG4
3
2
VCC/3
4
EXTAL
R70
10K
IRQA PUSHBUTTON
1
4
Freescale Semiconductor, Inc...
S1
Y1
4.00MHz
R16
10M
/IRQA
OSC BYPASS
C30
0.1uF
JG3
1
+3.3V
XTAL
2
12.288MHZ
3
+3.3V
R79
10K
+3.3V
VCC/2
DSP56852EVM Schematics
3
S2
1
3
/IRQB
R45
10K
DNP
R85
10K
2
R71
10K
IRQB PUSHBUTTON
C31
0.1uF
S3
/POR
RESET PUSHBUTTON
C32
0.1uF
R80
+3.3V
MODA
D13
10K
470K
S5
R81
+3.3V
MODB
10K
1
3
5
2
4
6
D13
D14
D15
D14
Vcc
RST
3
R43
2
470K
U16
2
R86
1
R82
/POR
GND
MODC
Boot MODE
Select
D15
10K
R41
470K
DS1818
DSP Standard Products Division
2100 East Elliot Road
Tempe, Arizona 85284
3
(480) 413-5090
FAX: (480) 413-2510
DS1818
1
1
Title
2
Size
A
A
B
RESET, CLOCK, BOOT MODE & IRQS
Document
Number
Rev.
DSP56852EVM.DSN
Date: Thursday, January 10, 2002
C
Designer: D S P D D e s i g n
D
A-3
Figure A-2. RESET, CLOCK, BOOT MODE & IRQs
Sheet 2
of
E
10
1.4
A-4
A
B
C
D
128Kx16-bit Program Memory (CS0)
E
128Kx16-bit Data Memory (CS1/CS2)
U2
DSP56852EVM User’s Manual
Freescale Semiconductor, Inc...
4
3
+3.3V
R60
10K
JG2
/CS0
1
/ECS0
2
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
5
4
3
2
1
44
43
42
27
26
25
24
21
20
19
18
22
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
/RD
/WR
41
17
6
39
40
OE
WE
CE
LB
UB
U3
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
7
8
9
10
13
14
15
16
29
30
31
32
35
36
37
38
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
VDD
VDD
11
33
+3.3V
VSS
VSS
12
34
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
JG1
/CS1
/CS2
1
3
2
4
41
17
6
/ E C S 1 39
/ E C S 2 40
OE
WE
CE
LB
UB
+3.3V
CS0 ENABLE JUMPER
/ECS1
JG2
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
7
8
9
10
13
14
15
16
29
30
31
32
35
36
37
38
VDD
VDD
11
33
VSS
VSS
12
34
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
4
+3.3V
3
GS72116ATP-7
R65
1K
R63
1K
OPTION
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
/RD
/WR
GS72116ATP-7
R62
1K
5
4
3
2
1
44
43
42
27
26
25
24
21
20
19
18
22
CS1/CS2 ENABLE JUMPER
R61
JG1
OPTION
SRAM WORD ENABLE
1-2
3-4
SRAM UPPER BYTE ENABLE
NC
3-4
SRAM LOWER BYTE ENABLE
1-2
NC
NC
NC
10K
2
2
SRAM ENABLE
1-2
/ECS2
SRAM DISABLE
R64
10K
NC
SRAM DISABLE
DSP Standard Products Division
2100 East Elliot Road
Tempe, Arizona 85284
(480) 413-5090
FAX: (480) 413-2510
1
1
Title
Size
MOTOROLA
A
A
B
P R O G RAM [WORD] (CS0) and DATA [BYTE] (CS1/CS2) SRAM MEMORY
Document
Number
Rev.
DSP56852EVM.DSN
Date: Sunday, October 06, 2002
C
Designer: DSPD Design
Sheet 3
D
Figure A-3. Program [Word] (CS0) & Data [Byte] (CS1/CS2) SRAM Memory
of
E
10
1.4
MOTOROLA
A
B
C
D
E
DSP56852EVM Schematics
3
2
1
4
Freescale Semiconductor, Inc...
4
+3.3V
U4
JG6
/SS
1
MISO
2
3
MOSI
4
5
SCK
6
7
8
/EE_CS
4
CS
VCC
6
EE_SO
8
SO
RESET
3
/RST
EE_SI
1
WP
5
/WP
EE_SCK
2
GND
7
SI
SCK
3
AT45DB011B-SC
EEPROM Enable
+3.3V
R58
10K
R59
10K
/RST
2
/WP
DSP Standard Products Division
2100 East Elliot Road
Tempe, Arizona 85284
(480) 413-5090
FAX: (480) 413-2510
1
Title
Size
A
A
B
SPI Serial 1M E E P R O M M E M O R Y
Document
Number
Rev.
DSP56852EVM.DSN
Date: Thursday, January 10, 2002
C
Designer: D S P D D e s i g n
D
A-5
Figure A-4. SPI Serial 1M-bit Serial EEPROM Memory
Sheet 4
of
E
10
1.4
A-6
A
B
C
D
E
+3.3V
U6
4
Freescale Semiconductor, Inc...
DSP56852EVM User’s Manual
3
28
C26
1.0 uF
C29
1.0 uF
1
3
2
4
TX
RX
+3.3V
V-
3
C27
1.0 uF
V+
27
C28
1.0 uF
GND
25
C1C2+
C2-
4
26
P6
1
6
2
7
3
8
4
9
5
T2IN
T3IN
14
13
12
T1IN
T2IN
T3IN
R2OUTB
R1OUT
R2OUT
R3OUT
R4OUT
R5OUT
FORCEON
T4
1
T5
T6
T7
T8
1
1
1
1
20
19
18
17
16
15
/EN
23
R52
1K
22
T1OUT
T2OUT
T3OUT
R1IN
R2IN
R3IN
R4IN
R5IN
INVALID
9
10
11
4
5
6
7
8
21
1
1
T2
T3
R2IN
R3IN
R4IN
R5IN
1
DCD
DSR
TXD
CTS
RXD
RTS
DTR
RI
GND
+3.3V
SCI
RS-232
CONNECTOR
T1
FORCEOFF
/EN
R50
1K
T2IN
R51
1K
T3IN
R53
1K
3
MAX3245EEAI
RS-232 ENABLE
RS-232 DISABLE
1
2
VCC
JG5
TXD
RXD
RS-232 ENABLE
2
24
1
C1+
N/C
1 - 2
JG8
R54
R2IN
1
2
1K
R3IN
R55
1K
R4IN
R56
1K
R5IN
R57
2
1K
DSP Standard Products Division
2100 East Elliot Road
Tempe, Arizona 85284
(480) 413-5090
FAX: (480) 413-2510
1
Title
Size
MOTOROLA
A
A
B
SCI PORT, RS-232 AND CONNECTOR
Document
Number
Rev.
DSP56852EVM.DSN
Date: Thursday, January 10, 2002
C
Designer: D S P D D e s i g n
D
Figure A-5. SCI PORT, RS-232 and Connector
Sheet 5
of
E
10
1.4
B
R19
5.62K
1%
P3
4
Freescale Semiconductor, Inc...
DSP56852EVM Schematics
1
R20
5.62K
1%
+3.3V
/PDN
R21
MODE1
R22
MODE2
R24
C9
4 7 0pF
10K
U5
TIP_IN
19
R23
5.62K
1%
1/8"
2
E
RING_IN
Line-Input
Stereo Jack
3
D
C11
4 7 0pF
LOUT
C13
0.33uF
R25
21
5.62K
1%
C16
0.47uF
C17
0.47uF
C18
0.47uF
U11
R32
1
+ 3 .3V
1K
4
20
RIN2
22
LIN2
EN OUT
1 2 .288MHZ
/ C O D E C _ R E SET
/PDN
CODEC_FSYNC
C O D E C _ S C LK
C O D E C _ S D O UT
CODEC_SDIN
1K
GND
1 2 . 2 8 8 M HZ OSC
+5.0VA
41
40
7
39
38
37
36
18
17
L O UT
MF5
MF4
MF3
MF2
MF1
32
30
29
33
34
MF5
/CCS
CCLK
CDIN
MF1
WF6
WF7
WF8
28
25
24
MF6
MF7
MF8
P4
RING_OUT
TIP_OUT
C12
1uF
25V
C14
0.0022uF
C15
0.0022uF
R27
3 9 .2K
1%
10K
3
11
10
2
1
R28
39.2K
1%
CLKIN
RESET
PDN
SSYNC
SCLK
SDOUT
SDIN
SWODE3
SWODE2
SWODE1
35
26
23
REFBY
15
MODE3
16
VDDA
VDD
42
GNDA
GND
43
R26
10K
1/8"
MF6
R29
10K
MF7
R30
10K
MODE3
MODE2
MODE1
R31
10K
/CCS
R34
3
10K
+
C20
0.1uF
REFGND
4
10K
Line Out
Stereo Jack
MF8
12.288MHZ
R33
10
C10
1uF
25V
ROUT
REFBUF
VCC
5
9
LIN1
14
+ 3 .3V
8
ROUT
RIN1
C19
4 7 uF
10VDC
MF5
R35
10K
+3.3V
SHUTDN R36
R37
10K
C S 4218-KQ
2 0 .0K 1%
MF1
R38
10K
R39
JG9
STXD
S R XD
SCK
/SS
MISO
STCK
STFS
PC4
1
3
5
7
9
CODEC_SDIN
C O D E C _ S D O UT
C O D E C _ S C LK
CODEC_FSYNC
/ C O D E C _ R E SET
2
4
6
8
10
2 0 .0K 1%
C21
PC5
PE0
PE1
1
3
5
S4
/CCS
CDIN
CCLK
2
4
6
MF6
MF7
MF8
6
4
2
FS (KHZ)
0
0
48.00
0
1
32.00
0
1
0
24.00
0
1
1
19.20
0 Ohm
1
0
0
16.00
R68
1
0
1
12.00
1
1
0
9.60
1
1
1
8.00
M O D E1
0 Ohm
R67
0 Ohm
M O D E2
M O D E3
DNP
Mode Select
MF6
MF7
0
0
1uF
25V
20.0K
1%
C23
R44
1uF
25V
MF8
SERIAL MODE 4 SELECTED
MASTER, 32BITS PER FRAME
6
20.0K
1%
C25
1uF
25V
7
RING_PHN
IN_A
BYPASS
3
BYPASS
SHUTDN
5
SHUTDN
OUT_A
1
VDD
8
GND
4
+5.0VA
TIP_PHN
3
11
10
2
1
2
Headphone Out
Stereo Jack
1/8"
C24
4 7 uF
10VDC
LM4880M
DSP Standard Products Division
2100 East Elliot Road
Tempe, Arizona 85284
(480) 413-5090
Title
B
B
OUT_B
2
Size
A
IN_B
C22
4 7 uF
10VDC
LOUT
5
3
1
Sample Select
R66
P5
ROUT
J G 10
MOSI
RXD
TXD
U12
R42
+
3
11
10
2
1
C
C8
0.33uF
+
MOTOROLA
A
1
FAX: (480) 413-2510
SSI 16-BIT STEREO CODEC
Document
Number
Date: Thursday, January 10, 2002
C
A-7
Figure A-6. SSI 16-Bit Stereo Codec
Rev.
DSP56852EVM.DSN
D
Designer: DSPD Design
Sheet 6
E
of
10
1.4
A-8
A
B
C
D
E
Parallel JTAG Interface
4
4
R4
P O R T _ I DENT
2
1
Freescale Semiconductor, Inc...
R5
1
14
2
15
3
PORT_TMS
4
P O RT_TCK
16
17
5
P O R T _ TDI
6
/ P O RT_TRST
18
U9
270
P O RT_RESET
2
1A1
1Y1
18
P_RESET
4
1A2
1Y2
16
TMS
6
1A3
1Y3
14
TCK
8
1A4
1Y4
12
TDI
11
2A1
2Y1
9
/J_TRST
7
2Y2
2A2
13
5
2Y3
2A3
15
TDO
2A4
17
+3.3V
R6
270
R7
270
19
R8
7
T9
P O R T _DE
20
1
270
8
21
9
3
P O R T _ VCC
22
24
20
1
19
51 Oh m
12
25
47K
3
R48
VCC
1G
2G
5.1K
GND
10
R11
P O R T _ C O N NECT
13
R78
TMS
R9
5.1K
/DE
R10
P O RT_TDO
11
47K
P _ DE
+ 3 .3V
10
23
2Y4
+3.3V
R17
TDO
2
1
DSP56852EVM User’s Manual
3
270
P1
JG7
51 Oh m
R12
5.1K
DB25M
MC74LCX244D W
R83
TCK
47K
On-Board
Host Target Interface
Disable
R84
TDI
47K
/J_TRST
R18
47K
+3.3V
R13
5.1K
2
U10A
/ J _ R E SET
/ J _ R E SET
U 1 0B
1
J3
4
3
/POR
R14
P_RESET
2
Q1
2N2222A
5.1K
R15
47K
5
/RESET
/DE
+ 3 .3V
7 4 AC00
7 4 AC00
U10C
U10D
9
/J_TRST
6
TCK
TDO
TDI
12
8
10
11
13
7 4 AC00
/ J _ R E SET
/TRST
13
11
9
7
5
3
1
14
12
10
8
6
4
2
/J_TRST
TMS
KEY
JTAG Connector
7 4 AC00
DSP Standard Products Division
2100 East Elliot Road
Tempe, Arizona 85284
C
(480) 413-5090
1
FAX: (480) 413-2510
2N2222A
Title
MOTOROLA
B
E
Size
B
A
B
C
PARALLEL JTAG HOST TARGET INTERFACE AND JTAG CONNECTOR
Document
Number
Rev.
DSP56852EVM.DSN
Date: Thursday, January 10, 2002
Designer: DSPD Design
D
Figure A-7. Parallel JTAG Host Target Interface and JTAG Connector
Sheet 7
E
of
10
1.4
MOTOROLA
A
B
C
D
E
DSP56852EVM Schematics
3
2
1
4
Freescale Semiconductor, Inc...
4
J1
GND
GND
/PS
GND
GND
A10
A9
A8
A7
A20
/WR
D0
D1
D2
GND
D3
D4
D5
D6
A18
D7
/CS0
A0
A1
A16
A2
A3
A19
/CS3
+3.3V
+5.0V
GND
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
J2
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
A11
/CS1
A15
A14
A19
A13
A12
D8
D9
GND
D10
D11
D12
D13
A17
D14
D15
/RD
A6
GND
A5
A4
/CS2
PB0
CLKO
GND
/DS
PA0
/CS0
A20
A17
PB3
GND
PB5
SRXD
MOSI
SCK
SRFS
SCLK
GND
MOSI
MISO
GND
SRCK
STFS
GND
/SS
MISO
/SS
/RESET
STCK
GND
GND
STXD
SCK
/IRQB
/IRQA
+3.3V
GND
TIO0
GND
GND
GND
GND
+3.3V
GND
+5.0V
Daughter Address/Data Connector
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
PA1
PA2
TIO1
GND
GND
GND
GND
PA0
PA1
PA2
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
/CS1
/CS2
A18
PB4
PB1
PB2
GND
PB6
/CS0
/CS1
/CS2
PB7
PD0
PD1
PD2
PD3
3
PD4
PD5
PD6
PD7
RXD1
TXD1
RXD
TXD
+3.3V
GND
Daughter Peripheral Port Connector
2
GND
DSP Standard Products Division
2100 East Elliot Road
Tempe, Arizona 85284
(480) 413-5090
FAX: (480) 413-2510
1
Title
Size
A
A
B
D A U G H T E R CARD EXPANSION CONNECTORS
Document
Number
Rev.
DSP56852EVM.DSN
Date: Thursday, January 10, 2002
C
Designer: D S P D D e s i g n
D
A-9
Figure A-8. Daughter Card Expansion Connectors
Sheet 8
of
E
10
1.4
A-10
A
B
C
EXTERNAL POWER INPUT
7-12VDC/AC
D
D3
D1
FM4001
FM4001
E
P2
1
3
2
4
4
D4
DSP56852EVM User’s Manual
3
+5VDC
INPUT
2 -
+ 1
3
+ C1
470uF
16VDC
1
GND
+5.0V
VOUT
2
VOUT
4
U7
3
C2
0.1uF
1
VIN
GND
VOUT
2
VOUT
4
VCC
L1
+3.3V
FERRITE BEAD
MC33269DT-5
+
MC33269DT-3.3
C3
47uF
10VDC
D2
TB1
+
-
3
FM4001
+5.0V
1
2
U8
C4
0.1uF
3
VIN
VOUT
2
1
GND
VOUT
4
L2
+1.8V
FERRITE BEAD
L3
MC33269DT-ADJ
+5.0V
2
VIN
1
4
Freescale Semiconductor, Inc...
3
U13
+5.0VA
FERRITE BEAD
+
R1
243
1%
C5
47uF
10VDC
Rhigh
C6
0.1uF
L4
C7
47uF
10VDC
FERRITE BEAD
+
R2
107
1%
Vout = 1.25( 1 + (Rlow/Rhigh))
2
Rlow = 107 1% for 1.8V
Rlow = 243 1% for 2.5V
Rlow = 127 1% for 1.9V
Rlow
+3.3V
R3
270
5.0V, 3.3V
& Adj
REGULATOR
DSP Standard Products Division
2100 East Elliot Road
Tempe, Arizona 85284
4
(480) 413-5090
LED7
1
MOTOROLA
POWER GOOD LED
A
2
FAX: (480) 413-2510
1
3
Title
Size
MC33269
A
B
P O W ER SUPPLIES
Document
Number
Rev.
DSP56F852EVM.DSN
Date: Thursday, January 10, 2002
C
Figure A-9. Power Supplies
Designer: D S P D D e s i g n
D
Sheet 9
of
E
10
1.4
MOTOROLA
A
B
C
D
E
DSP56852
+3.3V
+3.3V
C33
0.01uF
C34
0.1uF
C37
0.01uF
GS72116
+1.8V
C38
0.1uF
+1.8V
C39
0.01uF
+1.8V
C40
0.1uF
+1.8V
C41
0.01uF
+3.3V
C42
0.1uF
+3.3V
C43
0.01uF
C44
0.1uF
4
C46
0.1uF
CS4218
+3.3V
C47
0.01uF
OSC
74AC04
+3.3V
C48
0.1uF
+3.3V
C49
0.01uF
DS1818
+3.3V
C50
0.1uF
+3.3V
C51
0.1uF
+3.3V
C56
0.1uF
74LCX244
+3.3V
C52
0.01uF
ANALOG GROUND
TEST POINT
+5.0VA
+3.3V
C53
0.1uF
C54
0.1uF
3
C57
0.01uF
+3.3V
GROUND
TEST POINT
TP1
C55
0.01uF
MAX3245
LM4880
+5.0VA
+3.3V
74AC00
TP3
1
DSP56852EVM Schematics
C45
0.01uF
+3.3V
AT45DB011
+1.8V
DNP
1
1
+3.3V
+3.3V
1
C36
0.1uF
+3.3V
1
+3.3V
2
C35
0.01uF
+3.3V
Near VDDA
GS72116
3
+3.3V
1
Freescale Semiconductor, Inc...
4
+3.3V
C58
0.1uF
TP6
TP2
TP7
+5.0VA
TEST POINT
1
TP4
TP5
1
+3.3V
TEST POINT
+1.8V
TEST POINT
2
DSP Standard Products Division
2100 East Elliot Road
Tempe, Arizona 85284
(480) 413-5090
FAX: (480) 413-2510
1
Title
Size
A
A
B
BYPASS CAPS
Document
Number
Rev.
DSP56852EVM.DSN
Date: Thursday, January 10, 2002
C
A-11
Figure A-10. Bypass Caps
Designer: D S P D D e s i g n
D
Sheet 1 0
of
E
10
1.4
Freescale Semiconductor, Inc...
Freescale Semiconductor, Inc.
A-12
DSP56852EVM User’s Manual
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MOTOROLA
Freescale Semiconductor, Inc.
Appendix B
DSP56852EVM Bill of Material
Freescale Semiconductor, Inc...
Qty
Description
Ref. Designators
Vendor Part #
Integrated Circuits
1
DSP56852
U1
2
GS72116
1
AT45DB011
U4
Atmel, AT45DB011B-SC
1
CS4218
U5
Crystal Semiconductor, CS4218-KQ
1
MAX3245
U6
Maxim, MAX3245EEAI
1
+3.3V Voltage Regulator
U7
ON Semiconductor, MC33269DT-3.3
1
+1.8V Voltage Regulator
U8
ON Semiconductor, MC33269DT-ADJ
1
74LCX244
U9
ON Semiconductor, MC74LCX244ADW
1
74AC00
U10
Fairchild, 74AC00SC
1
12.288MHz OSC
U11
Epson, SG-531P-12.288MC
1
LM4880
U12
National Semiconductor, LM4880M
1
+5.0V Voltage Regulator
U13
ON Semiconductor, MC33269DT-5
1
74AC04
U14
ON Semiconductor, MC74AC04AD
1
DS1818
U16
Dallas Semiconductor, DS1818
U2, U3
Motorola, DSP56852VF120
GSI, GS72116ATP-7
Resistors
1
243 Ω, 1%
R1
SMEC, RC73L243OHMFT
1
107 Ω, 1%
R2
SMEC, RC73L107OHMFT
12
270 Ω
R3 - R8, R72 - R77
SMEC, RC73L2A270OHMJT
2
51 Ω
R10, R11
SMEC, RC73L2A51OHMJT
5
5.1K Ω
R9, R12 - R14, R48
SMEC, RC73L2A5.1KOHMJT
6
47K Ω
R15, R17, R18, R78, R83, R84
SMEC, RC73L2A47KOHMJT
MOTOROLA
DSP56852EVM Bill of Material
For More Information On This Product,
Go to: www.freescale.com
B-1
Freescale Semiconductor, Inc.
Freescale Semiconductor, Inc...
Qty
Description
Ref. Designators
Vendor Part #
1
10M Ω
4
5.62K Ω, 1%
23
10K Ω
2
39.2K Ω, 1%
13
1K Ω
4
20.0K Ω, 1%
3
470K Ω
R41, R43, R86
SMEC, RC73L2A470KOHMJT
0
10K Ω
R45
SMEC, RC73L2A10KOHMJT
2
0Ω
R66, R67
SMEC, RC73JP2A
0
0Ω
R68
SMEC, RC73JP2A
R16
R19, R20, R23, R25
R21, R22, R24, R26, R29 - R31,
R34-R36, R38, R58-R61, R64,
R70, R71, R79 - R82, R85
R27, R28
SMEC, RC73L2A10MOHMJT
SMEC, RC73L2A5.62KOHMFT
SMEC, RC73L2A10KOHMJT
SMEC, RC73L2A39.2KOHMFT
R32, R33, R50-R57, R62, R63,
R65
SMEC, RC73L2A1KOHMJT
R37, R39, R42, R44
SMEC, RC73L20.0KOHMFT
Inductors
4
1.0mH FERRITE BEAD
L1 - L4
Panasonic, EXC-ELSA35V
LEDs
2
Red LED
LED1, LED4
Hewlett-Packard, HSMS-C650
2
Yellow LED
LED2, LED5
Hewlett-Packard, HSMY-C650
3
Green LED
LED3, LED6, LED7
Hewlett-Packard, HSMG-C650
Diode
1
S2B-FM401
D1
Vishay, DL4001DICT
1
+50V 1A BRIDGE RECT
D2
DIODES, DF02S
B-2
DSP56852EVM User’s Manual
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MOTOROLA
Freescale Semiconductor, Inc.
Qty
Description
Ref. Designators
Vendor Part #
Freescale Semiconductor, Inc...
Capacitors
1
470µF, +16V DC
C1
ELMA, RV-16V471MH10R
21
0.1µF
C2, C4, C6, C20, C30 - C32,
C34, C36, C38, C40, C42, C44,
C46, C48, C50, C51, C53, C54,
C56, C58
SMEC, MCCE104K2NR-T1
6
47µF, +16V DC
2
0.33µF
C8, C13
SMEC, MCCE334K3NR-T1
2
470pF
C9, C11
SMEC, MCCE471J2NO-T1
9
1.0µF, +25V DC
C10, C12, C21, C23, C25 - C29
SMEC, MCCE105K3NR-T1
2
0.0022µF
C14, C15
SMEC, MCCE222K2NR-T1
3
0.47µF
C16 - C18
SMEC, MCCE474K3NR-T1
12
0.01µF
C33, C35, C37, C39, C41, C43,
C45, C47, C49, C52, C55, C57
SMEC, MCCE103K2NR-T1
C3, C5, C7, C19, C22, C24
ELMA, RV2-16V470M-R
Jumpers
3
1 × 2, 2mm Header
JG2, JG7, JG8
SAMTEC, TMM-102-02-S-S
2
3 × 1, 2mm Header
JG3, JG4
SAMTEC, TMM-103-02-S-S
1
4 × 2, 2mm Header
JG6
SAMTEC, TMM-104-02-S-D
2
2 x 2, 2mm Header
JG1, JG5
SAMTEC, TMM-102-02-S-D
1
5 x 2, 2mm Header
JG9
SAMTEC, TMM-105-02-S-D
1
3 x 2, 2mm Header
JG10
SAMTEC, TMM-103-02-S-D
Test Points
4
Black Test Point
TP1, TP3, TP6, TP7
Keystone, 5001
1
Red Test Point
TP2
Keystone, 5000
1
White Test Point
TP4
Keystone, 5002
1
Yellow Test Point
TP5
Keystone, 5004
Crystals
1
MOTOROLA
4.00MHz Crystal
Y1
CTS, ATS04ASM-T
DSP56852EVM Bill of Material
For More Information On This Product,
Go to: www.freescale.com
B-3
Freescale Semiconductor, Inc.
Freescale Semiconductor, Inc...
Connectors
1
DB25M Connector
P1
AMPHENOL, 617-C025P-AJ121
1
2.1mm coax
Power Connector
P2
Switchcraft, RAPC-722
3
1/8” Stereo Jack
P3 - P5
1
DE9S Connector
P6
2
51-Pin HD Connector
1
7 x 2 Bergstick
1
2-Pin Terminal Block
J1, J2
J3
TB1
Switchcraft, 35RAPC4BHN2
AMPHENOL, 617-C009S-AJ120
BERG, 91930-21151
SAMTEC, TSW-107-07-S-D
On-Shore Technology, ED500/2DS
Switches
3
SPST Pushbutton
S1 - S3
Panasonic, EVQ-PAD05R
2
3-Position DIP SW
S4, S5
CTS, 209-3LPST
Transistors
1
2N2222A
Q1
ZETEX, FMMT2222ACT
Miscellaneous
B-4
19
2mm Shunt
SH1 - SH19
4
Rubber Feet
RF1 - RF4
Samtec, 2SN-BK-G
3M, SJ5018BLKC
DSP56852EVM User’s Manual
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MOTOROLA
Freescale Semiconductor, Inc.
Freescale Semiconductor, Inc...
Index
C
H
Clock Source 2-7
Codec viii
Codec sample rate selector 2-1
Connecting the DSP56852EVM Cables 1-4
Connectors
Memory Daughter Card Expansion 2-18
Host Parallel Interface Connector 2-9
Host Target Interface 2-9
D
I
IC ix
ISSI ix
J
Daughter Card Connectors 2-18
Daughter Card Expansion interface 2-1
Debugging 2-8
DSP viii
DSP56852EVM
1 M-bit Serial EEPROM/Data FLASH 2-1
12.0V DC power supply 2-14
128Kx16-bit of data memory (U3) 2-1
128Kx16-bit of memory (U2) 2-1
16-bit 1.8V/3.3V Digital Signal Processor 2-1
16-bit stereo codec interface 2-1
4.00MHz crystal oscillator 2-1
external oscillator frequency input 2-1
FSRAM 2-1
ISSI compatible peripheral 2-2
JTAG port interface 2-1
On-board power regulation 2-2
Parallel JTAG Host Target Interface 2-1
real-time debugging 2-8
RS-232 interface 2-1
SCI compatible peripheral 2-2
test points 2-20
JTAG ix, 1-1, 2-1
connector 2-10
Jumper Group 1-3
JG1 1-3
JG10 1-3
JG2 1-3
JG3 1-3
JG4 1-3
JG5 1-3
JG6 1-3
JG7 1-3
JG8 1-3
JG9 1-3
L
LED ix
M
MBGA ix
MPIO ix
E
O
EEPROM viii
EOnCE viii
EVM ix
Operating Mode 2-7
F
PCB ix
PLL ix
P
FSRAM 2-3
G
GPIO ix, 2-2
MOTOROLA
R
RAM ix
ROM ix
RS-232
Index
For More Information On This Product,
Go to: www.freescale.com
1
Freescale Semiconductor, Inc.
interface 2-1, 2-6
level converter 2-6
schematic diagram 2-6
RS-232 Serial Communications 2-6
Freescale Semiconductor, Inc...
S
SCI ix
SPI ix, 2-2
SRAM ix
external data 2-1
external program 2-1
SSI ix
stereo 16-bit codec interface 2-1
Stereo headphone interface 2-1
W
WS ix
2
DSP56852EVM User’s Manual
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Go to: www.freescale.com
MOTOROLA
Freescale Semiconductor, Inc...
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc...
Freescale Semiconductor, Inc.
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the
suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and
specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters which may be provided in Motorola
data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including
“Typicals” must be validated for each customer application by customer’s technical experts. Motorola does not convey any license under its patent rights nor the
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applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury
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and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees
arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that
Motorola was negligent regarding the design or manufacture of the part. Motorola and the Stylized M Logo are registered trademarks of Motorola, Inc. Motorola,
Inc. is an Equal Opportunity/Affirmative Action Employer.
MOTOROLA and the Stylized M Logo are registered in the US Patent & Trademark Office. All other product or service names are the property of their
respective owners. © Motorola, Inc. 2002.
How to reach us:
USA/EUROPE/Locations Not Listed: Motorola Literature Distribution; P.O. Box 5405, Denver, Colorado 80217. 1–303–675–2140 or 1–800–441–2447
JAPAN: Motorola Japan Ltd.; SPS, Technical Information Center, 3–20–1, Minami–Azabu. Minato–ku, Tokyo 106–8573 Japan. 81–3–3440–3569
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DSP56F852EVMUM/D