ETC DSP56652DS

MOTOROLA Freescale Semiconductor, Inc.
Order this document by:
DSP56652/D
Rev 1, 1/99
SEMICONDUCTOR TECHNICAL DATA
DSP56652
Advance Information
Motorola designed the ROM-based DSP56652 to support the rigorous demands of the cellular
subscriber market. The high level of on-chip integration in the DSP56652 minimizes application
system design complexity and component count, resulting in very compact implementations.
This integration also yields very low-power consumption and cost-effective system
performance. The DSP56652 chip combines the power of MotorolaÕs 32-bit M¥CORE (TM)
MicroRISC Engine (MCU) and the DSP56600 digital signal processor (DSP) core with on-chip
memory, protocol timer, and custom peripherals to provide a single-chip cellular base-band
processor. Figure 1 shows the basic block diagram of the DSP56652.
Timer/
PWM
External
Memory
RAM
512 x 32
ROM
4K x 32
Program
Interrupt Timer
Watch
Dog
Edge
I/O
Smart
Card
I/F
M¥CORE
MicroRISC
Core
Keypad
I/F
Queued
SPI
Clocks
MCU - DSP INTERFACE
DSP56652
X Data
RAM
(7+1)K x 16
X Data
ROM
10K x 16
Y Data
RAM
6K x 16
Y Data
ROM
10K x 16
Program
RAM
512 x 24
Program
ROM
48K x 24
UART
MESSAGING
UNIT
56600
DSP
Core
MUX
Serial
Audio
CODEC I/F
MCU
OnCE
DSP
OnCE
1K x 16
RAM
JTAG
DSP PLL
JTAG
Freescale Semiconductor, Inc...
INTEGRATED CELLULAR BASEBAND PROCESSOR
Protocol
Timer
Serial Audio
CODEC I/F
Baseband
CODEC I/F
AA1618
Figure 1-1 DSP56652 System Block Diagram
This document contains information on a new product. Specifications and information herein are subject to change without notice.
Preliminary
©1998 MOTOROLA, INC.
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Freescale Semiconductor, Inc.
DSP56652
Freescale Semiconductor, Inc...
TABLE OF CONTENTS
SECTION 1
PIN AND SIGNAL DESCRIPTIONS. . . . . . . . . . . . . . . . . . . . . . . . . . 1-1
SECTION 2
SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1
SECTION 3
PACKAGING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1
SECTION 4
DESIGN CONSIDERATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1
SECTION 5
ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1
FOR TECHNICAL ASSISTANCE:
Telephone:
1 (800) 521-6274
Email:
[email protected]
Internet:
http://www.motorola-dsp.com
Data Sheet Conventions
This data sheet uses the following conventions:
OVERBAR
Used to indicate a signal that is active when pulled low; for example, the RESET
pin is active when low
ÒassertedÓ
Means that a high true (active high) signal is high or that a low true (active low)
signal is low
ÒdeassertedÓ
Means that a high true (active high) signal is low or that a low true (active low)
signal is high
Examples:
Note:
Signal/Symbol
Logic State
Signal State
Voltage1
PIN
True
Asserted
VIL/VOL
PIN
False
Deasserted
VIH/VOH
PIN
True
Asserted
VIH/VOH
PIN
False
Deasserted
VIL/VOL
Values for VIL, VOL, VIH, and VOH are defined by individual product specifications.
Preliminary
ii
DSP56652 Technical Data Sheet
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Freescale Semiconductor, Inc.
DSP56652
Features
FEATURES
Freescale Semiconductor, Inc...
RISC M¥CORE MCU
¥
32-bit load/store RISC architecture
¥
Fixed 16-bit instruction length
¥
16-entry 32-bit general-purpose register file
¥
32-bit internal address and data buses
¥
Efficient four-stage, fully interlocked execution pipeline
¥
Single-cycle execution for most instructions, two cycles for branches and memory
accesses
¥
Special branch, byte, and bit manipulation instructions
¥
Support for byte, half-word, and word memory accesses
¥
Fast interrupt support via vectoring/auto-vectoring and a 16-entry dedicated
alternate register file
High Performance DSP56600 Core
¥
1 ´ engine (e.g., 70 MHz = 70 MIPS)
¥
Fully pipelined 16 ´ 16-bit parallel multiplier-accumulator (MAC)
¥
Two 40-bit accumulators including extension bits
¥
40-bit parallel barrel shifter
¥
Highly parallel instruction set with unique DSP addressing modes
¥
Position-independent code support
¥
Nested hardware DO loops
¥
Fast auto-return interrupts
¥
On-chip support for software patching and enhancements
¥
Realtime trace capability via address bus visibility mode
Preliminary
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DSP56652 Technical Data Sheet
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iii
Freescale Semiconductor, Inc.
DSP56652
Features
Freescale Semiconductor, Inc...
On-chip Memories
¥
4K ´ 32-bit MCU ROM
¥
512 ´ 32-bit MCU RAM
¥
48K ´ 24-bit DSP program ROM
¥
512 ´ 24-bit DSP program RAM
¥
20K ´ 16-bit DSP data ROM, split into 10K x 16-bit each of X and Y data ROM spaces
¥
14K ´ 16-bit DSP data RAM, split into (7 + 1)K ´ 16-bit X data RAM and 6K x 16-bit
Y data RAM spaces
On-chip Peripherals
¥
Fully programmable phase-locked loop (PLL) for DSP clock generation
¥
External interface module (EIM) for glueless system integration
¥
External 22-bit address and 16-bit data MCU buses
¥
Thirty-two source MCU interrupt controller
¥
Intelligent MCU/DSP interface (MDI) dual 1K x 16-bit RAM (shares 1K DSP X data
RAM) with messaging status and control
¥
Serial audio codec port
¥
Serial baseband codec port
¥
Protocol timer frees the MCU from radio channel timing events
¥
Queued serial peripheral interface (SPI)
¥
Keypad port capable of scanning up to an 8 ´ 8 matrix keypad
¥
General-purpose MCU and DSP timers
¥
Pulse width modulation output
¥
Universal asynchronous receiver/transmitter (UART) with FIFO
¥
IEEE 1149.1-compliant boundary scan JTAG Test access port (TAP)
¥
Integrated DSP/M¥CORE On-Chip Emulation (OnCEª) module
¥
DSP address bus visibility mode for system development
¥
ISO 7816-compatible Smart Card port
Preliminary
iv
DSP56652 Technical Data Sheet
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Freescale Semiconductor, Inc.
DSP56652
Target Applications
Freescale Semiconductor, Inc...
Operating Features:
¥
Comprehensive static and dynamic power management
¥
M¥CORE operating frequency: dc to 16.8 MHz at 1.8 V
¥
DSP operating frequency: dc to 58.8 MHz at 1.8 V
¥
Internal operating voltage range: 1.8Ð2.5 V with 3.3 V-tolerant I/O
¥
Operating temperature: Ð40û to 85ûC ambient
¥
Package option: 15 ´ 15 mm, 196-lead PBGA
TARGET APPLICATIONS
The DSP56652 is intended for use in cellular subscriber applications and other applications
needing both DSP and control processing.
PRODUCT DOCUMENTATION
The four manuals listed in Table 1 are required for a complete description of the DSP56652 and
are necessary to design with the part properly. Documentation is available from a local Motorola
distributor, a Motorola semiconductor sales office, a Motorola Literature Distribution Center, or
the World Wide Web.
Table 1 DSP56652 Documentation
Document Name
Description of Contents
Order Number
DSP56600
Family Manual
Detailed description of the DSP56600 family core processor DSP56600FM/AD
architecture and instruction set
M¥CORE Reference
Manual
Detailed description of the M¥CORE MCU and instruction MCORERM/AD
set
DSP56652
UserÕs Manual
Detailed description of DSP56652 memory, peripherals,
and interfaces
DSP56652UM/D
DSP56652
Technical Data
DSP56652 pin and package descriptions; electrical and
timing specifications
DSP56652/D
Preliminary
MOTOROLA
DSP56652 Technical Data Sheet
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DSP56652
Freescale Semiconductor, Inc...
Product Documentation
Preliminary
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DSP56652 Technical Data Sheet
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SECTION
1
PIN AND SIGNAL DESCRIPTIONS
Freescale Semiconductor, Inc...
INTRODUCTION
The pins and signals of the DSP56652 are described in the following sections.
Figure 1-1 and Figure 1-2 on page 1-3 are top and bottom views of the package,
respectively, showing the pin-outs. Subsequent tables list the pins by number and
signal name. Figure 1-3 on page 1-11 is a representational pin-out of the chip
grouping the signals by their function. Subsequent tables identify the signals of each
group.
DSP56652 PIN DESCRIPTION
The following section provides information about the available packages for this
product, including diagrams of the package pinouts and tables describing how the
signals of the DSP 56652 are allocated for the 196-pin Plastic ball grid array (PBGA)
package. Top and bottom views of the PBGA package are shown in Figure 1-1 and
Figure 1-2 on page 1-3 with their pin-outs, while Table 1-1 on page 1-4 identifies the
signal associated with each pin.
Preliminary
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1-1
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Pin and Signal Descriptions
DSP56652 Pin Description
PBGA Package Description
Freescale Semiconductor, Inc...
Top View
1
2
3
4
5
6
7
8
9
10
11
A
NC
A20
TOUT0
TOUT3
TOUT6
SPICS4
GNDH
VCCHQ
DSP_IRQ
SRDB
GNDE
B
GNDA
A18
A21
TOUT2
TOUT7
SPICS1
VCCQ
MOSI
SC2B
SC0A
C
VCCA
A17
A19
TOUT1
TOUT5
VCCH
GNDQ
SCKB
STDB
D
A13
A15
A16
A14
TOUT4
SPICS3
SCK
MISO
E
A8
A12
A11
A10
GND
SPICS2
SPICS0
F
VCCA
A7
A9
A6
A5
GND
G
A0
GNDA
A4
A3
A2
H
CKIH
EB1
A1
EB0
J
GNDF
VCCQ
VCCHQ
K
CKO
VCCF
L
CS0
M
12
13
14
SRDA
STDA
NC
SCKA
PSTAT2
PSTAT1
GNDK
SC1A
PSTAT3
VCCK
PSTAT0
SIZ1
SC1B
SC2A
VCCE
SIZ0
MUX_CTL
CTS
NC
SC0B
GND
RTS
RxD
TEST
TxD
GND
GND
GND
TDO
TCK
DSP_DE
TDI
TRST
GND
GND
GND
GND
MCU_DE
ROW7
VCCHQ
ROW6
TMS
CKIL
GND
GND
GND
GND
GNDG
VCCG
VCCQ
ROW4
ROW5
CKOH
GNDQ
GND
GND
GND
GND
GNDQ
ROW2
INT7
ROW1
ROW3
OE
R/W
GND
D12
PWR_EN
GNDB
VCCP
GND
INT6
INT5
INT4
ROW0
CS1
VCCC
D5
GNDD
D11
SIMCLK
VCCB
PCAP
RESET_
IN
VCCG
INT0
GNDG
INT3
GNDC
CS2
CS4
D1
VCCD
D8
D13
VCCQ
SIM
DATA
RESET_
OUT
COL1
COL5
COL7
INT2
N
CS3
CS5
D0
D4
D7
D10
D15
GNDQ
SIM
RESET
GNDP1
COL0
COL3
COL6
INT1
P
NC
D2
D3
D6
D9
D14
VCCHQ
SENSE
GNDP
MOD
STO
COL2
COL4
NC
AA1692
Figure 1-1 DSP56652 Plastic Ball Grid Array (PBGA), Top View
Preliminary
1-2
DSP56652 Technical Data Sheet
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DSP56652
DSP56652 Pin Description
Freescale Semiconductor, Inc...
Bottom View
14
13
12
11
10
9
8
7
NC
STDA
SRDA
GNDE
SRDB
DSP_IRQ
VCCHQ
GNDH
GNDK
PSTAT1
PSTAT2
SCKA
SC0A
SC2B
MOSI
SIZ1
PSTAT0
VCCK
PSTAT3
SC1A
STDB
CTS
MUX_CTL
SIZ0
VCCE
SC2A
TxD
TEST
RxD
RTS
TRST
TDI
DSP_DE
TMS
ROW6
ROW5
6
5
4
3
2
1
SPICS4
TOUT6
TOUT3
TOUT0
A20
NC
A
VCCQ
SPICS1
TOUT7
TOUT2
A21
A18
GNDA
B
SCKB
GNDQ
VCCH
TOUT5
TOUT1
A19
A17
VCCA
C
SC1B
MISO
SCK
SPICS3
TOUT4
A14
A16
A15
A13
D
GND
SC0B
NC
SPICS0
SPICS2
GND
A10
A11
A12
A8
E
TCK
TDO
GND
GND
GND
GND
A5
A6
A9
A7
VCCA
F
VCCHQ
ROW7
MCU_DE
GND
GND
GND
GND
A2
A3
A4
GNDA
A0
G
ROW4
VCCQ
VCCG
GNDG
GND
GND
GND
GND
CKIL
EB0
A1
EB1
CKIH
H
ROW3
ROW1
INT7
ROW2
GNDQ
GND
GND
GND
GND
GNDQ
CKOH
VCCHQ
VCCQ
GNDF
J
ROW0
INT4
INT5
INT6
GND
VCCP
GNDB
PWR_EN
D12
GND
R/W
OE
VCCF
CKO
K
INT3
GNDG
INT0
VCCG
RESET_
IN
PCAP
VCCB
SIMCLK
D11
GNDD
D5
VCCC
CS1
CS0
L
INT2
COL7
COL5
COL1
RESET_
OUT
SIM
DATA
VCCQ
D13
D8
VCCD
D1
CS4
CS2
GNDC
M
INT1
COL6
COL3
COL0
GNDP1
SIM
RESET
GNDQ
D15
D10
D7
D4
D0
CS5
CS3
N
NC
COL4
COL2
STO
MOD
GNDP
SENSE
VCCHQ
D14
D9
D6
D3
D2
NC
P
AA1693
Figure 1-2 DSP56652 Plastic Ball Grid Array (PBGA), Bottom View
Preliminary
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1-3
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Pin and Signal Descriptions
DSP56652 Pin Description
Table 1-1 DSP56652 PBGA Signal Identification by Pin Number
Freescale Semiconductor, Inc...
Pin
No.
Signal Name
Pin
No.
Signal Name
Pin
No.
Signal Name
A1
Not Connected (NC),
reserved
B12
PSTAT2
D9
SC1B
A2
A20
B13
PSTAT1
D10
SC2A
A3
TOUT0
B14
GNDK
D11
VCCE
A4
TOUT3
C1
VCCA
D12
SIZ0
A5
TOUT6
C2
A17
D13
MUX_CTL
A6
SPICS4
C3
A19
D14
CTS
A7
GNDH
C4
TOUT1
E1
A8
A8
VCCHQ
C5
TOUT5
E2
A12
A9
DSP_IRQ
C6
VCCH
E3
A11
A10
SRDB
C7
GNDQ
E4
A10
A11
GNDE
C8
SCKB
E5
GND
A12
SRDA
C9
STDB
E6
SPICS2
A13
STDA
C10
SC1A
E7
SPICS0
A14
NC
C11
PSTAT3
E8
NC
B1
GNDA
C12
VCCK
E9
SC0B
B2
A18
C13
PSTAT0
E10
GND
B3
A21
C14
SIZ1
E11
RTS
B4
TOUT2
D1
A13
E12
RxD
B5
TOUT7
D2
A15
E13
TEST
B6
SPICS1
D3
A16
E14
TxD
B7
VCCQ
D4
A14
F1
VCCA
B8
MOSI
D5
TOUT4
F2
A7
B9
SC2B
D6
SPICS3
F3
A9
B10
SC0A
D7
SCK
F4
A6
B11
SCKA
D8
MISO
F5
A5
Preliminary
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DSP56652
DSP56652 Pin Description
Table 1-1 DSP56652 PBGA Signal Identification by Pin Number (Continued)
Freescale Semiconductor, Inc...
Pin
No.
Signal Name
Pin
No.
Signal Name
Pin
No.
Signal Name
F6
GND
H3
A1
J14
ROW3
F7
GND
H4
EB0
K1
CKO
F8
GND
H5
CKIL
K2
VCCF
F9
GND
H6
GND
K3
OE
F10
TDO
H7
GND
K4
R/W
F11
TCK
H8
GND
K5
GND
F12
DSP_DE
H9
GND
K6
D12
F13
TDI
H10
GNDG
K7
PWR_EN
F14
TRST
H11
VCCG
K8
GNDB
G1
A0
H12
VCCQ
K9
VCCP
G2
GNDA
H13
ROW4
K10
GND
G3
A4
H14
ROW5
K11
INT6
G4
A3
J1
GNDF
K12
INT5
G5
A2
J2
VCCQ
K13
INT4
G6
GND
J3
VCCHQ
K14
ROW0
G7
GND
J4
CKOH
L1
CS0
G8
GND
J5
GNDQ
L2
CS1
G9
GND
J6
GND
L3
VCCC
G10
MCU_DE
J7
GND
L4
D5
G11
ROW7
J8
GND
L5
GNDD
G12
VCCHQ
J9
GND
L6
D11
G13
ROW6
J10
GNDQ
L7
SIMCLK
G14
TMS
J11
ROW2
L8
VCCB
H1
CKIH
J12
INT7
L9
PCAP
H2
EB1
J13
ROW1
L10
RESET_IN
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Pin and Signal Descriptions
DSP56652 Pin Description
Table 1-1 DSP56652 PBGA Signal Identification by Pin Number (Continued)
Freescale Semiconductor, Inc...
Pin
No.
Signal Name
Pin
No.
Signal Name
Pin
No.
Signal Name
L11
VCCG
M13
COL7
P1
NC
L12
INT0
M14
INT2
P2
D2
L13
GNDG
N1
CS3
P3
D3
L14
INT3
N2
CS5
P4
D6
M1
GNDC
N3
D0
P5
D9
M2
CS2
N4
D4
P6
D14
M3
CS4
N5
D7
P7
VCCHQ
M4
D1
N6
D10
P8
SENSE
M5
VCCD
N7
D15
P9
GNDP
M6
D8
N8
GNDQ
P10
MOD
M7
D13
N9
SIMRESET
P11
STO
M8
VCCQ
N10
GNDP1
P12
COL2
M9
SIMDATA
N11
COL0
P13
COL4
M10
RESET_OUT
N12
COL3
P14
NC
M11
COL1
N13
COL6
M12
COL5
N14
INT1
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DSP56652 Pin Description
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Table 1-2 DSP56652 PBGA Signal Identification by Name
Signal Name
Pin
No.
Signal Name
Pin
No.
Signal Name
Pin
No.
A0
G1
CKOH
J4
D9
P5
A1
H3
COL0
N11
D10
N6
A2
G5
COL1
M11
D11
L6
A3
G4
COL2
P12
D12
K6
A4
G3
COL3
N12
D13
M7
A5
F5
COL4
P13
D14
P6
A6
F4
COL5
M12
D15
N7
A7
F2
COL6
N13
DSP_DE
F12
A8
E1
COL7
M13
DSP_IRQ
A9
A9
F3
CS0
L1
EB0
H4
A10
E4
CS1
L2
EB1
H2
A11
E3
CS2
M2
GND
E10
A12
E2
CS3
N1
GND
E5
A13
D1
CS4
M3
GND
F6
A14
D4
CS5
N2
GND
F7
A15
D2
CTS
D14
GND
F8
A16
D3
D0
N3
GND
F9
A17
C2
D1
M4
GND
G6
A18
B2
D2
P2
GND
G7
A19
C3
D3
P3
GND
G8
A20
A2
D4
N4
GND
G9
A21
B3
D5
L4
GND
H6
CKIH
H1
D6
P4
GND
H7
CKIL
H5
D7
N5
GND
H8
CKO
K1
D8
M6
GND
H9
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Pin and Signal Descriptions
DSP56652 Pin Description
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Table 1-2 DSP56652 PBGA Signal Identification by Name (Continued)
Signal Name
Pin
No.
Signal Name
Pin
No.
Signal Name
Pin
No.
GND
J6
INT2
M14
RESET_OUT
M10
GND
J7
INT3
L14
ROW0
K14
GND
J8
INT4
K13
ROW1
J13
GND
J9
INT5
K12
ROW2
J11
GND
K10
INT6
K11
ROW3
J14
GND
K5
INT7
J12
ROW4
H13
GNDA
B1
MCU_DE
G10
ROW5
H14
GNDA
G2
MISO
D8
ROW6
G13
GNDB
K8
MOD
P10
ROW7
G11
GNDC
M1
MOSI
B8
RTS
E11
GNDD
L5
MUX_CTL
D13
RxD
E12
GNDE
A11
NC
A1
SC0A
B10
GNDF
J1
NC
A14
SC0B
E9
GNDG
H10
NC
E8
SC1A
C10
GNDG
L13
NC
P1
SC1B
D9
GNDH
A7
NC
P14
SC2A
D10
GNDK
B14
OE
K3
SC2B
B9
GNDP
P9
PCAP
L9
SCK
D7
GNDP1
N10
PSTAT0
C13
SCKA
B11
GNDQ
C7
PSTAT1
B13
SCKB
C8
GNDQ
J10
PSTAT2
B12
SENSE
P8
GNDQ
J5
PSTAT3
C11
SIMCLK
L7
GNDQ
N8
PWR_EN
K7
SIMDATA
M9
INT0
L12
R/W
K4
SIMRESET
N9
INT1
N14
RESET_IN
L10
SIZ0
D12
Preliminary
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DSP56652
DSP56652 Pin Description
Freescale Semiconductor, Inc...
Table 1-2 DSP56652 PBGA Signal Identification by Name (Continued)
Signal Name
Pin
No.
Signal Name
Pin
No.
Signal Name
Pin
No.
SIZ1
C14
TOUT0
A3
VCCF
K2
SPICS0
E7
TOUT1
C4
VCCG
H11
SPICS1
B6
TOUT2
B4
VCCG
L11
SPICS2
E6
TOUT3
A4
VCCH
C6
SPICS3
D6
TOUT4
D5
VCCHQ
A8
SPICS4
A6
TOUT5
C5
VCCHQ
G12
SRDA
A12
TOUT6
A5
VCCHQ
J3
SRDB
A10
TOUT7
B5
VCCHQ
P7
STDA
A13
TRST
F14
VCCK
C12
STDB
C9
TxD
E14
VCCP
K9
STO
P11
VCCA
C1
VCCQ
B7
TCK
F11
VCCA
F1
VCCQ
J2
TDI
F13
VCCB
L8
VCCQ
H12
TDO
F10
VCCC
L3
VCCQ
M8
TEST
E13
VCCD
M5
TMS
G14
VCCE
D11
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Pin and Signal Descriptions
DSP56652 Signal Description
DSP56652 SIGNAL DESCRIPTION
DSP56652 signals are organized into 19 functional groups as summarized in
Table 1-3. Figure 1-3 is a diagram of DSP56652 signals by functional group.
Table 1-3 Signal Functional Group Allocations
Number
of Signals
Detailed
Description
Power (VCCX)
20
Table 1-4
Ground (GNDX)
17
Table 1-5
Substrate ground (GND)
20
Table 1-5
PLL and Clocks
5
Table 1-6
22
Table 1-7
16
Table 1-8
4
Table 1-9
Chip selects
6
Table 1-10
Reset, mode, and multiplexer control
5
Table 1-11
External interrupts
9
Table 1-12
Timers
8
Table 1-13
Keypad port
16
Table 1-14
Serial data port (UART)
4
Table 1-15
Serial control port (QSPI)
8
Table 1-16
Smart Card port (SIM)
5
Table 1-17
Serial audio codec port (SAP)
6
Table 1-18
Baseband codec port
6
Table 1-19
6
Table 1-20
2
Table 1-21
6
Table 1-22
Freescale Semiconductor, Inc...
Functional Group
Address bus
External
Interface
Module
(EIM)
Data bus
Bus control
Emulation port
Development and
Test
Debug control port
JTAG Test access port (TAP)
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DSP56652 Signal Description
Freescale Semiconductor, Inc...
DSP56652
VCCA
VCCB
VCCC
VCCD
VCCE
VCCF
VCCG
VCCH
VCCHQ
VCCK
VCCP
VCCQ
2
GNDA
GNDB
GNDC
GNDD
GNDE
GNDF
GNDG
GNDH
GNDK
GNDP
GNDP1
GNDQ
GND
CKIH
CKIL
CKO
CKOH
PCAP
2
2
4
4
2
4
20
A0-A21
D0-D15
R/W
EB0
EB1
OE
Chip
Selects
RESET_IN
RESET_OUT
MOD
MUX_CTL
STO
Power Inputs:
Address Bus
Smart Card
Bus Control
Data Bus
Audio Codec
Clock Output
GPIO/Keypad/Int/JTAG /UART/STO
Baseband Codec/Timers/QSPI
Quiet Power High
Emulation Port
PLL
Internal Logic (Quiet)
Interrupts
Grounds:
Address Bus
Smart Card
Bus Control
Data Bus
Audio Codec
Clock Output
GPIO/Keypad/Int/JTAG
Baseband Codec/Timers
Emulation Port
PLL
PLL
Internal Logic (Quiet)
Substrate Ground
Serial
Data Port
(UART)
PLL and
Clocks
Timers
6
INT0ÐINT5
INT6/STDA/DSR or TRST
INT7/SRDA/DTR/SCK or TMS
DSP_IRQ
8
TOUT0ÐTOUT7
6
Keypad
Port
Queued
Serial
Port
COL0ÐCOL5
COL6/OC1
COL7/PWM
ROW0ÐROW4
ROW5/IC2B
ROW6/SC2A/DCD or DSP_DE
ROW7/SCKA/RI or TCK
5
TxD or TDO
RxD/IC1 or TDI
RTS/IC2 or RESET_IN
CTS or MCU_DE
5
SPICS0ÐSPICS4
SCK
MISO
MOSI
SIMCLK
SENSE
SIMDATA
SIMRESET
PWR_EN
Smart
Card
Port
STDA
SRDA
SCKA
SC0AÐSC2A
Serial Audio
Codec Port
3
22
16
4
External Data Bus
Baseband
Codec
Port
External
Bus
Control
Emulation
Port
External Address Bus
CS0
CS1ÐCS4
CS5
Reset,
Mode, and
Multiplexer
Control
Debug Control
Port
STDB
SRDB
SCKB
SC0BÐSC2B
3
2
4
SIZ0ÐSIZ1
PSTAT0ÐPSTAT3
MCU_DE
DSP_DE
JTAG
Port
TCK
TDI
TDO
TMS
TRST
TEST
AA1691
Figure 1-3 Signals Identified by Functional Group
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Pin and Signal Descriptions
DSP56652 Signal Description
Power
Table 1-4 Power
Freescale Semiconductor, Inc...
Power Names
Description
VCCA
Address bus powerÑThese lines supply power to the address bus.
VCCB
Smart Card interface powerÑThis line supplies isolated power for Smart Card
interface I/O drivers.
VCCC
Bus control powerÑThis line supplies power to the bus control logic.
VCCD
Data bus powerÑThese lines supply power to the data bus.
VCCE
Audio codec port powerÑThis line supplies power to audio codec I/O drivers.
VCCF
Clock output powerÑThis line supplies a quiet power source for the CKOUT
output. Ensure that the input voltage to this line is well-regulated and uses an
extremely low impedance path to tie to the VCC power rail. Use a 0.1 mF bypass
capacitor located as close as possible to the chip package to connect between the
VCCF line and the GNDF line.
VCCG
GPIO powerÑThis line supplies power to the GPIO, keypad, data port, interrupts,
STO, and JTAG I/O drivers.
VCCH
Baseband codec and timer powerÑThis line supplies power to the baseband codec,
timer and QSPI I/O drivers.
VCCHQ
Quiet power highÑThese lines supply a quiet power source to the pre-driver
voltage converters. This value should be greater than or equal to the maximum
value of the power supplies of the chip I/O drivers (i.e., the maximum of VCCA,
VCCB, VCCC, VCCD, VCCE, VCCF, VCCG, VCCH, and VCCK).
VCCK
Emulation port powerÑThis line supplies power to the emulation port I/O drivers.
VCCP
Analog PLL circuit powerÑThis line is dedicated to the analog PLL circuits and
must remain noise-free to ensure stable PLL frequency and performance. Ensure
that the input voltage to this line is well-regulated and uses an extremely low
impedance path to tie to the VCC power rail. Use a 0.1 mF capacitor and a 0.01 mF
capacitor located as close as possible to the chip package to connect between the
VCCP line and the GNDP and GND P1 lines.
VCCQ
Quiet powerÑThese lines supply a quiet power source to the internal logic circuits.
Ensure that the input voltage to this line is well-regulated and uses an extremely low
impedance path to tie to the VCC power rail. Use a 0.1 mF bypass capacitor located as
close as possible to the chip package to connect between the VCCQ lines and the
GNDQ lines.
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DSP56652 Signal Description
Ground
Table 1-5 Ground
Freescale Semiconductor, Inc...
Ground Names
Description
GNDA
Address bus groundÑThese lines connect system ground to the address bus.
GNDB
Smart Card interface groundÑThese lines connect system ground to the Smart
Card bus.
GNDC
Bus control groundÑThis line connects ground to the bus control logic.
GNDD
Data bus groundÑThese lines connect system ground to the data bus.
GNDE
Audio codec port groundÑThese lines connect system ground to the audio codec
port.
GNDF
Clock output groundÑThis line supplies a quiet ground connection for the clock
output drivers. Ensure that this line connects through an extremely low impedance
path to ground. Use a 0.1 mF bypass capacitor located as close as possible to the chip
package to connect between the VCCF line and the GNDF line.
GNDG
GPIO groundÑThese lines connect system ground to GPIO, keypad, data port,
interrupts, STO, and JTAG I/O drivers.
GNDH
Baseband codec and timer groundÑThese lines connect system ground to the
baseband codec, timer and QSPI I/O drivers.
GNDK
Emulation port groundÑThese lines connect system ground to the emulation port
I/O drivers.
GNDP
Analog PLL circuit groundÑThis line supplies a dedicated quiet ground connection
for the analog PLL circuits and must remain relatively noise-free to ensure stable
PLL frequency and performance. Ensure that this line connects through an
extremely low impedance path to ground. Use a 0.1 mF capacitor and a 0.01 mF
capacitor located as close as possible to the chip package to connect between the
VCCP line and the GNDP line.
GNDP1
Analog PLL circuit groundÑThis line supplies a dedicated quiet ground connection
for the analog PLL circuits and must remain relatively noise-free to ensure stable
PLL frequency and performance. Ensure that this line connects through an
extremely low impedance path to ground. Use a 0.1 mF capacitor and a 0.01 mF
capacitor located as close as possible to the chip package to connect between the
VCCP line and the GNDP line.
GNDQ
Quiet groundÑThese lines supply a quiet ground connection for the internal logic
circuits. Ensure that this line connects through an extremely low impedance path to
ground. Use a 0.1 mF bypass capacitor located as close as possible to the chip
package to connect between the VCCQ line and the GNDQ line.
GND
Substrate groundÑThese lines must be tied to ground.
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Pin and Signal Descriptions
DSP56652 Signal Description
PLL and Clock
Table 1-6 PLL and Clock Signals
Freescale Semiconductor, Inc...
Signal
Name
Signal
Type
State
during
Reset
Signal Description
CKIH
Input
Input
High frequency clock inputÑThis signal provides the high frequency
input clock. This clock may be either a CMOS square wave or sinusoid
input.
CKIL
Input
Input
Low frequency clock inputÑThis signal provides the low frequency
input clock and should be less than or equal to the frequency of CKIH.
This is the default input clock after reset.
CKO
Output
Driven
low
DSP/MCU output clockÑThis signal provides an output clock
synchronized to the DSP or MCU core internal clock phases, according
the selected programming option. The choices of clock source and
enabling/disabling the output signal are software selectable.
CKOH
Output
Driven
low
High frequency clock outputÑThis signal provides an output clock
derived from the CKIH input. This signal can be enabled or disabled
by software.
PCAP
Input/
Output
Indeterminate
PLL capacitorÑThis signal is used to connect the required external
filter capacitor to the PLL filter. Connect one end of the capacitor to
PCAP and the other to VCCP. The value of the capacitor is specified in
Section 2 of this data sheet.
Address Bus
Table 1-7 Address Bus Signals
Signal
Names
A0ÐA21
Signal
Type
Output
State
during
Reset
Driven
low
Signal Description
Address busÑThese signals specify the address for external
memory accesses. If there is no external bus activity, A0ÐA21
remain at their previous values to reduce power consumption.
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DSP56652
DSP56652 Signal Description
Data Bus
Table 1-8 Data Bus Signals
Signal
Names
Freescale Semiconductor, Inc...
D0ÐD15
Signal
Type
Input/
Output
State
during
Reset
Input
Signal Description
Data busÑThese signals provide the bidirectional data bus for
external memory accesses. D0ÐD15 are held in the previous logic
state when there is no external bus activity and during hardware
reset. This is done with weak ÒkeepersÓ inside the I/O buffers.
Bus Control
Table 1-9 Bus Control Signals
Signal
Name
Signal
Type
State
during
Reset
Signal Description
R/W
Output
Driven
high
Read/writeÑThis signal indicates the bus access type. A high signal
indicates a bus read. A low signal indicates a write to the bus. When
accessing memory it can also be used as write enable (WE) signal. When
accessing a peripheral chip, the signal acts as a read/write.
EB0
Output
Driven
high
Enable byte 0ÑWhen driven low, this signal indicates access to data
byte 0 (D8ÐD15) during a read or write cycle. This pin may also act as a
write byte enable, if so programmed. This output is used when accessing
16-bit wide SRAM.
EB1
Output
Driven
high
Enable byte 1ÑWhen driven low, this signal indicates access to data
byte 1 (D0ÐD7) during a read or write cycle. This pin may also act as a
write byte enable, if so programmed. This output is used when accessing
16-bit wide SRAM.
OE
Output
Driven
high
Bus selectÑWhen driven low, this signal indicates that the current bus
access is a read cycle and enables slave devices to drive the data bus with
a read.
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Pin and Signal Descriptions
DSP56652 Signal Description
Chip Selects
Table 1-10 Chip Select Signals
Freescale Semiconductor, Inc...
Signal Name
Signal
Type
State
during
Reset
Signal Description
CS0
Output
Chipdriven
Chip select 0ÑThis signal is asserted low based on the decode of the
internal address bus bits A[31:24] and is typically used as the external
flash memory chip select. After reset, accesses using this CS have a
default of 15 wait states.
CS1ÐCS4
Output
Driven
high
Chip select 1Ðchip select 4ÑThese signals are asserted low based
on the decode of the internal address bus bits A[31:24] of the access
address.
When not selected as chip select signals, these signals become
general purpose outputs (GPOs). After reset, these signals are
GPOs that are driven high.
CS5
Output
Driven
low
Chip select 5ÑThis signal is asserted high based on the decode of
the internal address bus bits A[31:24] of the access address.
When not selected as a chip select signal, this signal becomes a
GPO. After reset, this signal is a GPO that is driven low.
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DSP56652
DSP56652 Signal Description
Reset, Mode, and Multiplexer Control
Table 1-11 Reset, Mode, and Multiplexer Control Signals
Freescale Semiconductor, Inc...
Signal Name
Signal
Type
State
during
Reset
Signal Description
RESET_IN
Input
Input
Reset inputÑThis signal is an active low Schmitt trigger input
that provides a reset signal to the internal circuitry. The input is
valid if it is asserted for at least three CKIL clock cycles.
This pin has a 47kW pull-up resistor.
Note: If MUX_CTL is held high, the RTS signal of the serial data
port (UART) becomes the RESET_IN input line.
(See Table 1-15 on page 1-26.)
RESET_OUT
Output
Pulled
low
Reset outputÑThis signal is asserted low for at least seven CKIL
clock cycles under one of the following conditions:
¥ RESET_IN is pulled low for at least three CKIL clock
cycles
¥
The alternate RESET_IN signal is enabled by MUX_CTL
and is pulled low for at least three CKIL clock cycles
¥
The watchdog count expires
This signal is asserted immediately after the qualifier detects a
valid RESET_IN signal, remains asserted during RESET_IN
assertion, and is stretched for at least seven more CKIL clock
cycles after RESET_IN is deasserted. Three CKIL clock cycles
before RESET_OUT is deasserted, the MCU boot mode is latched
from the MOD signal.
MOD
Input
Input
Mode selectÑThis signal selects the MCU boot mode during
hardware reset. If MOD is driven low at least four CKIL clock
cycles before RESET_OUT is deasserted, then the internal MCU
ROM ignores the first access and the M¥CORE fetches the first
word from the first location the external Flash memory. If MOD is
driven high four CKIL clock cycles before RESET_OUT
deassertion, then the internal MCU ROM is enabled and the
M¥CORE fetches the first word from the first location in the
internal ROM.
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Pin and Signal Descriptions
DSP56652 Signal Description
Table 1-11 Reset, Mode, and Multiplexer Control Signals (Continued)
Signal Name
Freescale Semiconductor, Inc...
MUX_CTL
Signal
Type
Input
State
during
Reset
Input
Signal Description
Multiplexer controlÑThis input allows the designer to select an
alternate set of pins to be used for RESET_IN, the debug control
port signals, and the JTAG signals as defined below:
Normal
Alternate
(MUX_CTL low)
(MUX_CTL high)
Interrupt signals INT6/STDA/DSR
TRST
(See Table 1-12) INT7/SRDA/DTR/SCLK
TMS
Keypad signals ROW6/SC2A/DCD
DSP_DE
(See Table 1-14 ROW7/SCKA/RI
TCK
on page 1-22)
Serial Data Port TxD
TDO
(UART) signals RxD/IC1
TDI
(See Table 1-15 RTS/IC2A
RESET_IN
on page 1-26) CTS
MCU_DE
If MUX_CTL is driven low, the normal functions are selected. If
MUX_CTL is driven high, the alternate functions are selection.
Note:
The user is responsible to ensure that transition between
normal and alternate functions are made smoothly. No
provisions are made in the on-chip hardware to assure
such a smooth switch. The external command converter
uses to drive this signal must ensure that critical pins
(such as the JTAG TMS and TRST signals and RESET_IN)
are driven with inactive values during and after the
switch.
The MUX_CTL signal has an internal 100 kW pull-down resistor.
STO
Output
Chip
driven
Soft turn offÑThis is a general purpose output pin. Its logic state
is not affected by reset.
For Reset, mode, and MUX control signals equipped with resistors, all pull-ups and
pull-downs are automatically disconnected when the pin is an output.
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DSP56652 Signal Description
Interrupts
Table 1-12 Interrupt Signals
Signal
Name
Freescale Semiconductor, Inc...
INT0ÐINT3
Signal
Type
State
during
Reset
Input or Input
Output
Signal Description
Interrupt 0Ðinterrupt 3ÑThese signals can be programmed as
interrupt inputs or GPIO signals. The signals have on-chip 100 kW
pull-up resistors.
As Schmitt trigger interrupt inputs the signals can be programmed
to be level sensitive, positive edge-triggered, or negative edgetriggered. When edge-triggered, triggering occurs at a voltage level
and is not directly related to the fall time of the interrupt signal;
however, as signal fall time of the interrupt signal increases, the
probability of generating multiple interrupts due to this noise also
increases.
The signals are GPIOs when not programmed as interrupts. After
reset, the default state for these signals is general purpose input
(GPI).
INT4ÐINT5
Input or Input
Output
Interrupt 4Ðinterrupt 5ÑThese signals can be programmed as
interrupt inputs or GPIO signals, and have 10-27kW pull-up
resistors.
As Schmitt trigger interrupt inputs, the signals can be programmed
to be level sensitive, positive edge-triggered, or negative edgetriggered. When edge-triggered, triggering occurs at a voltage level
and is not directly related to the fall time of the interrupt signal;
however, as signal fall time of the interrupt signal increases, the
probability of generating multiple interrupts due to this noise also
increases.
The signals are GPIOs when not programmed as interrupts. After
reset, the default state for these signals is GPI.
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Pin and Signal Descriptions
DSP56652 Signal Description
Table 1-12 Interrupt Signals (Continued)
Signal
Name
Signal
Type
State
during
Reset
Signal Description
Normal:
Freescale Semiconductor, Inc...
INT6
MUX_CTL driven low
Input or Input
Output
Interrupt 6ÑWhen selected, this signal can be programmed as an
interrupt input or a GPIO signal, and has a 47kW pull-up resistor.
As a Schmitt trigger interrupt input, the signal can be programmed
to be level sensitive, positive edge-triggered, or negative edgetriggered. When edge-triggered, triggering occurs at a voltage level
and is not directly related to the fall time of the interrupt signal;
however, as signal fall time of the interrupt signal increases, the
probability of generating multiple interrupts due to this noise also
increases.
STDA
Output
Audio codec serial transmit data (alternate)ÑWhen programmed
as STDA, this signal transmits data from the serial transmit shift
register in the serial audio codec port.
Note:
DSR
Output
When this signal is used as STDA, the primary STDA signal
is disabled. (See Table 1-18 on page 1-31.)
Data set readyÑWhen programmed as GPIO output, this signal can
be used as the DSR output for the serial data port. (See Table 1-15
on page 1-26)
The signal is a GPIO when not programmed as one of the above
functions. After reset, the default state for this signal is GPI.
Alternate:
TRST
MUX_CTL driven high
Input
Input
Test ResetÑWhen selected, this signal acts as the TRST input for the
JTAG TAP controller. The signal is a Schmitt trigger input that
asynchronously initializes the JTAG test controller when asserted.
Note:
When this signal is enabled, the primary TRST signal is
disconnected from the TAP controller. (See Table 1-22
on page 1-36.)
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DSP56652
DSP56652 Signal Description
Table 1-12 Interrupt Signals (Continued)
Signal
Name
Signal
Type
State
during
Reset
Signal Description
Normal:
Freescale Semiconductor, Inc...
INT7
MUX_CTL driven low
Input or Input
Output
Interrupt 7ÑWhen selected, this signal can be programmed as an
interrupt input or a GPIO signal, and has a 47kW pull-up resistor.
As a Schmitt trigger interrupt input, the signal can be programmed
to be level sensitive, positive edge-triggered, or negative edgetriggered. When edge-triggered, triggering occurs at a voltage level
and is not directly related to the fall time of the interrupt signal;
however, as signal fall time of the interrupt signal increases, the
probability of generating multiple interrupts due to this noise also
increases.
SRDA
Input
Audio codec serial receive data (alternate)ÑWhen programmed as
SRDA, this signal receives data into the serial receive shift register in
the serial audio codec port.
Note:
When this signal is used as SRDA, the primary SRDA signal
is disabled. (See Table 1-18 on page 1-31.)
DTR
Input
Data terminal readyÑWhen programmed as GPIO, this signal is
used as the DTR positive and negative edge-triggered interrupt
input for the serial data port. (See Table 1-15 on page 1-26.)
SCLK
Input
Serial clockÐWhen so programmed, this signal provides the input
clock for the serial data port (UART). (See Table 1-15 on page 1-26.)
The signal is a GPIO when not programmed as one of the above
functions. After reset, the default state for this signal is GPI.
Alternate:
TMS
MUX_CTL driven high
Input
Input
Test Mode SelectÑWhen selected, this signal acts as the TMS input
for the JTAG TAP controller. The signal is used to sequence that
TAP controller state machine. The TMS is sampled on the rising
edge of TCK.
Note:
When this signal is enabled, the primary TMS signal is
disconnected from the TAP controller. (See Table 1-22
on page 1-36.)
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Pin and Signal Descriptions
DSP56652 Signal Description
Table 1-12 Interrupt Signals (Continued)
Signal
Name
Signal
Type
Freescale Semiconductor, Inc...
DSP_IRQ
Input
State
during
Reset
Signal Description
Input
DSP external interrupt requestÑThis active low Schmitt trigger
input can be programmed as a level-sensitive or negative edgetriggered maskable interrupt request input during normal
instruction processing. If the DSP is in the stop state and DSP_IRQ is
asserted, the DSP exits the stop state.
This signal has an on-chip 47 kW pull-up resistor.
For Interrupt signals equipped with resistors, all pull-ups and pull-downs are
automatically disconnected when the pin is an output.
Timers
Table 1-13 Timer Signals
Signal Name
TOUT0Ð
TOUT7
Signal
Type
State
during
Reset
Input or Input
Output
Signal Description
Timer output 0Ð7ÑThese are Timer Output signals.
Note:
These signals are GPIOs when not used as timer outputs.
After reset, the default state for these signals are GPIs.
Keypad Port
Table 1-14 Keypad Port Signals
Signal Name
COL0ÐCOL5
Signal
Type
State
during
Reset
Input or Input
Output
Signal Description
Column strobe 0Ð5ÑThese signals function as keypad column
strobes that can be programmed as regular or open-drain outputs.
When not used as column strobe signals, these are GPIO signals.
After reset, the default state is GPI.
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DSP56652 Signal Description
Table 1-14 Keypad Port Signals (Continued)
Signal Name
COL6
Signal
Type
State
during
Reset
Input or Input
Output
Column strobe 6ÑThis signal functions as a keypad column strobe
that can be programmed as a regular or open drain output.
Output
MCU timer 1 output compare ÑWhen programmed as OC1, this is
the MCU timer 1 output compare signal.
OC1
Freescale Semiconductor, Inc...
Signal Description
When not programmed as OC1 and not used as a column strobe
signal, this is a GPIO signal. After reset, the default state is GPI.
COL7
Input or Input
Output
Column strobe 7ÑThis signal functions as a keypad column strobe
that can be programmed as a regular or open-drain output.
Output
Pulse width modulator outputÑWhen so programmed, this is the
pulse width modulator output.
PWM
When not programmed as PWM and not used as a column strobe
signal, this is a GPIO signal. After reset, the default state is GPI.
ROW0Ð
ROW4
Input or Input
Output
Row sense 0Ð4ÑThese signals function as keypad row senses.
When not used as row sense signals, these are GPIO signals. After
reset, the default state is GPI. These signals have on-chip 22 kW pullup resistors.
ROW5
Input or Input
Output
Row sense 5ÑThis signal functions as a keypad row sense.
IC2B
Input
MCU input compare 2 timerÑWhen so programmed, this signal
can be the input capture for the MCU input compare 2 timer.
When not programmed as IC2B and not used as a row sense signal,
this is a GPIO signal. After reset, the default state is GPI.
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Pin and Signal Descriptions
DSP56652 Signal Description
Table 1-14 Keypad Port Signals (Continued)
Signal Name
Signal
Type
State
during
Reset
Freescale Semiconductor, Inc...
Normal:
Signal Description
MUX_CTL driven low
ROW6
Input or Input
Output
Row sense 6ÑThis signal functions as a keypad row sense and is
equipped with an on-chip 100kW pull-up resistor.
SC2A
Input or
Output
Audio codec serial control 2 (alternate)ÑWhen programmed as
SC2A, this signal provides I/O frame synchronization for the serial
audio codec port. In synchronous mode, the signal provides the
frame sync for both the transmitter and receiver. In asynchronous
mode, the signal provides the frame sync for the transmitter only.
As SC2A, this pin has a 100kW pull-down resistor.
Note: When this signal is used as SC2A, the primary SC2A signal
is disabled. (See Table 1-18 on page 1-31.)
DCD
Output
Data carrier detectÑWhen programmed as GPIO output, this
signal can be used as the DSR output for the serial data port. (See
Table 1-15 on page 1-26.) After reset, the default state is GPI.
Alternate:
DSP_DE
MUX_CTL driven high
Input
Output
Input
Digital signal processor debug eventÑAs an input signal, this
signal provides a means to enter the debug mode of operation from
an external command converter. An an output signal, it acknowledges that the DSP has entered the debug mode. When programmed as DSP_DE, this signal has an open-drain 100kW pull-up.
When the DSP enters the debug mode due to a debug request or as
the result of meeting a breakpoint condition, it asserts DSP_DE as
an output signal for three clock cycles.
Note: When this signal is enabled, the primary DSP_DE signal is
disabled. (See Table 1-21 on page 1-35.)
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DSP56652
DSP56652 Signal Description
Table 1-14 Keypad Port Signals (Continued)
Signal Name
Signal
Type
State
during
Reset
Signal Description
Freescale Semiconductor, Inc...
Normal:
MUX_CTL driven low
ROW7
Input or Input
Output
SCKA
Input
Row sense 7ÑThis signal functions as a keypad row sense.
Audio codec serial clock (alternate)ÑWhen programmed as SCKA,
this signal provides the serial bit rate clock for the serial audio codec
port. In synchronous mode, the signal provides the clock input or
output for both the transmitter and receiver. In asynchronous mode,
the signal provides the clock for the transmitter only.
Note:
RI
Ring indicatorÑWhen programmed as GPIO output, this signal
can be used as the RI output for the serial data port. (See Table 1-15
on page 1-26.) After reset, the default state is GPI
Output
Alternate:
TCK
When this signal is used as SCKA, the primary SCKA signal
is disabled. (See Table 1-18 on page 1-31.)
MUX_CTL driven high
Input
Input
Test clockÑWhen selected, this signal provides the TCK input for
the JTAG TAP controller. The signal is used to synchronize the
JTAG test logic. This signal is equipped with a 47kW pull-up
resistor.
Note: When this signal is enabled, the primary TCK signal is
disconnected from the TAP controller. (See Table 1-22
on page 1-36.)
For keypad port signals equipped with resistors, all pull-ups and pull-downs are
automatically disconnected when the pin is an output.
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Pin and Signal Descriptions
DSP56652 Signal Description
Serial Data Port (UART)
Table 1-15 Serial Data Port (UART) Signals
Signal Name
Signal
Type
State
during
Reset
Signal Description
Normal:
Freescale Semiconductor, Inc...
TxD
MUX_CTL driven low
Input or Input
Output
UART transmitÑThis signal transmits data from the UART.
The signal is a GPIO when not programmed as the TxD signal. After
reset, the default state for this signal is GPI.
Alternate:
TDO
MUX_CTL driven high
Output
Test data outputÑWhen selected, this signal provides the TDO
serial output for test instructions and data from the JTAG TAP
controller. TDO is a tri-state signal that is actively driven in the
shift-IR and shift-DR controller states.
Note:
Normal:
When this signal is enabled, the primary TDO signal is
disconnected from the TAP controller. (See Table 1-22
on page 1-36.)
MUX_CTL driven low
RxD
Input or Input
Output
UART receiveÑThis signal receives data into the UART.
IC1
Input
Input compare 1ÑWhen so programmed, the signal connects to an
Input capture/output compare Timer used for autobaud mode
support.
The signal is a GPIO when not programmed as one of the above
functions. This signal has an on-chip 47 kW pull-up resistor. After
reset, the default state for this signal is GPI.
Alternate:
TDI
MUX_CTL driven high
Input
Input
Test data inÑWhen selected, this signal provides the TDI serial
input for test instructions and data for the JTAG TAP controller. TDI
is sampled on the rising edge of TCK.
Note:
When this signal is enabled, the primary TDI signal is
disconnected from the TAP controller. (See Table 1-22
on page 1-36.)
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DSP56652 Signal Description
Table 1-15 Serial Data Port (UART) Signals (Continued)
Signal Name
Signal
Type
State
during
Reset
Signal Description
Freescale Semiconductor, Inc...
Normal:
MUX_CTL driven low
RTS
Input or Input
Output
Request to sendÑThis signal functions as the UART RTS signal.
IC2A
Input
Input compare 2 AÑWhen so programmed, this signal connects to
an Input Capture Timer channel.
The signal is a GPIO when not programmed as one of the above
functions. After reset, the default state for this signal is GPI.
Alternate:
RESET_IN
MUX_CTL driven high
Input
Input
Reset inputÑThis signal is an active low Schmitt trigger input that
provides a reset signal to the internal circuitry. The input is valid if
it is asserted for at least three CKIL clock cycles.
Note:
When this signal is enabled, the primary RESET_IN signal
is disabled. (See Table 1-11 on page 1-17.)
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Pin and Signal Descriptions
DSP56652 Signal Description
Table 1-15 Serial Data Port (UART) Signals (Continued)
Signal Name
Signal
Type
State
during
Reset
Signal Description
Normal:
CTS
MUX_CTL driven low
Input or Input
Output
Clear to sendÑThis signal functions as the UART CTS signal, and is
equipped with a 47kW pull-up.
Freescale Semiconductor, Inc...
Note:
The signal is a GPIO when not used as CTS.
After reset, the default state for this signal is GPI.
Alternate:
MCU_DE
MUX_CTL driven high
Input
Output
Input
Microcontroller debug eventÑAs an input signal, this signal
provides a means to enter the debug mode of operation from an
external command converter. An an output signal, it acknowledges
that the MCU has entered the debug mode. The signal is equipped
with an open-drain 47kW pull-up resistor.
When the MCU enters the debug mode due to a debug request or as
the result of meeting a breakpoint condition, it asserts MCU_DE as
an output signal for several clock cycles.
Note:
Note:
¥
When this signal is enabled, the primary MCU_DE signal is
disabled. (See Table 1-21 on page 1-35.)
There are four additional signals that support UART operation, provided as follows:
DSRÑdata set ready. This is an alternate function for the INT6 signal. (See Table 1-12
on page 1-19.)
¥
DTRÑdata terminal ready. This is an alternate function for the INT7 signal. (See Table 1-12
on page 1-19.)
¥
DCDÑdata carrier detect. This is an alternate function for the ROW6 signal. (See Table 1-14
on page 1-22.)
¥
RIÑring indicator. This is an alternate function for the ROW7 signal. (See Table 1-14
on page 1-22.)
For serial data port (UART) signals equipped with resistors, all pull-ups and
pull-downs are automatically disconnected when the pin is an output.
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DSP56652 Signal Description
Serial Control Port
Table 1-16 Serial Control Port Signals
Signal Name
Freescale Semiconductor, Inc...
SPICS0Ð
SPICS3
Signal
Type
Output
State
during
Reset
Input
Input or
Output
SPICS4
Output
Output
Input
Input
Input
Output
Input or
Output
Serial clock Ñ This output signal provides the serial clock from the
QSPI for the accessed peripherals. There is a programmable number
of clock cycles delay between the assertion of the chip select signal
and the first transmission of the serial clock. The polarity and phase
of SCK are programmable.
This is a GPIO signal when the SCK function is not being used.
After reset, the default state is GPI.
Input
Synchronous master in slave outÑThis input signal provides serial
data input to the QSPI. Input data can be sampled on the rising or
falling edge of SCK and received in QSPI RAM MSB or LSB first.
This is a GPIO signal when the function is not being used. After
reset, the default state is GPI.
Input or
Output
MOSI
Synchronous peripheral chip select 4ÑThis output signal provides
a chip select signal for the QSPI. This signal is programmable as
active high or active low. This signal has an on-chip 100 kW pulldown resistor.
This is a GPIO signal when the chip select function is not being
used. After reset, the default state is GPI.
Input or
Output
MISO
Synchronous peripheral chip Select 0Ð3ÑThe output signals
provide chip select signals for the queued serial peripheral interface
(QSPI). The signals are programmable as active high or active low.
Each signal has an on-chip 100 kW pull-up resistor.
These are GPIO signals when the chip select functions are not being
used. After reset, the default state for each signal is GPI.
Input or
Output
SCK
Signal Description
Input
Synchronous master out slave inÑThis output signal provides
serial data from the QSPI. Output data can be programmed to
change state on the rising or falling edge of SCK and transmitted
MSB or LSB first.
This is a GPIO signal when the function is not being used. After
reset, the default state is GPI.
For serial control port signals equipped with resistors, all pull-ups and pull-downs
are automatically disconnected when the pin is an output.
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Pin and Signal Descriptions
DSP56652 Signal Description
Smart Card Port
After rest, the default state of all Smart Card port pins is GPI. For Smart Card port
signals equipped with resistors, all pull-ups and pull-downs are automatically
disconnected when the pin is an output.
Table 1-17 Smart Card Port Signals
Freescale Semiconductor, Inc...
Signal Name
SIMCLK
Signal
Type
Output
State
during
Reset
Input
Input or
Output
SENSE
Input
Input/
Output
Input
Output
Input
Output
Input or
Output
SIM dataÑThis bidirectional signal is used to transmit data to and
receive data from the Smart Card. In the output state, the signal is
open drain.
This signal is a GPIO signal when the Smart Card port is not being
used. The signal has an on-chip 47 kW pull-up resistor.
Input
Input or
Output
PWR_EN
SIM senseÑThis signal is a Schmitt trigger input that signals when
a Smart Card is inserted or removed.
This signal is a GPIO signal when the Smart Card port is not being
used. The signal has an on-chip 100 kW pull-down resistor.
Input or
Output
SIMRESET
SIM clockÑThis signal is an output clock from the Smart Card port
to the Smart Card.
This signal is a GPIO signal when the Smart Card port is not being
used.
Input or
Output
SIMDATA
Signal Description
SIM ResetÑThis signal is an output reset signal from the Smart
Card port to the Smart Card. The Smart Card port can activate the
reset of an attached Smart Card by driving SIMRESET low.
This signal is a GPIO signal when the Smart Card port is not being
used.
Input
SIM power enableÑThis active high output enables the external
device that supplies VCC to the Smart Card. If this pin is driven
high, the external device supplies power to the Smart Card. Driving
the signal low cuts off power to card. This permits effective power
management and power sequencing for Smart Card enable/disable.
This signal is a GPIO signal when the Smart Card port is not being
used. This signal has an on-chip 100 kW pull-down resistor.
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DSP56652 Signal Description
Serial Audio Codec Port
After reset, the default state of all serial audio codec pins is Hi-Z. For serial audio
codec port signals equipped with resistors, all pull-ups and pull-downs are
automatically disconnected when the pin is an output
Table 1-18 Serial Audio Codec Port Signals
Freescale Semiconductor, Inc...
Signal Name
STDA
Signal
Type
State
during
Reset
Input or Input
Output
Signal Description
Audio codec transmit dataÑ This output signal transmits serial
data from the audio codec serial transmitter shift register. It is
equipped with a 100kW pull-up resistor.
This is a GPIO signal when STDA is not being used.
Note:
SRDA
Input or Input
Output
Audio codec receive data Ñ This input signal receives serial data
and transfers the data to the audio codec receive shift register. It is
equipped with a 100kW pull-down resistor.
This is a GPIO signal when SRDA is not being used.
Note:
SCKA
Input or Input
Output
Input or Input
Output
This signal is disabled if the alternate SRDA function on
INT7 is selected. (See Table 1-12 on page 1-19.)
Audio codec serial clock Ñ This bidirectional signal provides the
serial bit rate clock when only one clock is being used or the TxD
clock otherwise. It is equipped with a 100kW pull-down resistor.
This is a GPIO signal when the serial audio codec port is not being
used.
Note:
SC0A
This signal is disabled if the alternate STDA function on
INT6 is selected. (See Table 1-12 on page 1-19.)
This signal is disabled if the alternate SCKA function on
ROW7 is selected. (See Table 1-14 on page 1-22.)
Audio codec serial clock 0ÑThis signalÕs function is determined by
the SCLK mode.
¥ Synchronous modeÑserial I/O flag 0
¥
Asynchronous modeÑreceive clock I/O
This is a GPIO signal when SC0A is not being used.
SC1A
Input or Input
Output
Audio codec serial clock 1ÑThis signalÕs function is determined by
the SCLK mode.
¥ Synchronous modeÑserial I/O flag 0
¥
Asynchronous modeÑreceiver frame sync I/O
This is a GPIO signal when SC1A is not being used.
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Pin and Signal Descriptions
DSP56652 Signal Description
Table 1-18 Serial Audio Codec Port Signals (Continued)
Signal Name
SC2A
Signal
Type
State
during
Reset
Input or Input
Output
Signal Description
Audio codec serial clock 2ÑThis signalÕs function is determined by
the SCLK mode.
¥ Synchronous modeÑtransmitter and receiver frame sync I/O
Freescale Semiconductor, Inc...
¥
Asynchronous modeÑtransmitter frame sync I/O
It is equipped with a 100kW pull-down resistor.
This is a GPIO signal when SC2A is not being used.
Note: This signal is disabled if the alternate SC2A function on
ROW6 is selected. (See Table 1-14 on page 1-22.)
Baseband Codec Port
After reset, the default state of the baseband codec port pins is Hi-Z. For baseband
codec port signals equipped with resistors, all pull-ups and pull-downs are
automatically disconnected when the pin is an output.
Table 1-19 Baseband Codec Port Signals
Signal Name
STDB
Signal
Type
Output
State
during
Reset
Input
Input or
Output
SRDB
Input
Baseband codec transmit dataÑ This output signal transmits serial
data from the baseband codec serial transmitter shift register. This
signal is equipped with a 100 pull-up resistor.
This is a GPIO signal when STDB is not being used.
Input
Input or
Output
SCKB
Signal Description
Input or Input
Output
Baseband codec receive data Ñ This input signal receives serial
data and transfers the data to the baseband codec receive shift
register. This signal is equipped with a 100kW pull-down resistor.
This is a GPIO signal when SRDB is not being used.
Baseband codec serial clock Ñ This bidirectional signal provides
the serial bit rate clock when only one clock is being used or the TxD
clock otherwise. This signal is equipped with a 100kW pull-down
resistor. This is a GPIO signal when the serial baseband codec port
is not being used.
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DSP56652
DSP56652 Signal Description
Table 1-19 Baseband Codec Port Signals (Continued)
Signal Name
SC0B
Signal
Type
State
during
Reset
Input or Input
Output
Signal Description
baseband codec serial clock 0ÑThis signalÕs function is determined
by the SCLK mode.
¥ Synchronous modeÑserial I/O flag 0
Freescale Semiconductor, Inc...
¥
Asynchronous modeÑreceive clock I/O
This signal is equipped with a 100kW pull-down resistor.
This is a GPIO signal when SC0B is not being used.
SC1B
Input or Input
Output
Baseband codec serial clock 1ÑThis signalÕs function is determined
by the SCLK mode.
¥ Synchronous modeÑserial I/O flag 0
¥
Asynchronous modeÑreceiver frame sync I/O
This signal is equipped with a 100KkW pull-down resistor.
This is a GPIO signal when SC1B is not being used.
SC2B
Input or Input
Output
Baseband codec serial clock 2ÑThis signalÕs function is determined
by the SCLK mode.
¥ Synchronous modeÑtransmitter and receiver frame sync I/O
¥
Asynchronous modeÑtransmitter frame sync I/O
This signal is equipped with a 100kW pull-down resistor.
This is a GPIO signal when SC2B is not being used.
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Pin and Signal Descriptions
DSP56652 Signal Description
Emulation Port
After reset, the default state for the emulation port pins is GPI.
Table 1-20 Emulation Port Signals
Signal Name
Freescale Semiconductor, Inc...
SIZ0ÐSIZ1
Signal
Type
State
during
Reset
Input or Input
Output
Signal Description
Data size 0Ð1ÑThese signals encode the data size for the current
MCU access.
When not programmed as data size signals, these are GPIO signals.
The signals have on-chip 100 kW pull-up resistors.
PSTAT0Ð
PSTAT3
Input or Input
Output
Pipeline state 0Ð3ÑThese signals encode the internal MCU
execution unit status.
When not programmed as pipeline state signals, these are GPIO
signals. The signals have on-chip 100 kW pull-up resistors.
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DSP56652
DSP56652 Signal Description
Debug Control Port
If the MUX_CTL signal is driven high, the alternate MCU_DE and DSP_DE signal
locations are selected, and this interface is disabled. For debug port control signals
equipped with resistors, all pull-ups and pull-downs are automatically disconnected
when the pin is an output.
Table 1-21 Debug Port Control Signals
Freescale Semiconductor, Inc...
Signal Name
MCU_DE
Signal
Type
Input
State
during
Reset
Input
Output
DSP_DE
Input
Output
Signal Description
Microcontroller debug eventÑAs an input signal, this signal
provides a means to enter the debug mode of operation from an
external command converter. An an output signal, it acknowledges
that the MCU has entered the debug mode. This signal is equipped
with an open-drain 47kW pull-up resistor.
When the MCU enters the debug mode due to a debug request or as
the result of meeting a breakpoint condition, it asserts MCU_DE
as an output signal for three clock cycles.
Input
Digital signal processor debug eventÑAs an input signal, this
signal provides a means to enter the debug mode of operation from
an external command converter. An an output signal, it acknowledges that the DSP has entered the debug mode.This signal is
equipped with an open-drain 4kW K pull-up resistor.
When the DSP enters the debug mode due to a debug request or as
the result of meeting a breakpoint condition, it asserts DSP_DE as
an output signal for three clock cycles.
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Pin and Signal Descriptions
DSP56652 Signal Description
JTAG Port
When the bottom connector pins are selected as a debug port by holding the
MUX_CTL pin at a logic high, the dedicated JTAG pins become inactive. That is, they
are disconnected from the JTAG TAP controller. For JTAG signals equipped with
resistors, all pull-ups and pull-downs are automatically disconnected when the pin is
an output.
Freescale Semiconductor, Inc...
Table 1-22 JTAG Port Signals
Signal Name
Signal
Type
State
during
Reset
Signal Description
TMS
Input
Input
Test mode selectÑTMS is an input signal used to sequence the test
controllerÕs state machine. TMS is sampled on the rising edge of
TCK and has an internal 47 kW pull-up resistor.
MUX_CTL high: INT7 is connected to the TAP controller and
functions as TMS, see Table 1-12 on page 1-19.)
TDI
Input
Input
Test data inputÑTDI is a serial test data input signal used for test
instructions and data. TDI is sampled on the rising edge of TCK and
has an internal 47 kW pull-up resistor.
MUX_CTL high: RxD is connected to the TAP controller and
functions as TDI, see Table 1-15 on page 1-26.)
TDO
Output
Tristated
Test data outputÑTDO is a test data serial output signal used for
test instructions and data. TDO is tri-statable and is actively driven
in the shift-IR and shift-DR controller states. TDO changes on the
falling edge of TCK.
MUX_CTL high: TxD is connected to the TAP controller and
functions as TDO, see Table 1-15 on page 1-26.)
TCK
Input
Input
Test clockÑTCK is a test clock input signal used to synchronize the
JTAG test logic. It has an internal 47 kW pull-up resistor.
MUX_CTL high: ROW7 is connected to the TAP controller and
functions as TCK, see Table 1-14 on page 1-22.)
TRST
Input
Input
Test ResetÑTRST is an active-low Schmitt-trigger input signal used
to asynchronously initialize the test controller. TRST has an internal
47 kW pull-up resistor.
MUX_CTL high: INT6 is connected to the TAP controller and
functions as TRST, see Table 1-12 on page 1-19.)
TEST
Input
Input
Factory test modeÑSelects factory test mode. Reserved. This pin
MUST be connected to ground.
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SECTION
2
SPECIFICATIONS
Freescale Semiconductor, Inc...
GENERAL CHARACTERISTICS
The DSP56652 is fabricated in high-density CMOS. The DSP56652 specifications are
preliminary and are from design simulations, and may not be fully tested or
guaranteed at this early stage of the product life cycle. Finalized specifications will be
published after full characterization and device qualifications are complete.
MAXIMUM RATINGS
CAUTION
This device contains circuitry protecting
against damage due to high static voltage or
electrical fields; however, normal precautions
should be taken to avoid exceeding maximum
voltage ratings. Reliability is enhanced if
unused inputs are tied to an appropriate logic
voltage level (e.g., either GND or VCC).
Note: In the calculation of timing requirements, adding a maximum value of one
specification to a minimum value of another specification does not yield a
reasonable sum. A maximum specification is calculated using a worst case
variation of process parameter values in one direction. The minimum
specification is calculated using the worst case for the same parameters in the
opposite direction. Therefore, a ÒmaximumÓ value for a specification will
never occur in the same device that has a ÒminimumÓ value for another
specification; adding a maximum to a minimum represents a condition that
can never exist.
Preliminary
MOTOROLA
DSP56652 Technical Data Sheet
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2-1
Freescale Semiconductor, Inc.
Specifications
Thermal characteristics
Table 2-1 Absolute Maximum Ratings (GND = 0 V)
Rating
Symbol
Value
Unit
Internal supply voltage
VCCI
Ð0.3 to +2.75
V
External supply voltage
VCCE
Ð0.3 to +3.6
V
TA
Ð40 to +85
°C
TSTG
Ð55 to +125
°C
Operating temperature range
Freescale Semiconductor, Inc...
Storage temperature
THERMAL CHARACTERISTICS
Table 2-2 Thermal Characteristics
Symbol
BGA Value3
Unit
Junction-to-ambient thermal resistance1
RqJA or qJA
TBD
ûC/W
Junction-to-case thermal resistance2
RqJC or qJC
TBD
ûC/W
Thermal characterization parameter
YJT
TBD
ûC/W
Characteristic
Notes:
1.
2.
3.
Junction-to-ambient thermal resistance is based on measurements on a horizontal-singlesided printed circuit board per SEMI G38-87 in natural convection.(SEMI is Semiconductor
Equipment and Materials International, 805 East Middlefield Rd., Mountain View, CA
94043, (415) 964-5111)
Junction-to-case thermal resistance is based on measurements using a cold plate per SEMI
G30-88, with the exception that the cold plate temperature is used for the case temperature.
These are measured values; testing is not complete. Values were measured on a nonstandard four-layer thermal test board (two internal planes) at one watt in a horizontal
configuration.
Preliminary
2-2
DSP56652 Technical Data Sheet
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MOTOROLA
Freescale Semiconductor, Inc.
DSP56652
DC Electrical Characteristics
DC ELECTRICAL CHARACTERISTICS
Table 2-3 DC Electrical Characteristics
Characteristics
Symbol
Min
Typ
Max
Units
Internal supply voltage
VCCI
1.8
Ñ
2.5
V
External supply voltage
VCCE
VCCI
Ñ
3.4
V
VCCHQ
VCCE
Ñ
3.4
V
Input high voltage
VIH
0.7 ´ VCCE
Ñ
VCCE + 0.2
V
Input low voltage
VIL
Ð0.3
Ñ
0.2 ´ VCCE
V
Input leakage current
IIN
Ð10
Ñ
10
mA
Output high voltage (IOH = Ð400 mA)
VOH
0.75 ´ VCCE
Ñ
VCCE
V
Output low voltage (IOL = 800 mA)
VOL
0
Ñ
0.18 ´ VCCE
V
Total stop mode (DSP and MCU stopped, PLL
powered down, timers disabled)
ICC_STOP
Ñ
60
Ñ
mA
DSP run current at 58.8 MHz (MCU stopped,
timers disabled, DSP running algorithm from
internal memory, BBP and SAP active)
ICCDSP_RUN
Ñ
35
Ñ
mA
PLL supply current (16.8 MHz input,
DSP freq = 58.8 MHz, MCU clock = 16.8 MHz)
ICC_PLL
Ñ
1.6
Ñ
mA
DSP wait current at 58.8 MHz (MCU stopped,
timers disabled, BBP and SAP active)
ICC_DSP_WAIT
Ñ
4.5
Ñ
mA
MCU run current at 16.8 MHz (DSP and DSP
ICC_MCU_RUN
PLL stopped, timers disabled, MCU peripherals
active)
Ñ
9
Ñ
mA
MCU doze current at 16.8 MHz (DSP and DSP ICC_MCU_DOZE
PLL stopped, timers disabled, MCU peripherals
active)
Ñ
3
Ñ
mA
MCU wait current at 16.8 MHz (DSP and DSP ICC_MCU_WAIT
PLL stopped, timers disabled, MCU peripherals
active)
Ñ
3
Ñ
mA
Timer current (MCU and DSP stopped; 16.8
MHz to timer)
ICC_TIMER
Ñ
500
Ñ
mA
CIN
Ñ
Ñ
TBD
pF
Ñ
50%
100%
180%
Ñ
Freescale Semiconductor, Inc...
I/O predriver supply voltage
Input capacitance per pin
Pull-up resistor
Note:
1.
value1
Applies to 22K and 47K resistors.
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2-3
Freescale Semiconductor, Inc.
Specifications
Clock Requirements
CLOCK REQUIREMENTS
Table 2-4 Clock Requirements
Freescale Semiconductor, Inc...
Characteristics
Symbol
Min
Typ
Max
Units
CKIH input frequency
f1
0
Ñ
16.8
MHz
CKIL input frequency
f2
0
32.768
f1
kHz
MCU internal frequency
fMCU-CLK
0
Ñ
16.8
MHz
DSP internal frequency
fDSP-CLK
Ñ
Ñ
58.8
MHz
CKIH input amplitude
VI-CKIH
285
Ñ
VIH
mVPP
CKIH input voltage
VIH-CKIH
0
Ñ
VCCE
V
CKIL input low voltage
VIL-CKIL
-0.3
Ñ
0.2xVCCE
V
CKIL input high voltage
VIH-CKIL
VCCI
Ñ
2.77
V
CKIH input impedance
RI-CKIH
TBD
Ñ
TBD
MW
EXTERNAL BUS INTERFACE REQUIREMENTS
When the MCU is operating at 16.8 MHz, the bus interface can access 100 ns access
time external memory with one wait state or 15 ns access time external memory with
no wait states.
AC ELECTRICAL CHARACTERISTICS
The characteristics listed in this section are given for VDDI = 1.8 V and VDDE = 3.3 V
with a capacitive load of 50 pF.
Preliminary
2-4
DSP56652 Technical Data Sheet
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Freescale Semiconductor, Inc.
DSP56652
Internal Clocks
INTERNAL CLOCKS
For each occurrence of TDH, TDL, TDC, or IDCYC, substitute with the numbers in
Table 2-6. DF, MF, and PDF are the DSP PLL division, multiplication, and predivision factors set in registers.
Table 2-5 DSP Clocks
Freescale Semiconductor, Inc...
Characteristics
Symbol
Min
Max
Unit
Input frequency to the DSP PLL
EfD
0
16.8
MHz
DSP PLL input clock cycle time
¥ with PLL disabled
¥ with PLL enabled
ETDC
59.5
59.5
¥
273100
ns
ns
Table 2-6 Internal DSP Clocks
Characteristics
Symbol
Expression
Internal DSP operation frequency with PLL enabled
fD
(EfD ´ MF) / (PDF ´ DF)
Internal DSP operation frequency with PLL
disabled
fD
EfD/2
Internal DSP clock high period
¥ with PLL disabled
¥ with PLL enabled and MF £ 4
TDH
ETDC
(Min) 0.49 ´ ETDC ´ PDF ´ DF/MF
(Max) 0.51 ´ ETDC ´ PDF ´ DF/MF
(Min) 0.47 ´ ETDC ´ PDF ´ DF/MF
(Max) 0.53 ´ ETDC ´ PDF ´ DF/MF
¥ with PLL enabled and MF > 4
Internal clock low period
¥ with PLL disabled
¥ with PLL enabled and MF £ 4
TDL
ETDC
(Min) 0.49 ´ ETDC ´ PDF ´ DF/MF
(Max) 0.51 ´ ETDC ´ PDF ´ DF/MF
(Min) 0.47 ´ ETDC ´ PDF ´ DF/MF
(Max) 0.53 ´ ETDC ´ PDF ´ DF/MF
Internal clock cycle time with PLL enabled
TDC
ETDC ´ PDF ´ DF/MF
Internal clock cycle time with PLL disabled
TDC
2 ´ ETDC
IDCYC
TDC
¥ with PLL enabled and MF > 4
DSP Instruction cycle time
Table 2-7 MCU Clocks
Characteristics
Symbol
Min
Max
Unit
fM
0
16.8
MHz
TMC
59.5
¥
ns
Frequency of the internal MCU-CLK clock
Internal MCU-CLK clock cycle time
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2-5
Freescale Semiconductor, Inc.
Specifications
Phase-Locked Loop (PLL) Characteristics
PHASE-LOCKED LOOP (PLL) CHARACTERISTICS
Table 2-8 Phase-Locked Loop (PLL) Characteristics
Characteristics
VCO frequency when PLL
enabled1
Expression
Min
Max
Unit
MF ´ EfD ´ 2 / PDF
30
120
MHz
CPCAP 2
PLL external capacitor (PCAP pin to VCCP)
¥ MF £ 4
¥
Freescale Semiconductor, Inc...
Notes:
MF > 4
1.
2.
MF ´ 580Ð 100 MF ´ 780Ð 140
MF ´ 830
MF ´ 1470
pF
The VCO output is further divided by 2 when PLL is enabled. If the division factor (DF) is 1, the
operating frequency is VCO .
------------2
CPCAP is the value of the PLL capacitor (connected between PCAP pin and VCCP).
(The recommended value for Cpcap is (680 ´ MF Ð 120) pF for MF £ 4 and (1100 ´ MF) pF for MF > 4.)
RESET, MODE SELECT, AND INTERRUPT TIMING
Table 2-9 Reset, Mode Select, and Interrupt Timing
Num
Characteristics
Expression
MCU @16.8
MHz DSP
@58.8 MHz
Min
Max
Ñ
1
RESET_IN duration to guarantee reset
3 ´ TCKIL + 0.05
91.6
2
Delay from RESET_IN assertion to RESET_OUT
assertion
min: 4.5 ´ TCKIL
max: 5.5 ´ TCKIL
137.33
7 ´ TCKIL
213.62
Unit
ms
ms
167.85
Ñ
ms
167.85
ms
ms
107
Ñ
ms
Ñ
0
Ñ
ns
Minimum edge-triggered DSP_IRQ assertion
width
Ñ
10
Ñ
ns
8
Minimum edge-triggered DSP_IRQ deassertion
width
Ñ
10
Ñ
ns
9
Minimum edge-triggered INTn width high
Ñ
TBD
Ñ
ns
10
Minimum edge-triggered INTn width low
Ñ
TBD
Ñ
ns
3
Duration of RESET_OUT assertion
4
Delay from RESET_IN assertion to all pins at Reset
value (periodically sampled and not 100% tested)
min: 4.5 ´ TCKIL
max: 5.5 ´ TCKIL
137.33
5
MOD select setup time
3.5 ´ TCKIL + 0.02
6
MOD select hold time
7
Preliminary
2-6
DSP56652 Technical Data Sheet
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Freescale Semiconductor, Inc.
DSP56652
RESET, Mode Select, and Interrupt Timing
RESET_IN
1
Freescale Semiconductor, Inc...
RESET_OUT
3
2
4
All Pins
Reset Value
AA1679
Figure 2-1 Reset Timing
RESET_OUT
5
6
MOD
AA1680
Figure 2-2 Operating Mode Select Timing
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MOTOROLA
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2-7
Freescale Semiconductor, Inc.
Specifications
RESET, Mode Select, and Interrupt Timing
DSP_IRQ
7
DSP_IRQ
Freescale Semiconductor, Inc...
8
AA1681
Figure 2-3 DSP External Interrupt Timing (Negative Edge-Triggered)
DSP External Interrupt Timing (Negative Edge-Triggered)
INTn
9
INTn
10
AA1682
Figure 2-4 INT0ÐINT7 External Interrupt Timing
Preliminary
2-8
DSP56652 Technical Data Sheet
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Freescale Semiconductor, Inc.
DSP56652
External Interface Module (EIM) Timing
EXTERNAL INTERFACE MODULE (EIM) TIMING
The EIM provides the bus interface between the DSP56652 and external memory and
peripherals. It uses the external address bus, data bus, bus control signals, and the
chip select signals.
Table 2-10 EIM External Bus Output AC Timing Specifications1
Freescale Semiconductor, Inc...
Num
Characteristics
MCU
@16.8 MHz
Min
Max
Unit
11
CLK rise to address and R/W valid
0
15
ns
12
CLK rise to address and R/W invalid (output hold)
0
15
ns
13
CLK rise to CS asserted
0
15
ns
14
CLK rise to CS deasserted (output hold)
0
15
ns
15
CLK fall to OE, EB asserted (read, OEA = 0),
EB asserted (write)2
0
15
ns
16
CLK rise to OE, EB asserted (read, OEA = 1)2
0
15
ns
17
CLK rise to OE, EB deasserted (output hold) (read)2
0
15
ns
CLK rise to EB deasserted (output hold) (write, WEN = 0)
0
15
ns
CLK fall to EB deasserted (output hold) (write, WEN = 1)
0
15
ns
Ñ
15
ns
18
0)2
19
CLK fall to OE, EB asserted (WSC =
20
CLK rise to OE, EB deasserted (output hold) (WSC = 0)2
0
15
ns
21
Data-in valid to CLK rise (setup)
3
Ñ
ns
22
CLK rise to dataÐin invalid (hold)
7
Ñ
ns
23
CLK rise to data-out valid
0
20
ns
24
CLK rise to data-out invalid (output hold)
0
20
ns
25
CLK rise to data-out high impedance
0
20
ns
26
CLK fall to data-out valid (WSC = 0)
0
20
ns
27
CLK rise to data-out invalid (output hold) (WSC = 0)
0
20
ns
28
CLK rise to data-out high impedance (WSC = 0)
0
20
ns
Note:
1.
2.
The following notes apply to this table:
¥ Input and Output timings are measured at the 50% point of the waveforms. The specifications
assume a capacitive load of 50 pF.
¥ These timings were measured with respect to the input clock edges.
EB outputs are asserted for reads if the EBC bit in the corresponding CS control register is clear.
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2-9
Freescale Semiconductor, Inc.
Specifications
External Interface Module (EIM) Timing
CLK
11
ADDRESS
R/W
12
CS
13
Freescale Semiconductor, Inc...
14
15
OE, EB (OEA=0)
(READ)
17
16
OE, EB (OEA=1)
(READ)
17
15
EB (WEN=0)
(WRITE)
17
15
EB (WEN=1)
(WRITE)
18
19
OE, EB (WSC=0)
20
21
DATA in
(READ)
22
23
25
DATA out
(WRITE)
24
26
28
DATA out (WSC=0)
(WRITE)
27
AA1683
Figure 2-5 EIM Read/Write Timing
Preliminary
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DSP56652 Technical Data Sheet
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Freescale Semiconductor, Inc.
DSP56652
Smart Card Timing
SMART CARD TIMING
Table 2-11 Smart Card Port to Smart Card AC Timing
Freescale Semiconductor, Inc...
Num
CKIH
@ 16.8 MHz
Characteristics
Min
Max
Unit
31
SIMRESET low to SIMCLK low
1.18
200/f
ms
32
SIMCLK deactivated to SIMDATA tri-state to low
1.18
200/f
ms
33
SIMDATA low to PWR_EN low
1.18
200/f
ms
34
SIMRESET low
40000/f
Ñ
ns
35
SENSE high to SIMRESET low
57
76
ms
Note:
ÒfÓ is CKIH/4 (for 5 V sims) or CKIH/5 (for 3 V sims), as programmed in the Smart Card
port.
SENSE
35
34
SIMRESET
31
SIMCLK
32
38
SIMDATA
33
PWR_EN
AA1684
Figure 2-6 Smart Card Interface Power Down AC Timing
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2-11
Freescale Semiconductor, Inc.
Specifications
QSPI Timing
QSPI TIMING
The queued serial peripheral interface (QSPI) uses the signals in the serial control
port to select individual serial peripherals (using the SPI chip select signals) and
transfer data between peripherals and the DSP56652.
Table 2-12 QSPI Timing
Freescale Semiconductor, Inc...
Num
Characteristics
301
Cycle time
302
Symbol
Expression
MCU
@ 16.8 MHz
Unit
Min
Max
1
504
TMC
252
TMC
TQCYC
Ñ
Clock (SCK) high or low time
TSW
Ñ
303
Chip-select lag time
TLAG
Ñ
1
¥
TQCYC
304
Inter-queue transfer delay
TTD
Ñ
1
¥
TQCYC
305
Chip-select lead time
TLEAD
Ñ
1
128
TQCYC
306
Data setup time (inputs)
TSU
Ñ
0
Ñ
nS
307
Data hold time (inputs)
THI
Ñ
0.5
Ñ
TQCYC
308
Data valid (after SCK edge)
TV
Ñ
Ñ
6
nS
309
Data hold time (outputs)
THO
Ñ
Ð2
Ñ
nS
310
Rise time
TI
Ñ
Ñ
10
nS
311
Fall time
TF
Ñ
Ñ
10
nS
305
303
PCS [4:0]
301
310
304
302
SCK (CSPOL = 0)
304
SCK (CSPOL = 1)
MISO
MSB IN
DATA
308
MOSI
307
311
306
MSB OUT
MSB IN
LSB IN
309
DATA
LSB OUT
MSB OUT
AA1685
Figure 2-7 QSPI Timings for CPHA = 0
Preliminary
2-12
DSP56652 Technical Data Sheet
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Freescale Semiconductor, Inc.
DSP56652
Audio Serial Codec and Baseband Serial Codec Timing
303
305
PCS [4:0]
310
301
304
SCK (CSPOL = 0)
302
SCK (CSPOL = 1)
302
Freescale Semiconductor, Inc...
MISO
MSB IN
DATA
308
MOSI
307
311
306
LSB IN
MSB IN
309
MSB OUT
DATA
LSB OUT
AA1686
MSB OUT
Figure 2-8 QSPI Timings for CPHA = 1
AUDIO SERIAL CODEC AND BASEBAND SERIAL CODEC TIMING
The audio serial codec port (also called the serial audio port or SAP) and the
baseband serial codec port (also called the baseband port or BBP) have the same
timing specifications. The timing table uses the following acronyms to describe the
signal parameters:
tSSICC
TXC (SCKA/SCKB Pin)
RXC (SC0A/SC0B or SCKA/SCKB Pin)
FST (SC2A/SC2B Pin)
FSR (SC1A/SC1B or SC2A/SC2B Pin)
i ck
x ck
i ck a
=
=
=
=
=
=
=
=
i ck s =
bl =
wl =
wr =
BBP/SAP clock cycle time
Transmit clock
Receive clock
Transmit frame sync
Receive frame sync
Internal clock
External clock
Internal clock, asynchronous mode (Asynchronous
implies that TXC and RXC are two different clocks)
Internal clock, synchronous mode (Synchronous implies
that TXC and RXC are the same clock)
Bit length
Word length
Word length relative
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Freescale Semiconductor, Inc.
Specifications
Audio Serial Codec and Baseband Serial Codec Timing
Table 2-13 SAP and BBP Timing
Num
Characteristics
Symbol
Expression
DSP_CLK
@ 58.8
Case
MHz
Unit
Freescale Semiconductor, Inc...
Min Max
430
Clock cycle1
431
Clock high period
for internal clock
for external clock
Ñ
Clock low period
for internal clock
for external clock
Ñ
433
RXC rising edge to FSR out (bl) high
Ñ
Ñ
Ñ
Ñ
45.1 x ck
26.8 i ck a
ns
ns
434
RXC rising edge to FSR out (bl) low
Ñ
Ñ
Ñ
Ñ
45.1 x ck
26.8 i ck a
ns
ns
435
RXC rising edge to FSR out (wr) high2
Ñ
Ñ
Ñ
Ñ
47.6 x ck
29.3 i ck a
ns
ns
436
RXC rising edge to FSR out (wr) low2
Ñ
Ñ
Ñ
Ñ
47.6 x ck
29.3 i ck a
ns
ns
437
RXC rising edge to FSR out (wl) high
Ñ
Ñ
Ñ
Ñ
45.9 x ck
25.6 i ck a
ns
ns
438
RXC rising edge to FSR out (wl) low
Ñ
Ñ
Ñ
Ñ
45.1 x ck
26.8 i ck a
ns
ns
439
Data in setup time before RXC
(SCK in synchronous mode) falling edge
Ñ
Ñ
0.0
23.2
Ñ
Ñ
x ck
i ck
ns
ns
440
Data in hold time after RXC
falling edge
Ñ
Ñ
6.1
3.6
Ñ
Ñ
x ck
i ck
ns
ns
441
FSR input (bl, wr) high before RXC
falling edge2
Ñ
Ñ
1.2
28.0
Ñ
Ñ
x ck
i ck a
ns
ns
442
FSR input (wl) high before RXC
falling edge
Ñ
Ñ
1.2
28.0
Ñ
Ñ
x ck
i ck a
ns
ns
443
FSR Input hold time after RXC
falling edge
Ñ
Ñ
3.6
0.0
Ñ
Ñ
x ck
i ck a
ns
ns
444
Flags input setup before RXC
Falling edge
Ñ
Ñ
0.0
23.2
Ñ
Ñ
x ck
i ck s
ns
ns
432
tSSICC
4 ´ TDC
3 ´ TDC
68
51
Ñ
Ñ
i ck
x ck
ns
ns
2 ´ TDC Ð 12.2 21.8
1.5 ´ TDC
25.5
Ñ
Ñ
ick
xck
ns
ns
2 ´ TDC Ð 12.2 21.8
1.5 ´ TDC
25.5
Ñ
Ñ
ick
xck
ns
ns
Preliminary
2-14
DSP56652 Technical Data Sheet
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DSP56652
Audio Serial Codec and Baseband Serial Codec Timing
Table 2-13 SAP and BBP Timing (Continued)
Num
Characteristics
Symbol
Expression
DSP_CLK
@ 58.8
Case
MHz
Unit
Freescale Semiconductor, Inc...
Min Max
445
Flags input hold time after RXC
falling edge
Ñ
Ñ
7.3
0.0
446
TXC rising edge to FST out (bl) high
Ñ
Ñ
Ñ
Ñ
35.4 x ck
18.3 i ck
ns
ns
447
TXC rising edge to FST out (bl) low
Ñ
Ñ
Ñ
Ñ
37.8 x ck
20.7 i ck
ns
ns
448
TXC rising edge to FST out (wr) high2
Ñ
Ñ
Ñ
Ñ
37.8 x ck
20.7 i ck
ns
ns
449
TXC rising edge to FST out (wr) low2
Ñ
Ñ
Ñ
Ñ
40.3 x ck
23.2 i ck
ns
ns
450
TXC rising edge to FST out (wl) high
Ñ
Ñ
Ñ
Ñ
36.6 x ck
19.5 i ck
ns
ns
451
TXC rising edge to FST out (wl) low
Ñ
Ñ
Ñ
Ñ
37.8 x ck
20.7 i ck
ns
ns
452
TXC rising edge to data out enable from
high impedance
Ñ
Ñ
Ñ
Ñ
37.8 x ck
20.7 i ck
ns
ns
454
TXC rising edge to data out valid
Ñ
35 + 0.5 ´ TDC
Ñ
Ñ
43.5 x ck
25.6 i ck
ns
ns
455
TXC rising edge to data out high
impedance3
Ñ
Ñ
Ñ
Ñ
37.8 x ck
19.5 i ck
ns
ns
457
FST input (bl, wr) setup time before TXC
falling edge2
Ñ
Ñ
2.0
21.0
Ñ
Ñ
458
FST input (wl) to data out enable from
high impedance3
Ñ
Ñ
Ñ
32.9
460
FST input (wl) setup time before TXC
falling edge
Ñ
Ñ
2.0
21.0
Ñ
Ñ
x ck
i ck
ns
ns
461
FST input hold time after TXC falling
edge
Ñ
Ñ
4.0
0.0
Ñ
Ñ
x ck
i ck
ns
ns
462
Flag output valid after TXC rising edge
Ñ
Ñ
Ñ
Ñ
39.0 x ck
22.0 i ck
ns
ns
Note:
1.
2.
3.
Ñ
Ñ
x ck
i ck s
x ck
i ck
ns
ns
ns
ns
ns
For internal clock, external clock cycle is defined by ICYC and BBP/SAP control register.
Word relative frame sync signal wave form, relates to clock, as the bit length frame sync signal wave
form, but spreads from one serial clock before first bit clock (same as bit length frame sync signal),
until the one before last bit clock of the first word in frame.
Periodically sampled and not 100% tested
Preliminary
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Specifications
Audio Serial Codec and Baseband Serial Codec Timing
430
431
432
TXC
(Input/Output)
Freescale Semiconductor, Inc...
446
447
FST (Bit)
Out
450
451
FST (Word)
Out
455
455
457
452
Data Out
First Bit
Last Bit
460
461
FST (Bit) In
458
461
460
FST (Word) In
462
Flags Out
AA1687
Note: In the network mode, output flag transitions can occur at the start of each time slot
within the frame. In the normal mode, the output flag state is asserted for the entire
frame period.
Figure 2-9 BBP and SAP Transmitter Timing
Preliminary
2-16
DSP56652 Technical Data Sheet
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Freescale Semiconductor, Inc.
DSP56652
Audio Serial Codec and Baseband Serial Codec Timing
430
431
432
RXC
(Input/Output)
Freescale Semiconductor, Inc...
433
FSR (Bit)
Out
434
437
438
FSR (Word)
Out
440
439
First
Data In
Bit
Last Bit
443
441
FSR (Bit)
In
442
443
FSR (Word)
In
444
445
Flags In
AA1688
Figure 2-10 BBP And SAP Receiver Timing
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Freescale Semiconductor, Inc.
Specifications
JTAG Port Timing
JTAG PORT TIMING
Table 2-14 JTAG Timing
Freescale Semiconductor, Inc...
Num
Characteristics
DSP_CLK
@ 58.8 MHz
Expression
Unit
Min
Max
1/(3 ´ TDC)
0.0
19.6
MHz
500
TCK frequency of operation
501
TCK cycle time in crystal mode
Ñ
45.0
Ñ
ns
502
TCK clock pulse width measured at 1.5 V
Ñ
20.0
Ñ
ns
503
TCK rise and fall times
Ñ
0.0
3.0
ns
504
Boundary scan input data setup time
Ñ
5.0
Ñ
ns
505
Boundary scan input data hold time
Ñ
24.0
Ñ
ns
506
TCK low to output data valid
Ñ
0.0
40.0
ns
507
TCK low to output high impedance
Ñ
0.0
40.0
ns
508
TMS, TDI data setup time
Ñ
5.0
Ñ
ns
509
TMS, TDI data hold time
Ñ
25.0
Ñ
ns
510
TCK low to TDO data valid
Ñ
0.0
44.0
ns
511
TCK low to TDO high impedance
Ñ
0.0
44.0
ns
512
TRST assert time
Ñ
100.0
Ñ
ns
513
TRST setup time to TCK low
Ñ
40.0
Ñ
ns
501
TCK
(Input)
VIH
502
502
VM
VM
VIL
503
503
AA0496
Figure 2-11 Test Clock Input Timing Diagram
Preliminary
2-18
DSP56652 Technical Data Sheet
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Freescale Semiconductor, Inc.
DSP56652
JTAG Port Timing
TCK
(Input)
VIH
VIL
504
Data
Inputs
505
Input Data Valid
506
Freescale Semiconductor, Inc...
Data
Outputs
Output Data Valid
507
Data
Outputs
506
Data
Outputs
Output Data Valid
AA0497
Figure 2-12 Boundary Scan (JTAG) Timing Diagram
TCK
(Input)
513
TRST
(Input)
AA1689
512
Figure 2-13 TRST Timing Diagram
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Freescale Semiconductor, Inc.
Specifications
JTAG Port Timing
TCK
(Input)
VIH
VIL
508
TDI
TMS
(Input)
509
Input Data Valid
510
TDO
(Output)
Output Data Valid
Freescale Semiconductor, Inc...
511
TDO
(Output)
510
TDO
(Output)
Output Data Valid
AA0498
Figure 2-14 Test Access Port Timing Diagram
Preliminary
2-20
DSP56652 Technical Data Sheet
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Freescale Semiconductor, Inc.
SECTION
3
PACKAGING
Freescale Semiconductor, Inc...
PACKAGE INFORMATION
This section provides information about the available packages for this product. The
DSP56652 is available in a 196-pin plastic ball grid array (PBGA) package.
The DSP56652 part (ROM-based DSP program memory) is delivered in a 15-mm
(outline) PBGA. Compatibility between the footprints of the package is maintained to
minimize impact to the customerÕs application board routing, such that the same
board can be used for both the DSP56651 and DSP56652.
196 PBGA (GT), 15 x 15 mm, 1-mm Pitch Solder Balls
The DSP56652 is offered in the JEDEC-standard, 15-mm PBGA with 1 mm pitch
solder balls. Refer to Figure 3-1 on page 3-3 and Table 3-1 for package drawing and
dimensions, respectively.
Preliminary
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3-1
Freescale Semiconductor, Inc.
Packaging
196 PBGA (GT), 15 x 15 mm, 1-mm Pitch Solder Balls
PBGA Package Dimensions
Table 3-1 Dimensions for 196 PBGA (15-mm outline)
Freescale Semiconductor, Inc...
MILLIMETERS
DIM
MIN
MAX
A
1.32
1.75
A1
0.27
0.47
A2
0.30
0.40
A3
0.75
0.88
b
0.35
0.65
D
15.00
BASIC
D1
13.00
BASIC
D2
12.00
BASIC
E
15.00
BASIC
E1
13.00
BASIC
E2
12.00
BASIC
e
1.00
BASIC
R1
Ñ
2.50
Preliminary
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DSP56652 Technical Data Sheet
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Freescale Semiconductor, Inc.
DSP56652
196 PBGA (GT), 15 x 15 mm, 1-mm Pitch Solder Balls
PBGA Package Mechanical Drawing
4X
B
D
A
0.2
Freescale Semiconductor, Inc...
C
0.15 C
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. DIMENSIONS IN MILLIMETERS.
3. DIMENSION b IS THE SOLDER BALL
DIAMETER MEASURED PARALLEL TO
DATUM C.
E
E2
0.45 C
MILLIMETERS
D2
TOP VIEW
D1
13X
e /2
P
N
M
L
K
J
H
G
F
E
D
C
B
A
e
E1
A2
A3
DIM
A
A1
A2
A3
b
D
D1
D2
E
E1
E2
e
MIN
MAX
1.75
1.32
0.27
0.47
0.30
0.40
0.75
0.88
0.35
0.65
15.00 BSC
13.00 BSC
12.00
15.00
15.00 BSC
13.00 BSC
12.00
15.00
1.00 BSC
A1
e /2
A
TOP VIEW
1 2 3 4 5 6 7 8 9 10 11 12 13 14
b
196X
0.3
C A B
0.1
C
BOTTOM VIEW
CASE 1128-01
Figure 3-1 DSP56652 Mechanical Information, 196-pin PBGA Package
Preliminary
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Freescale Semiconductor, Inc.
Packaging
Ordering Drawings
ORDERING DRAWINGS
Complete mechanical information regarding DSP56652 packaging is available by
facsimile through Motorola's Mfax system. Call the following number to obtain
information by facsimile:
(602) 244-6591
Freescale Semiconductor, Inc...
The Mfax automated system requests the following information:
¥
The receiving facsimile telephone number including area code or country code
¥
The callerÕs personal identification number (PIN)
Note: For first time callers, the system provides instructions for setting up a PIN,
which requires entry of a name and telephone number.
¥
The type of information requested:
Ð
Instructions for using the system
Ð
A literature order form
Ð
Specific part technical information or data sheets
Ð
Other information described by the system messages
A total of three documents may be ordered per call.
The DSP56652 196-pin PBGA package mechanical drawing is referenced as Case
1128-01 Rev. D.
Preliminary
3-4
DSP56652 Technical Data Sheet
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Freescale Semiconductor, Inc.
SECTION
4
DESIGN CONSIDERATIONS
Freescale Semiconductor, Inc...
HEAT DISSIPATION
An estimation of the chip junction temperature, TJ, in °C can be obtained from the
equation:
Equation 1: T J = T A + ( P D ´ R qJA )
Where:
TA = ambient temperature ûC
RqJA = package junction-to-ambient thermal resistance ûC/W
PD = power dissipation in package
Historically, thermal resistance has been expressed as the sum of a junction-to-case
thermal resistance and a case-to-ambient thermal resistance:
Equation 2: R qJA = R qJC + R qCA
Where:
RqJA = package junction-to-ambient thermal resistance ûC/W
RqJC = package junction-to-case thermal resistance ûC/W
RqCA = package case-to-ambient thermal resistance ûC/W
RqJC is device-related and cannot be influenced by the user. The user controls the
thermal environment to change the case-to-ambient thermal resistance, RqCA. For
example, the user can change the air flow around the device, add a heat sink, change
the mounting arrangement on the printed circuit board, or otherwise change the
thermal dissipation capability of the area surrounding the device on a printed circuit
board. This model is most useful for ceramic packages with heat sinks; ninety percent
of the heat flow is dissipated through the case to the heat sink and out to the ambient
environment. For ceramic packages, in situations where the heat flow is split between
a path to the case and an alternate path through the printed circuit board, analysis of
the device thermal performance may need the additional modeling capability of a
system level thermal simulation tool.
The thermal performance of plastic packages is more dependent on the temperature
of the printed circuit board to which the package is mounted. Again, if the
Preliminary
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Design Considerations
Heat Dissipation
estimations obtained from RqJA do not satisfactorily answer whether the thermal
performance is adequate, a system level model may be appropriate.
Freescale Semiconductor, Inc...
A complicating factor is the existence of three common ways for determining the
junction-to-case thermal resistance in plastic packages:
¥
To minimize temperature variation across the surface, the thermal resistance is
measured from the junction to the outside surface of the package (case) closest to the
chip mounting area when that surface has a proper heat sink.
¥
To define a value approximately equal to a junction-to-board thermal resistance, the
thermal resistance is measured from the junction to where the leads are attached to
the case.
¥
If the temperature of the package case (TT) as determined by a thermocouple, the
thermal resistance is computed using the value obtained by the equation (TJ - TT)/
PD.
As noted above, the junction-to-case thermal resistances quoted in this data sheet are
determined using the first definition. From a practical standpoint, this value is also
suitable for determining the junction temperature from a case thermocouple reading
in forced convection environments. In natural convection, using the junction-to-case
thermal resistance to estimate junction temperature from a thermocouple reading on
the case of the package will estimate a junction temperature slightly hotter than
actual temperature. Hence, the new thermal metric, thermal characterization
parameter or YJT, has been defined to be (TJ - TT)/PD. This value gives a better
estimate of the junction temperature in natural convection when using the surface
temperature of the package. Remember that surface temperature readings of
packages are subject to significant errors caused by inadequate attachment of the
sensor to the surface and to errors caused by heat loss to the sensor. The
recommended technique is to attach a 40-gauge thermocouple wire and bead to the
top center of the package with thermally conductive epoxy.
Note: Table 2-2 on page 2-2 of this document contains the package thermal values
for this chip.
Preliminary
4-2
DSP56652 Technical Data Sheet
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Freescale Semiconductor, Inc.
DSP56652
Electrical Design Considerations
ELECTRICAL DESIGN CONSIDERATIONS
Freescale Semiconductor, Inc...
CAUTION
This device contains protective circuitry to
guard against damage due to high static
voltage or electrical fields. However, normal
precautions are advised to avoid application
of any voltages higher than maximum rated
voltages to this high-impedance circuit.
Reliability of operation is enhanced if unused
inputs are tied to an appropriate logic voltage
level (e.g., either GND or VCC).
Use the following list of recommendations to assure correct DSP operation:
¥
Provide a low-impedance path from the board power supply to each VCC pin on the
DSP and from the board ground to each GND pin.
¥
Use at least four 0.1 mF bypass capacitors positioned as close as possible to the four
sides of the package to connect the VCC power source to GND.
¥
Ensure that capacitor leads and associated printed circuit traces that connect to the
chip VCC and GND pins are less than 0.5 inch per capacitor lead.
¥
Use at least a four-layer printed circuit board (PCB) with two inner layers for VCC
and GND.
¥
Because the DSP output signals have fast rise and fall times, PCB trace lengths should
be minimal. This recommendation particularly applies to the address and data buses
as well as the R/W, DSP_IRQ, and INT0ÐINT7 signals.
¥
Consider all device loads as well as parasitic capacitance due to PCB traces when
calculating capacitance. This is especially critical in systems with higher capacitive
loads that could create higher transient currents in the VCC and GND circuits.
¥
All inputs must be terminated (i.e., not allowed to float) using CMOS levels.
¥
Take special care to minimize noise levels on the PLL supply pins (both VCC and
GND).
Preliminary
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Freescale Semiconductor, Inc.
Design Considerations
Freescale Semiconductor, Inc...
Electrical Design Considerations
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4-4
DSP56652 Technical Data Sheet
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Freescale Semiconductor, Inc.
SECTION
5
ORDERING INFORMATION
Table 5-1 lists the pertinent information needed to place an order. Consult a Motorola
Semiconductor sales office or authorized distributor to determine availability and to
order parts.
Freescale Semiconductor, Inc...
Table 5-1 DSP56652 Ordering Information
Part
Supply
Voltage
DSP56652
3V
Package Type
Plastic ball grid array (PBGA)
Pin
Count
Order Number
196
Customer Specific
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5-1
Freescale Semiconductor, Inc.
Freescale Semiconductor, Inc...
Ordering information
Preliminary
5-2
DSP56652 Technical Data Sheet
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MOTOROLA
Freescale Semiconductor, Inc...
Freescale Semiconductor, Inc.
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Freescale Semiconductor, Inc.
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Freescale Semiconductor, Inc.
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Freescale Semiconductor, Inc...
Freescale Semiconductor, Inc.
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