19-2698; Rev 0; 1/03 2-Wire-Interfaced 8-Bit I/O Port Expander with Reset Features ♦ 400kHz 2-Wire Interface ♦ 2.3V to 5.5V Operation ♦ Low Standby Current (1.7µA typ) ♦ Bus Timeout for Lock-Up-Free Operation ♦ 56 Slave ID Addresses ♦ Polarity Inversion ♦ Eight I/O Pins that Default to Inputs on Power-Up ♦ 5V Tolerant Open-Drain Output on I/O0 ♦ 4mm x 4mm, 0.8mm Thin QFN Package ♦ -40°C to +125°C Operation Applications Ordering Information Servers PART TEMP RANGE RAID Systems MAX7310AUE -40°C to +125°C 16 TSSOP PIN-PACKAGE Industrial Control MAX7310AEE -40°C to +125°C 16 QSOP Medical Equipment MAX7310ATE -40°C to +125°C 16 Thin QFN Instrumentation, Test Measurement SMBus is a trademark of Intel Corp. 14 I/O7 13 I/O6 AD1 4 AD2 5 MAX7310 12 I/O5 I/O0 6 11 I/O4 I/O1 7 10 I/O3 GND 8 9 I/O2 TSSOP/QSOP V+ RESET 14 13 AD0 1 12 I/O7 AD1 2 11 I/O6 AD2 3 I/O0 4 MAX7310 10 I/O5 9 5 6 7 8 I/O3 15 RESET AD0 3 15 I/O2 SDA 2 16 GND 16 V+ I/01 SCL 1 SCL TOP VIEW SDA Pin Configurations I/O4 THIN QFN ________________________________________________________________ Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. 1 MAX7310 General Description The MAX7310 provides 8-bit parallel input/output port expansion for SMBus™-compatible and I2C-compatible applications. The MAX7310 consists of an input port register, an output port register, a polarity inversion register, a configuration register, a bus timeout register, and an SMBus/I2C-compatible serial interface. The system master can invert the MAX7310 input data by writing to the active-high polarity inversion register. The system master can enable or disable bus timeout by writing to the bus timeout register. Any of the eight I/O ports may be configured as input or output. An active-low reset input sets the eight I/Os as inputs. Three address select pins configure one of 56 slave ID addresses. The MAX7310 is available in 16-pin thin QFN, TSSOP, and QSOP packages and is specified over the -40°C to +125°C automotive temperature range. MAX7310 2-Wire-Interfaced 8-Bit I/O Port Expander with Reset ABSOLUTE MAXIMUM RATINGS V+ to GND ................................................................-0.3V to +6V I/O1–I/O7 as an Input .......................(VSS - 0.3V) to (VDD + 0.3V) I/O0 as an Input..............................................(VSS - 0.3V) to +6V SCL, SDA, AD0, AD1, AD2, RESET ...............(VSS - 0.3V) to +6V DC Current on I/O0 ........................................................ +400µA DC Current on I/O1 to I/O7 ............................................. ±50mA Maximum GND and V+ Current........................................180mA Continuous Power Dissipation (TA = +70°C) 16-Pin TSSOP (derate 5.7mW/°C above +70°C) .........457mW 16-Pin QSOP (derate 8.3mW/°C above +70°C)...........667mW 16-Pin Thin QFN (derate 16.9mW/°C above +70°C) ...1349mW Operating Temperature Range .........................-40°C to +125°C Junction Temperature ......................................................+150°C Storage Temperature Range .............................-65°C to +150°C Lead Temperature (soldering, 10s) .................................+300°C Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. DC ELECTRICAL CHARACTERISTICS (V+ = 2.3V to 5.5V, GND = 0, RESET = V+, TA = -40°C to +125°C, unless otherwise noted. Typical values are at V+ = 3.3V, TA = +25°C.) (Note 1) PARAMETER Supply Voltage Supply Current SYMBOL CONDITIONS V+ I+ Standby Current MIN TYP 2.3 MAX UNITS 5.5 V All outputs floating, all inputs at V+ or GND, fSCL = 400kHz V+ = 2.3V 19 30 V+ = 3.3V 29 40 V+ = 5.5V 65 80 All outputs floating, all inputs at V+ or GND, fSCL = 0 V+ = 2.3V 1.5 3.4 V+ = 3.3V 1.7 3.9 V+ = 5.5V Power-On Reset Voltage µA µA 2.1 5 1.6 2.1 V 0.8 V 0.4 V +1 µA SCL, SDA Input Voltage Low VIL Input Voltage High VIH Low-Level Output Voltage VOIL Leakage Current IL Input Capacitance CI 2 V ISINK = 6mA -1 10 pF I/Os Input Voltage Low VIL Input Voltage High VIH Input Leakage Current Low-Level Output Current High Output Current for I/O1–I/O7 IL IOL IOH 0.8 V +1 µA 2 All inputs at V+ or GND V -1 V+ = 2.3V, VOL = 0.5V 8 V+ = 3.3V, VOL = 0.5V 12.5 14 22 V+ = 5.5V, VOL = 0.5V 19 30 V+ = 3.3V, VOH = 2.4V 6.5 11 V+ = 5.5V, VOH = 4.5V 12.5 18 mA mA AD0, AD1, AD2, AND RESET Input Voltage Low Input Voltage High 2 0.8 2 _______________________________________________________________________________________ V V 2-Wire-Interfaced 8-Bit I/O Port Expander with Reset (V+ = 2.3V to 5.5V, GND = 0, RESET = V+, TA = -40°C to +125°C, unless otherwise noted. Typical values are at V+ = 3.3V, TA = +25°C.) (Note 1) PARAMETER SYMBOL CONDITIONS Leakage Current MIN TYP -1 Input Capacitance MAX UNITS +1 µA 10 pF AC ELECTRICAL CHARACTERISTICS (V+ = 2.3V to 5.5V, GND = 0, RESET = V+, TA = -40°C to +125°C, unless otherwise noted.) (Note 1) PARAMETER SCL Clock Frequency BUS Timeout SYMBOL fSCL CONDITIONS MIN TYP (Note 2) tTIMEOUT 30 MAX UNITS 400 kHz 60 ms Bus Free Time Between STOP and START Condition tBUF Figure 2 1.3 µs Hold Time (Repeated) START Condition tHD, STA Figure 2 0.6 µs Repeated START Condition Setup Time tSU, STA Figure 2 0.6 µs STOP Condition Setup Time tSU, STO Figure 2 0.6 Data Hold Time tHD, DAT Figure 2 (Note 3) Data Setup Time tSU, DAT Figure 2 0.1 µs SCL Low Period tLOW Figure 2 1.3 µs SCL High Period tHIGH Figure 2 0.7 SCL/SDA Fall Time (Transmitting) Pulse Width of Spike Supressed tF µs 0.9 µs µs Figure 2 (Note 4) 250 50 ns tSP (Note 5) ns Output Data Valid tPV Figure 9 Input Data Setup Time tPS Figure 10 29 µs Input Data Hold Time tPH Figure 10 0 µs 100 ns PORT TIMING 1 µs RESET Reset Pulse Width Note 1: All parameters are 100% production tested at TA = +25°C. Specifications over temperature are guaranteed by design. Note 2: Minimum SCL clock frequency is limited by the MAX7310 bus timeout feature, which resets the serial bus interface if either SDA or SCL is held low for a 30ms minimum. Note 3: A master device must internally provide a hold time of at least 300ns for the SDA signal (referred to the VIL of the SCL signal) in order to bridge the undefined region of SCL’s falling edge. Note 4: tF measured between 90% to 10% of V+. Note 5: Input filters on the SDA and SCL inputs suppress noise spikes less than 50ns. _______________________________________________________________________________________ 3 MAX7310 DC ELECTRICAL CHARACTERISTICS (continued) Typical Operating Characteristics (TA = +25°C, unless otherwise noted.) 30 29 28 27 V+ = 3.3V, fSCL = 0, NO LOAD ON I/O0–I/O7 60 2.00 1.75 1.50 fSCL = 440kHz, NO LOAD ON I/O0–I/O7 50 40 30 20 1.25 26 1.00 10 -40 -25 -10 5 20 35 50 65 80 95 110 125 -40 -25 -10 5 20 35 50 65 80 95 110 125 TEMPERATURE (°C) TEMPERATURE (°C) SUPPLY VOLTAGE (V) I/O0–I/O7 OUTPUT SINK CURRENT vs. TEMPERATURE I/O0–I/O7 OUTPUT SINK CURRENT vs. SUPPLY VOLTAGE I/O1–I/O7 OUTPUT SOURCE CURRENT vs. TEMPERATURE 30 10 25 20 15 10 3.0 3.5 4.0 4.5 V+ = 2.3V, VOH = 1.4V 8 SOURCE CURRENT (mA) VCC = 2.3V 15 SINK CURRENT (mA) VCC = 3.3V 20 9 2.5 5.0 5.5 MAX7310 toc06 25 2.0 MAX7310 toc05 35 MAX7310 toc04 30 7 6 5 5 5 VOL = 0.5V VOL = 0.5V 0 0 -40 -25 -10 5 20 35 50 65 80 95 110 125 TEMPERATURE (°C) 4 70 SUPPLY CURRENT (µA) 2.25 SUPPLY CURRENT (µA) SUPPLY CURRENT (µA) 31 2.50 SUPPLY CURRENT vs. SUPPLY VOLTAGE MAX7310 toc02 V+ = 3.3V, fSCL = 440kHz, NO LOAD ON I/O0–I/O7 MAX7310 toc01 32 STANDBY SUPPLY CURRENT vs. TEMPERATURE MAX7310 toc03 SUPPLY CURRENT vs. TEMPERATURE SINK CURRENT (mA) MAX7310 2-Wire-Interfaced 8-Bit I/O Port Expander with Reset 4 2.0 2.5 3.0 3.5 4.0 4.5 SUPPLY VOLTAGE (V) 5.0 5.5 -40 -25 -10 5 20 35 50 65 80 95 110 125 TEMPERATURE (°C) _______________________________________________________________________________________ 2-Wire-Interfaced 8-Bit I/O Port Expander with Reset PIN TSSOP/ QSOP THIN QFN NAME 1 15 SCL Serial Clock Line 2 16 SDA Serial Data Line 3 1 AD0 Address Input 0 4 2 AD1 Address Input 1 5 3 AD2 Address Input 2 6 4 I/O0 Input/Output Port 0 (Open Drain) 7 5 I/O1 Input/Output Port 1 8 6 GND Supply Ground 9–14 7–12 I/O2–I/O7 15 13 RESET 16 14 V+ FUNCTION Input/Output Port 2—Input/Output Port 7 External Reset (Active Low). Pull RESET low to configure I/O pins as inputs. Set RESET high for normal operation. Supply Voltage. Bypass with a 0.047µF capacitor to GND. AD0 AD1 MAX7310 AD2 SCL INPUT FILTER SDA SMBus CONTROL 8 BIT WRITE PULSE N READ PULSE INPUT/ OUTPUT PORTS I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 V+ RESET POWER-ON RESET GND Figure 1. MAX7310 Block Diagram Detailed Description The MAX7310 general-purpose input/output (GPIO) peripheral provides up to eight I/O ports, controlled through an I 2 C-compatible serial interface. The MAX7310 consists of an input port register, an output port register, a polarity inversion register, a configura- tion register, and a bus timeout register. An active-low reset input sets the eight I/O lines as inputs. Three slave ID address select pins (AD0, AD1, and AD2) choose one of 56 slave ID addresses (Figure 1). Table 1 is the register address table. Tables 2–6 list register 0 through register 4 information. _______________________________________________________________________________________________________ 5 MAX7310 Pin Description MAX7310 2-Wire-Interfaced 8-Bit I/O Port Expander with Reset Serial Interface Serial Addressing The MAX7310 operates as a slave that sends and receives data through a 2-wire interface. The interface uses a serial data line (SDA) and a serial clock line (SCL) to achieve bidirectional communication between master(s) and slave(s). A master, typically a microcontroller, initiates all data transfers to and from the MAX7310, and generates the SCL clock that synchronizes the data transfer (Figure 2). Each transmission consists of a start condition sent by a master, followed by the MAX7310 7-bit slave address plus an R/W bit, a register address byte, one or more data bytes, and finally a stop condition (Figure 3). Start and Stop Conditions Both SCL and SDA remain high when the interface is not busy. A master signals the beginning of a transmission with a start (S) condition by transitioning SDA from high to low while SCL is high. When the master has finished communicating with the slave, it issues a stop (P) condition by transitioning SDA from low to high while SCL is high. The bus is then free for another transmission (Figure 3). Bit Transfer One data bit is transferred during each clock pulse. The data on SDA must remain stable while SCL is high (Figure 4). Acknowledge The acknowledge bit is a clocked 9th bit, which the recipient uses as a handshake receipt of each byte of data (Figure 5). Thus, each byte transferred effectively requires 9 bits. The master generates the 9th clock pulse, and the recipient pulls down SDA during the acknowledge clock pulse, such that the SDA line is stable low during the high period of the clock pulse. When the master is transmitting to the MAX7310, the MAX7310 generates the acknowledge bit since the MAX7310 is the recipient. When the MAX7310 is transmitting to the master, the master generates the acknowledge bit. Slave Address The MAX7310 has a 7-bit-long slave address (Figure 6). The 8th bit following the 7-bit slave address is the R/W bit. Set this bit low for a write command and high for a read command. SDA tBUF tSU, STA tSU, DAT tHD, STA tLOW tSU, STO tHD, DAT SCL tHIGH tHD, STA tR tF REPEATED START CONDITION START CONDITION STOP CONDITION Figure 2. 2-Wire Serial Interface Timing Diagrams SDA SCL S P START CONDITION STOP CONDITION Figure 3. Start and Stop Conditions 6 _______________________________________________________________________________________ START CONDITION 2-Wire-Interfaced 8-Bit I/O Port Expander with Reset MAX7310 SDA SCL DATA LINE STABLE; DATA VALID CHANGE OF DATA ALLOWED Figure 4. Bit Transfer START CONDITION CLOCK PULSE FOR ACKNOWLEDGMENT SCL 1 2 8 9 SDA BY TRANSMITTER S SDA BY RECEIVER Figure 5. Acknowledge FIXED SDA PROGRAMMABLE A5 0 A4 A3 MSB A2 A1 A0 R/W ACK LSB SCL Figure 6. Slave Address The first bits (MSBs) of the MAX7310 slave address are always zero. Slave address bits AD2, AD1, and AD0 choose 1 of 56 slave ID addresses (Table 7). Registers The register address byte is the first byte to follow the address byte during a read/write transmission. The register address byte acts as a pointer to determine which register is written or read. The input port register is a read-only port. It reflects the incoming logic levels of the I/O ports, regardless of whether the pin is defined as an input or an output by _______________________________________________________________________________________ 7 MAX7310 2-Wire-Interfaced 8-Bit I/O Port Expander with Reset tion, not the actual I/O value, which may differ if the output is overloaded. Table 1. Register Address REGISTER ADDRESS (hex) FUNCTION The polarity inversion register enables polarity inversion of ports defined as inputs by the configuration register. Set the bit in the polarity inversion register (write with a 1) to invert the corresponding port pin’s polarity. Clear the bit in the polarity inversion register (write with a zero) to retain the corresponding port pin’s original polarity. The configuration register configures the directions of the ports. Set the bit in the configuration register to enable the corresponding port pin as an input with a high-impedance output driver. Clear the bit in the configuration register to enable the corresponding port pin as an output. PROTOCOL 0x00 Input port register 0x01 Output port register Read byte. Read/write byte. 0x02 Polarity inversion register Read/write byte. 0x03 Configuration register Read/write byte. 0x04 Timeout register Read/write byte. 0xFF Reserved register Factory reserved. Do not write to this register. the configuration register. Writes to the input port register are ignored. Set bit T0 to enable the bus timeout function and low to disable the bus timeout function. Enabling the timeout feature resets the serial bus interface when SCL stops either high or low during a read or write access to the MAX7310. If either SCL or SDA is low for more than 30ms min and 60ms max after the start of a valid serial transfer, the interface resets itself. Resetting the serial bus interface sets up SDA as an input. The MAX7310 then waits for another start condition. The output port register sets the outgoing logic levels of the I/O ports, defined as outputs by the configuration register. Reads from the output port register reflect the value that is in the flip-flop controlling the output selec- The MAX7310 goes into standby when all pins are set to V+ or GND. Standby supply current is typically 1.7µA. Table 2. Register 0—Input Port Register BIT I7 I6 I5 I4 I3 I2 I1 I0 Standby Table 3. Register 1—Output Port Register BIT O7 O6 O5 O4 O3 O2 O1 O0 Default 0 0 0 0 0 0 0 0 Table 4. Register 2—Polarity Inversion Register BIT I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 I/O0 Default 1 1 1 1 0 0 0 0 Table 5. Register 3—Configuration Register BIT I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 I/O0 Default 1 1 1 1 1 1 1 1 Table 6. Register 4—Timeout Register 8 BIT T7 T6 T5 T4 T3 T2 T1 T0 Default x x x x x x x 1 _______________________________________________________________________________________ 2-Wire-Interfaced 8-Bit I/O Port Expander with Reset MAX7310 Table 7. MAX7310 Address Map AD2 AD1 AD0 A6 A5 A4 A3 A2 A1 A0 GND SCL GND 0 0 0 1 0 0 0 GND SCL V+ 0 0 0 1 0 0 1 GND SDA GND 0 0 0 1 0 1 0 GND SDA V+ 0 0 0 1 0 1 1 V+ SCL GND 0 0 0 1 1 0 0 V+ SCL V+ 0 0 0 1 1 0 1 V+ SDA GND 0 0 0 1 1 1 0 V+ SDA V+ 0 0 0 1 1 1 1 GND GND SCL 0 0 1 0 0 0 0 GND GND SDA 0 0 1 0 0 0 1 GND V+ SCL 0 0 1 0 0 1 0 GND V+ SDA 0 0 1 0 0 1 1 V+ GND SCL 0 0 1 0 1 0 0 V+ GND SDA 0 0 1 0 1 0 1 V+ V+ SCL 0 0 1 0 1 1 0 V+ V+ SDA 0 0 1 0 1 1 1 GND GND GND 0 0 1 1 0 0 0 GND GND V+ 0 0 1 1 0 0 1 GND V+ GND 0 0 1 1 0 1 0 GND V+ V+ 0 0 1 1 0 1 1 V+ GND GND 0 0 1 1 1 0 0 V+ GND V+ 0 0 1 1 1 0 1 V+ V+ GND 0 0 1 1 1 1 0 V+ V+ V+ 0 0 1 1 1 1 1 SCL SCL SCL 0 1 0 0 0 0 0 SCL SCL SDA 0 1 0 0 0 0 1 SCL SDA SCL 0 1 0 0 0 1 0 SCL SDA SDA 0 1 0 0 0 1 1 SDA SCL SCL 0 1 0 0 1 0 0 SDA SCL SDA 0 1 0 0 1 0 1 SDA SDA SCL 0 1 0 0 1 1 0 SDA SDA SDA 0 1 0 0 1 1 1 SCL SCL GND 0 1 0 1 0 0 0 SCL SCL V+ 0 1 0 1 0 0 1 SCL SDA GND 0 1 0 1 0 1 0 SCL SDA V+ 0 1 0 1 0 1 1 SDA SCL GND 0 1 0 1 1 0 0 SDA SCL V+ 0 1 0 1 1 0 1 SDA SDA GND 0 1 0 1 1 1 0 SDA SDA V+ 0 1 0 1 1 1 1 _______________________________________________________________________________________ 9 MAX7310 2-Wire-Interfaced 8-Bit I/O Port Expander with Reset Table 7. MAX7310 Address Map (continued) AD2 AD1 AD0 A6 A5 A4 A3 A2 A1 A0 SCL GND SCL 0 1 1 0 0 0 0 SCL GND SDA 0 1 1 0 0 0 1 SCL V+ SCL 0 1 1 0 0 1 0 SCL V+ SDA 0 1 1 0 0 1 1 SDA GND SCL 0 1 1 0 1 0 0 SDA GND SDA 0 1 1 0 1 0 1 SDA V+ SCL 0 1 1 0 1 1 0 SDA V+ SDA 0 1 1 0 1 1 1 SCL GND GND 0 1 1 1 0 0 0 SCL GND V+ 0 1 1 1 0 0 1 SCL V+ GND 0 1 1 1 0 1 0 SCL V+ V+ 0 1 1 1 0 1 1 SDA GND GND 0 1 1 1 1 0 0 SDA GND V+ 0 1 1 1 1 0 1 SDA V+ GND 0 1 1 1 1 1 0 SDA V+ V+ 0 1 1 1 1 1 1 Applications Information Power-Supply Consideration The MAX7310 operates from a supply voltage of 2.3V to 5.5V. Bypass the power supply to GND with a 0.047µF capacitor as close to the device as possible. 10 Chip Information TRANSISTOR COUNT: 10,256 PROCESS: BiCMOS ______________________________________________________________________________________ 2-Wire-Interfaced 8-Bit I/O Port Expander with Reset DATA FROM SHIFT REGISTER CONFIGURATION REGISTER D Q OUTPUT PORT REGISTER DATA FF Q D WRITE CONFIGURATION PULSE MAX7310 DATA FROM SHIFT REGISTER CK Q WRITE PULSE I/O0 FF CK Q OUTPUT PORT REGISTER ESD-PROTECTION DIODE GND INPUT PORT REGISTER D Q FF READ PULSE DATA FROM SHIFT REGISTER CK Q D Q INPUT PORT REGISTER DATA POLARITY REGISTER DATA FF WRITE POLARITY PULSE CK Q POLARITY INVERSION REGISTER Figure 7. Simplified Schematic of I/O0 ______________________________________________________________________________________ 11 MAX7310 2-Wire-Interfaced 8-Bit I/O Port Expander with Reset DATA FROM SHIFT REGISTER DATA FROM SHIFT REGISTER OUTPUT PORT REGISTER DATA CONFIGURATION REGISTER D V+ Q ESD-PROTECTION DIODE FF WRITE CONFIGURATION PULSE CK Q WRITE PULSE D Q I/O1 TO I/O7 FF CK Q ESD-PROTECTION DIODE OUTPUT PORT REGISTER INPUT PORT REGISTER D Q FF READ PULSE DATA FROM SHIFT REGISTER CK Q D Q FF WRITE POLARITY PULSE CK Q POLARITY INVERSION REGISTER Figure 8. Simplified Schematic of I/O1–I/O7 12 ______________________________________________________________________________________ GND INPUT PORT REGISTER DATA POLARITY REGISTER DATA 2-Wire-Interfaced 8-Bit I/O Port Expander with Reset 1 2 3 4 5 6 7 9 8 COMMAND BYTE SLAVE ADDRESS SDA S 0 A5 A4 A3 A2 A1 A0 START CONDITION MAX7310 SCL 0 A 0 0 0 0 0 0 DATA TO PORT 0 R/W ACKNOWLEDGE FROM SLAVE 1 A A DATA 1 ACKNOWLEDGE FROM SLAVE P ACKNOWLEDGE FROM SLAVE WRITE TO PORT DATA OUT FROM PORT DATA 1 VALID tPV Figure 9. Write to Output Port Register Through Write-Byte Protocol DATA FROM PORT SLAVE ADDRESS SDA S1 0 A5 START CONDITION A4 A3 A2 A1 A0 1 R/W DATA FROM PORT DATA 1 A A ACKNOWLEDGE FROM SLAVE DATA 4 ACKNOWLEDGE FROM MASTER NA NO ACKNOWLEDGE FROM MASTER P STOP CONDITION WRITE FROM PORT DATA INTO PORT DATA 2 tPH DATA 3 DATA 4 tPS NOTE 1: THIS FIGURE ASSUMES THE COMMAND HAS PREVIOUSLY BEEN PROGRAMMED WITH 0x00. NOTE 2: TRANSFER OF DATA CAN BE STOPPED AT ANY MOMENT BY A STOP CONDITION. WHEN THIS OCCURS, DATA PRESENT AT THE LAST ACKNOWLEDGED PHASE IS VALID (OUTPUT MODE). INPUT DATA IS LOST. Figure 10. Read Input Port Register Through Receive-Byte Protocol ______________________________________________________________________________________ 13 Package Information (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.) 24L QFN THIN.EPS MAX7310 2-Wire-Interfaced 8-Bit I/O Port Expander with Reset PACKAGE OUTLINE 12,16,20,24L QFN THIN, 4x4x0.8 mm 21-0139 14 ______________________________________________________________________________________ A 2-Wire-Interfaced 8-Bit I/O Port Expander with Reset PACKAGE OUTLINE 12,16,20,24L QFN THIN, 4x4x0.8 mm 21-0139 A ______________________________________________________________________________________ 15 MAX7310 Package Information (continued) (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.) Package Information (continued) (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.) TSSOP4.40mm.EPS MAX7310 2-Wire-Interfaced 8-Bit I/O Port Expander with Reset 16 ______________________________________________________________________________________ 2-Wire-Interfaced 8-Bit I/O Port Expander with Reset QSOP.EPS Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 17 © 2003 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products. MAX7310 Package Information (continued) (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.)