INTEGRATED CIRCUITS PCA9557 8-bit I2C and SMBus I/0 port with reset Product data File under Integrated Circuits — ICL03 2001 Dec 12 Philips Semiconductors Product data 8-bit I2C and SMBus I/0 port with reset PCA9557 The system master can also invert the PCA9557 inputs by writing to the active HIGH polarity inversion register. Finally, the system master can reset the PCA9557 in the event of a timeout by asserting a LOW in the reset input. The power-on reset puts the registers in their default state and initializes the I2C/SMBus state machine. The RESET pin causes the same reset/initialization to occur without depowering the part. PIN CONFIGURATION FEATURES • Lower voltage, higher performance migration path for the SCL 1 PCA9556 SDA • 8 general purpose input/output expander/collector • Input/output configuration register • Active HIGH polarity inversion register • I2C and SMBus interface logic • Internal power-on reset • Noise filter on SCL/SDA inputs • Active LOW reset input • 3 address pins allowing up to 8 devices on the I2C/SMBus • High impedance open drain on I/O0 • No glitch on power-up • Power-up with all channels configured as inputs • Low standby current • Operating power supply voltage range of 2.3 V to 5.5 V • 5 V tolerant inputs/outputs • 0 to 400 kHz clock frequency • ESD protection exceeds 2000 V HBM per JESD22-A114, 2 16 VDD 15 RESET A0 3 14 I/O7 A1 4 13 I/O6 A2 5 12 I/O5 I/O0 6 11 I/O4 I/O1 7 10 I/O3 VSS 8 9 I/O2 su01045 Figure 1. Pin configuration PIN DESCRIPTION PIN NUMBER 200 V MM per JESD22-A115 and 1000 V CDM per JESD22-C101 • Latch-up testing is done to JESDEC Standard JESD78 which exceeds 100 mA • Package offer: SO 16, TSSOP 16 SYMBOL FUNCTION 1 SCL Serial clock line 2 SDA Serial data line 3 A0 Address input 0 4 A1 Address input 1 5 A2 Address input 2 6 I/O0 I/O0 (open drain) 7 I/O1 I/O1 8 VSS Supply ground 9 I/O2 I/O2 10 I/O3 I/O3 DESCRIPTION 11 I/O4 I/O4 The PCA9557 is a silicon CMOS circuit which provides parallel input/output expansion for SMBus and I2C applications. The PCA9557 consists of an 8-bit input port register, 8-bit output port register, and an I2C/SMBus interface. It has low current consumption and a high impedance open drain output pin, I/O0. 12 I/O5 I/O5 13 I/O6 I/O6 14 I/O7 I/O7 15 RESET The system master can enable the PCA9557’s I/O as either input or output by writing to the configuration register. 16 VDD Active low reset input Supply voltage ORDERING INFORMATION PACKAGES TEMPERATURE RANGE ORDER CODE DRAWING NUMBER 16-Pin Plastic SO (narrow) –40 to +85 °C PCA9557D SOT109-1 16-Pin Plastic TSSOP –40 to +85 °C PCA9557PW Standard packing quantities and other packaging data is available at www.philipslogic.com/packaging. SMBus as specified by the Smart Battery System Implementers Forum is a derivative of the Philips I2C patent. I2C is a trademark of Philips Semiconductors Corporation. 2001 Dec 12 2 SOT403-1 853-2308 27449 Philips Semiconductors Product data 8-bit I2C and SMBus I/0 port with reset PCA9557 BLOCK DIAGRAM PCA9557 A0 A1 I/O0 A2 I/O1 SCL SDA I/O2 INPUT FILTER INPUT/ OUTPUT PORTS 8-BIT I2C/SMBus CONTROL I/O3 I/O4 WRITE pulse I/O5 READ pulse I/O6 I/O7 VDD VSS POWER-ON RESET RESET SW00827 Figure 2. Block diagram SYSTEM DIAGRAM Input Port VCC= 16 GND = 8 Polarity Inversion Configuration Output Port 1.1 KΩ Q7 Q7 Q7 Q7 I/O0 Q6 Q6 Q6 Q6 I/O1 Q5 Q5 Q5 Q5 I/O2 Q4 Q4 Q4 Q4 I/O3 Q3 Q3 Q3 Q3 I/O4 Q2 Q2 Q2 Q2 I/O5 Q1 Q1 Q1 Q1 I/O6 Q0 Q0 Q0 Q0 I/O7 1.1 KΩ 15 7 RESET 1.6 KΩ 1 SCL 2 SDA 1.6 KΩ 5 A2 4 A1 3 6 A0 or or or 1.1 KΩ 1.1 KΩ 1.1 KΩ I2C/SMBus Interface logic SW00794 Figure 3. System diagram 2001 Dec 12 3 9 10 11 12 13 14 Philips Semiconductors Product data 8-bit I2C and SMBus I/0 port with reset PCA9557 SIMPLIFIED SCHEMATIC OF I/O0 DATA FROM SHIFT REGISTER CONFIGURATION REGISTER DATA FROM SHIFT REGISTER Q D OUTPUT PORT REGISTER DATA FF WRITE CONFIGURATION PULSE CK Q D Q FF I/O0 WRITE PULSE CK Q ESD PROTECTION DIODE OUTPUT PORT REGISTER INPUT PORT REGISTER D Q VSS INPUT PORT REGISTER DATA FF READ PULSE CK DATA FROM SHIFT REGISTER D Q Q POLARITY REGISTER DATA FF WRITE POLARITY PULSE CK Q POLARITY INVERSION REGISTER SW00795 NOTE: On power–up or reset, all registers return to default values. Figure 4. Simplified schematic of I/O0 2001 Dec 12 4 Philips Semiconductors Product data 8-bit I2C and SMBus I/0 port with reset PCA9557 SIMPLIFIED SCHEMATIC OF I/O1 TO I/O7 DATA FROM SHIFT REGISTER OUTPUT PORT REGISTER DATA CONFIGURATION REGISTER DATA FROM SHIFT REGISTER VDD Q D ESD PROTECTION DIODE FF WRITE CONFIGURATION PULSE CK Q D Q FF I/O1 TO I/O7 WRITE PULSE CK Q ESD PROTECTION DIODE OUTPUT PORT REGISTER INPUT PORT REGISTER D Q VSS INPUT PORT REGISTER DATA FF Q CK READ PULSE DATA FROM SHIFT REGISTER D Q POLARITY REGISTER DATA FF WRITE POLARITY PULSE CK Q POLARITY INVERSION REGISTER NOTE: On power–up or reset, all registers return to default values. Figure 5. Simplified schematic of I/O1 to I/O7 2001 Dec 12 5 SW00796 Philips Semiconductors Product data 8-bit I2C and SMBus I/0 port with reset PCA9557 DEVICE ADDRESS Register 1 – Output Port Register Following a START condition the bus master must output the address of the slave it is accessing. The address of the PCA9557 is shown in Figure 6. To conserve power, no internal pullup resistors are incorporated on the hardware selectable address pins and they must be pulled HIGH or LOW. 0 1 1 A2 fixed A1 O7 O6 O5 O4 O3 O2 O1 O0 default 0 0 0 0 0 0 0 0 This register reflects the outgoing logic levels of the pins defined as outputs by the Configuration Register. Bit values in this register have no effect on pins defined as inputs. In turn, reads from this register reflect the value that is in the flip-flop controlling the output selection, NOT the actual pin value. slave address 0 bit Register 2 – Polarity Inversion Register A0 R/W bit N7 N6 N5 N4 N3 N2 N1 N0 default 1 1 1 1 0 0 0 0 programmable su01048 Figure 6. PCA9557 address The last bit of the slave address defines the operation to be performed. When set to logic 1 a read is selected while a logic 0 selects a write operation. This register enables polarity inversion of pins defined as inputs by the Configuration Register. If a bit in this register is set (written with ‘1’), the corresponding port pin’s polarity is inverted. If a bit in this register is cleared (written with a ‘0’), the corresponding port pin’s original polarity is retained. CONTROL REGISTER Register 3 – Configuration Register Following the successful acknowledgement of the slave address, the bus master will send a byte to the PCA9557, which will be stored in the control register. This register can be written and read via the I2C bus. 0 0 0 0 0 0 D1 bit C7 C6 C5 C4 C3 C2 C1 C0 default 1 1 1 1 1 1 1 1 This register configures the directions of the I/O pins. If a bit in this register is set, the corresponding port pin is enabled as an input with high impedance output driver. If a bit in this register is cleared, the corresponding port pin is enabled as an output. D0 POWER-ON RESET SW00953 When power is applied to VDD, an internal power-on reset holds the PCA9557 in a reset state until VDD has reached VPOR. At that point, the reset condition is released and the PCA9557 registers and I2C/SMBus state machine will initialize to their default states. Figure 7. Control Register For a power reset cycle, VDD must be set to 0 V, then ramped back to the operating voltage. REGISTER DEFINITION D1 D0 NAME TYPE FUNCTION 0 0 Register 0 Read Input port register RESET INPUT 0 1 Register 1 Read/Write Output port register 1 0 Register 2 Read/Write Polarity inversion register 1 1 Register 3 Read/Write Configuration register A reset can be accomplished by holding the RESET pin LOW for a minimum of tW. The PCA9557 registers and SMBus/I2C state machine will be held in their default state until the RESET input is once again HIGH. This input typically requires a pull-up to VCC. REGISTER DESCRIPTION Register 0 – Input Port Register I7 I6 I5 I4 I3 I2 I1 I0 This register is an read-only port. It reflects the incoming logic levels of the pins, regardless of whether the pin is defined as an input or an output by the Configuration Register. Writes to this register have no effect. 2001 Dec 12 6 Philips Semiconductors Product data 8-bit I2C and SMBus I/0 port with reset PCA9557 CHARACTERISTICS OF THE I2C-BUS Start and stop conditions The I2C-bus is for 2-way, 2-line communication between different ICs or modules. The two lines are a serial data line (SDA) and a serial clock line (SCL). Both lines must be connected to a positive supply via a pull-up resistor when connected to the output stages of a device. Data transfer may be initiated only when the bus is not busy. Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW transition of the data line, while the clock is HIGH is defined as the start condition (S). A LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the stop condition (P) (see Figure 9). Bit transfer System configuration One data bit is transferred during each clock pulse. The data on the SDA line must remain stable during the HIGH period of the clock pulse as changes in the data line at this time will be interpreted as control signals (see Figure 8). A device generating a message is a ‘transmitter’, a device receiving is the ‘receiver’. The device that controls the message is the ‘master’ and the devices which are controlled by the master are the ‘slaves’ (see Figure 10). SDA SCL data line stable; data valid change of data allowed SW00363 Figure 8. Bit transfer SDA SDA SCL SCL S P START condition STOP condition SW00365 Figure 9. Definition of start and stop conditions SDA SCL MASTER TRANSMITTER/ RECEIVER SLAVE RECEIVER SLAVE TRANSMITTER/ RECEIVER MASTER TRANSMITTER MASTER TRANSMITTER/ RECEIVER I2C MULTIPLEXER SLAVE SW00366 Figure 10. System configuration 2001 Dec 12 7 Philips Semiconductors Product data 8-bit I2C and SMBus I/0 port with reset PCA9557 Acknowledge The number of data bytes transferred between the start and the stop conditions from transmitter to receiver is not limited. Each byte of eight bits is followed by one acknowledge bit. The acknowledge bit is a HIGH level put on the bus by the transmitter whereas the master generates an extra acknowledge related clock pulse. A slave receiver which is addressed must generate an acknowledge after the reception of each byte. Also a master must generate an acknowledge after the reception of each byte that has been clocked out of the slave transmitter. The device that acknowledges has to pull down the SDA line during the acknowledge clock pulse, so that the SDA line is stable LOW during the HIGH period of the acknowledge related clock pulse, set-up and hold times must be taken into account. A master receiver must signal an end of data to the transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave. In this event, the transmitter must leave the data line HIGH to enable the master to generate a stop condition. DATA OUTPUT BY TRANSMITTER not acknowledge DATA OUTPUT BY RECEIVER acknowledge SCL FROM MASTER 1 2 8 9 S clock pulse for acknowledgement START condition SW00368 Figure 11. Acknowledgement on the 2001 Dec 12 8 I2C-bus Philips Semiconductors Product data 8-bit I2C and SMBus I/0 port with reset PCA9557 Bus Transactions Data is transmitted to the PCA9557 registers using Write Byte transfers (see Figures 12 and 13). Data is read from the PCA9557 registers using Read and Receive Byte transfers (see Figures 14 and 15). 1 SCL 2 3 4 5 6 7 8 9 command byte slave address SDA S 0 0 1 1 A2 A1 A0 start condition 0 A R/W 0 0 0 0 0 data to port 0 0 DATA 1 A 1 acknowledge from slave A acknowledge from slave P acknowledge from slave WRITE TO PORT DATA OUT FROM PORT DATA 1 VALID tpv SW00797 Figure 12. WRITE to output port register 1 SCL 2 3 4 5 6 7 8 9 command byte slave address SDA S 0 0 1 1 A2 start condition A1 A0 0 R/W A 0 0 0 0 0 data to register 0 1 1/0 acknowledge from slave DATA A A acknowledge from slave P acknowledge from slave SW00798 Figure 13. WRITE to I/O configuration or polarity inversion registers slave address S 0 0 1 1 acknowledge from slave A2 A1 A0 0 A acknowledge from slave COMMAND BYTE A S slave address 0 0 1 1 acknowledge from slave A2 A1 A0 R/W 1 R/W data from register acknowledge from master DATA A A first byte at this moment master-transmitter becomes master-receiver and slave-receiver becomes slave-transmitter data from register DATA no acknowledge from master NA P last byte su01052 Figure 14. READ from register 2001 Dec 12 9 Philips Semiconductors Product data 8-bit I2C and SMBus I/0 port with reset PCA9557 slave address SDA S 0 0 1 1 A2 start condition data from port A1 A0 1 R/W data from port DATA 1 A DATA 4 A acknowledge from slave acknowledge from master NA no acknowledge from master P stop condition READ FROM PORT DATA INTO PORT DATA 2 DATA 3 DATA 4 tph tps SW00799 NOTES: 1. This figure assumes the command byte has previously been programmed with 00h. 2. Transfer of data can be stopped at any moment by a stop condition. When this occurs, data present at the last acknowledge phase is valid (output mode). Input data is lost. Figure 15. READ input port register TYPICAL APPLICATION VDD 2 kΩ VDD 1.6 kΩ 1.6 kΩ 1.1 kΩ 2 kΩ VDD MASTER CONTROLLER SCL SCL SDA SDA SUBSYSTEM 1 (e.g. temp sensor) I/00 INT I/01 RESET RESET I/02 RESET GND I/03 PCA9557 SUBSYSTEM 2 (e.g. counter) I/04 I/05 A2 A Controlled Switch (e.g. CBT device) I/06 ENABLE A1 I/07 B A0 GND ALARM SUBSYSTEM 3 (e.g. alarm system) NOTE: Device address configured as 0011100 for this example I/00, I/01, I/02, configured as outputs I/03, I/04, I/05, configured as inputs I/006, I/07, are not used and have to be configured as outputs VDD SW00993 Figure 16. Typical application 2001 Dec 12 10 Philips Semiconductors Product data 8-bit I2C and SMBus I/0 port with reset PCA9557 ABSOLUTE MAXIMUM RATINGS In accordance with the Absolute Maximum Rating System (IEC 134). PARAMETER SYMBOL VDD CONDITIONS DC supply voltage MIN MAX UNIT –0.5 +6 V VI DC input voltage VSS – 0.5 5.5 V II DC input current — ± 20 mA — ±400 µA IIHL(max) Maximum allowed input current through protection diode (I/O1 – I/O7) VI ≥ VDD or VI ≤ VSS VI/O DC voltage on an I/O as an input other than I/O0 VSS – 0.5 5.5 V VI/O0 DC voltage on I/O0 as an input VSS – 0.5 5.5 V — +400 II/O0 /O DC input current on I/O0 µA — –20 mA II/O DC output current on an I/O — ± 50 mA IDD DC supply current — 85 mA ISS DC supply current — 100 mA Ptot Total power dissipation — 200 mW Tstg Storage temperature range –65 +150 °C Tamb Operating ambient temperature –40 +85 °C HANDLING Inputs and outputs are protected against electrostatic discharge in normal handling. However, to be totally safe, it is desirable to take precautions appropriate to handling MOS devices. Advice can be found in Data Handbook IC24 under ”Handling MOS devices”. 2001 Dec 12 11 Philips Semiconductors Product data 8-bit I2C and SMBus I/0 port with reset PCA9557 DC CHARACTERISTICS VDD = 2.3 to 5.5 V; VSS = 0 V; Tamb = –40 to +85 °C; unless otherwise specified. LIMITS SYMBOL PARAMETER CONDITIONS UNIT MIN TYP MAX 2.3 — 5.5 V Supplies VDD Supply voltage IDD Supply current Operating mode; VDD = 3.6 V; no load; VI = VDD or VSS; fSCL = 100 kHz — — 1 µA Istbl Standby current Standby mode; VDD = 5.5 V; no load; VI = VSS; fSCL = 0 kHz; I/O = inputs — — 1 µA Istbh Standby current Standby mode; VDD = 5.5 V; no load; VI = VDD; fSCL = 0 kHz; I/O = inputs — — 1 µA Power-on reset voltage No load; Temp = 25 °C VI = VDD or VSS — 1.65 — V VPOR Input SCL; input/output SDA VIL LOW level input voltage –0.5 — 0.3 VDD V VIH HIGH level input voltage 0.7 VDD — 5.5 V IOL LOW level output current VOL = 0.4 V 3 — — mA IL Leakage current VI = VDD or VSS –1 — +1 µA CI Input capacitance VI = VSS — 6 10 pF VIL LOW level input voltage –0.5 — 0.8 V VIH HIGH level input voltage 2.0 — 5.5 V IOL LOW level output current VOL = 0.55 V; note 1 8 10 — mA HIGH level output current except I/O0 VOH = 2.4 V; note 2 4 — — mA VOH = 4.6 V — — 1 VOH = 3.3 V — — 1 VDD = 5.5 V, VI = VSS I/Os IOH HIGH level output current on I/O0 µA IL Input leakage current — — –100 µA CI Input capacitance — 3.7 5 pF CO Output capacitance — 3.7 5 pF Select Inputs A0, A1, A2, and RESET VIL LOW level input voltage –0.5 — 0.8 V VIH HIGH level input voltage 2.0 — 5.5 V –1 — 1 µA ILI Input leakage current NOTES: 1. The total amount sunk by all I/Os must be limited to 100 mA and 25 mA per bit. 2. The total current sourced by all I/Os must be limited to 85 mA and 20 mA per bit. 2001 Dec 12 12 Philips Semiconductors Product data 8-bit I2C and SMBus I/0 port with reset PCA9557 AC SPECIFICATIONS SYMBOL STANDARD MODE I2C BUS PARAMETER fSCL Operating frequency tBUF FAST MODE I2C BUS UNITS MIN MAX MIN MAX 0 100 0 400 kHz Bus free time between STOP and START conditions 4.7 — 1.3 — µs tHD;STA Hold time after (repeated) START condition 4.0 — 0.6 — µs tSU;STA Repeated START condition setup time 4.7 — 0.6 — µs tSU;STO Setup time for STOP condition 4.0 — 0.6 — µs tHD;DAT Data in hold time 0 — 0 — ns — 1 — 0.9 µs — 1 — 0.9 µs condition2 tVD;ACK Valid time for ACK tVD;DAT Data out valid time3 tSU;DAT Data setup time 250 — 100 — ns tLOW Clock LOW period 4.7 — 1.3 — µs tHIGH Clock HIGH period 4.0 — 0.6 — µs tF Clock/Data fall time — 300 20 + 0.1 Cb1 300 ns 1 tR tSP Clock/Data rise time Pulse width of spikes that must be suppressed by the input filters — 1000 20 + 0.1 Cb 300 ns — 50 — 50 ns Port Timing tPV Output data valid I/O0 — 250 — 250 ns tPV Output data valid I/O1 – I/O7 — 200 — 200 ns tPS Input data setup time 0 — 0 — ns tPH Input data hold time 200 — 200 — ns 4 — 4 — ns 0 — 0 — ns 400 — 400 — ns Reset tW Reset pulse width tREC Reset recovery time tRESET Time to reset NOTES: 1. Cb = total capacitance of one bus line in pF. 2. tVD;ACK = time for Acknowledgement signal from SCL low to SDA (out) low. 3. tVD;DAT = minimum time for SDA data out to be valid following SCL low. SDA tBUF tLOW tR tF tHD;STA tSP SCL tHD;STA P S tSU;STA tHD;DAT tHIGH tSU;DAT Sr tSU;STO P SU00645 Figure 17. Definition of timing on the 2001 Dec 12 13 I2C-bus Philips Semiconductors Product data 8-bit I2C and SMBus I/0 port with reset PCA9557 SO16: plastic small outline package; 16 leads; body width 3.9 mm 2001 Dec 12 14 SOT109-1 Philips Semiconductors Product data 8-bit I2C and SMBus I/0 port with reset PCA9557 TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm 2001 Dec 12 15 SOT403-1 Philips Semiconductors Product data 8-bit I2C and SMBus I/0 port with reset PCA9557 Purchase of Philips I2C components conveys a license under the Philips’ I2C patent to use the components in the I2C system provided the system conforms to the I2C specifications defined by Philips. This specification can be ordered using the code 9398 393 40011. Data sheet status Data sheet status [1] Product status [2] Definitions Objective data Development This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. Preliminary data Qualification This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. Product data Production This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Changes will be communicated according to the Customer Product/Process Change Notification (CPCN) procedure SNW-SQ-650A. [1] Please consult the most recently issued data sheet before initiating or completing a design. [2] The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. Definitions Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Disclaimers Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes — Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Koninklijke Philips Electronics N.V. 2001 All rights reserved. Printed in U.S.A. Contact information For additional information please visit http://www.semiconductors.philips.com. Fax: +31 40 27 24825 Date of release: 12-01 For sales offices addresses send e-mail to: [email protected]. Document order number: 2001 Dec 12 16 9397 750 09217