MAXIM MAX7300AAI

19-2413; Rev 1; 2/03
2-Wire-Interfaced, 2.5V to 5.5V, 20-Port or
28-Port I/O Expander
Applications
White Goods
Industrial Controllers
Automotive
System Monitoring
Features
♦ 400kbps I C-Compatible Serial Interface
2
♦ 2.5V to 5.5V Operation
♦ -40°C to +125°C Temperature Range
♦ 20 or 28 I/O Ports, Each Configurable as
Push-Pull Logic Output
Schmitt Logic Input
Schmitt Logic Input with Internal Pullup
♦ 11µA (max) Shutdown Current
♦ Logic Transition Detection for Seven I/O Ports
Ordering Information
PART
TEMP RANGE
PIN-PACKAGE
MAX7300ANI
-40°C to +125°C
28 DIP
MAX7300AAI
-40°C to +125°C
28 SSOP
MAX7300AAX
-40°C to +125°C
36 SSOP
MAX7300AGL
-40°C to +125°C
40 QFN
Typical Operating Circuit
Pin Configurations
3V
36 V+
TOP VIEW
47nF
ISET 1
28 V+
GND 2
27 AD1
GND 3
26 SCL
AD0 4
25 SDA
P12 5
24 P31
P13 6
MAX7300
23 P30
P14 7
22 P29
P15 8
21 P28
P16 9
20 P27
P17 10
19 P26
P18 11
18 P25
P19 12
17 P24
P20 13
16 P23
P21 14
15 P22
39kΩ
3 GND
2 GND
1
ISET
35
DATA
CLOCK
AD1
4 AD0
33 SDA
34 SCL
MAX7300AAX
P4 32
P5 30
P6 28
P7 26
I/O 4
I/O 5
P8 5
P9 7
P10 9
P11 11
I/O 8
I/O 9
I/O 10
P12 6
P13 8
P14 10
P15 12
31 P31
29 P30
27 P29
25 P28
24 P27
P16 13
P17 14
P18 15
P19 16
P20 17
23 P26
22 P25
21 P24
P21 18
P22 19
P23 20
SSOP/DIP
Pin Configurations continued at end of data sheet.
I/O 6
I/O 7
I/O 11
I/O 12
I/O 13
I/O 14
I/O 15
I/O 16
I/O 17
I/O 18
I/O 19
I/O 20
I/O 21
I/O 22
I/O 23
I/O 24
I/O 25
I/O 26
I/O 27
I/O 28
I/O 29
I/O 30
I 2C is a trademark of Philips Corp.
I/O 31
________________________________________________________________ Maxim Integrated Products
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
1
MAX7300
General Description
The MAX7300 compact, serial-interfaced, I/O expansion peripheral provides microprocessors with up to 28
ports. Each port is individually user configurable to
either a logic input or logic output.
Each port can be configured as either a push-pull logic
output capable of sinking 10mA and sourcing 4.5mA, or a
Schmitt logic input with optional internal pullup. Seven
ports feature configurable transition detection logic, which
generates an interrupt upon change of port logic level.
The MAX7300 is controlled through an I2C™-compatible
2-wire serial interface, and uses four-level logic to allow
16 I2C addresses from only two select pins.
The MAX7300AAX and MAX7300AGL have 28 ports
and are available in 36-pin SSOP and 40-pin QFN packages, respectively. The MAX7300AAI and MAX7300ANI
have 20 ports and are available in 28-pin SSOP and 28pin DIP packages, respectively.
MAX7300
2-Wire-Interfaced, 2.5V to 5.5V, 20-Port or
28-Port I/O Expander
ABSOLUTE MAXIMUM RATINGS
Operating Temperature Range
(TMIN to TMAX) ...............................................-40°C to +125°C
Junction Temperature ......................................................+150°C
Storage Temperature Range .............................-65°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
Voltage (with respect to GND)
V+ .............................................................................-0.3V to +6V
SCL, SDA, AD0, AD1................................................-0.3V to +6V
All Other Pins................................................-0.3V to (V+ + 0.3V)
P4–P31 Current ................................................................±30mA
GND Current .....................................................................800mA
Continuous Power Dissipation (TA = +70°C)
28-Pin PDIP (derate 20.8mW/°C above +70°C).........1667mW
28-Pin SSOP (derate 9.5mW/°C above +70°C) ...........762mW
36-Pin SSOP (derate 11.8mW/°C above +70°C) .........941mW
40-Pin QFN (derate 23.25mW/°C aboveTA = +70°C)..1860mW
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(Typical Operating Circuit, V+ = 2.5V to 5.5V, TA = TMIN to TMAX, unless otherwise noted.) (Note 1)
PARAMETER
Operating Supply Voltage
Shutdown Supply Current
Operating Supply Current
Operating Supply Current
Operating Supply Current
SYMBOL
CONDITIONS
V+
ISHDN
IGPOH
IGPOL
IGPI
MIN
TYP
2.5
All digital inputs at
V+ or GND
TA = +25°C
5.5
MAX
UNITS
5.5
V
8
TA = -40°C to +85°C
10
TMIN to TMAX
11
All ports programmed TA = +25°C
as outputs high, no
TA = -40°C to +85°C
load, all other inputs
at V+ or GND
TMIN to TMAX
180
All ports programmed TA = +25°C
as outputs low, no
TA = -40°C to +85°C
load, all other inputs
at V+ or GND
TMIN to TMAX
170
All ports programmed TA = +25°C
as inputs without
pullup, ports, and all TA = -40°C to +85°C
other inputs at V+ or
TMIN to TMAX
GND
110
µA
240
260
µA
280
210
230
µA
240
135
140
µA
145
INPUTS AND OUTPUTS
Logic High Input Voltage
Port Inputs
VIH
Logic Low Input Voltage
Port Inputs
VIL
Input Leakage Current
IIH, IIL
GPIO Input Internal Pullup to V+
IPU
Hysteresis Voltage GPIO Inputs
∆VI
2
0.7 x
V+
GPIO inputs without pullup,
VPORT = V+ to GND
-100
V
±1
0.3 x
V+
V
+100
nA
V+ = 2.5V
12
19
30
V+ = 5.5V
80
120
180
0.3
_______________________________________________________________________________________
µA
V
2-Wire-Interfaced, 2.5V to 5.5V, 20-Port or
28-Port I/O Expander
(Typical Operating Circuit, V+ = 2.5V to 5.5V, TA = TMIN to TMAX, unless otherwise noted.) (Note 1)
PARAMETER
Output High Voltage
Port Sink Current
SYMBOL
VOH
IOL
Output Short-Circuit Current
IOLSC
Input High-Voltage SDA, SCL,
AD0, AD1
VIH
Input Low-Voltage SDA, SCL,
AD0, AD1
VIL
Input Leakage Current SDA, SCL
VOL
MIN
V+ 0.7
GPIO outputs, ISOURCE = 1mA,
TA = TMIN to TMAX (Note 2)
V+ 0.7
VPORT = 0.6V
Port configured output low, shorted to V+
TYP
MAX
UNITS
V
2
10
18
mA
2.75
11
20
mA
0.7 x
V+
IIH, IIL
Input Capacitance
Output Low-Voltage SDA
CONDITIONS
GPIO outputs, ISOURCE = 2mA,
TA = -40°C to +85°C
V
-50
0.3 x
V+
V
+50
nA
(Note 2)
10
pF
ISINK = 6mA
0.4
V
MAX
UNITS
400
kHz
TIMING CHARACTERISTICS (Figure 2)
(V+ = 2.5V to 5.5V, TA = TMIN to TMAX, unless otherwise noted.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
Serial Clock Frequency
fSCL
Bus Free Time Between a STOP
and a START Condition
tBUF
1.3
µs
Hold Time (Repeated) START
Condition
tHD, STA
0.6
µs
Repeated START Condition
Setup Time
tSU, STA
0.6
µs
STOP Condition Setup Time
tSU, STO
Data Hold Time
tHD, DAT
Data Setup Time
0.6
(Note 3)
µs
15
900
ns
tSU, DAT
100
ns
SCL Clock Low Period
tLOW
1.3
µs
SCL Clock High Period
tHIGH
0.7
µs
Rise Time of Both SDA and SCL
Signals, Receiving
tR
(Notes 2, 4)
20 +
0.1Cb
300
ns
Fall Time of Both SDA and SCL
Signals, Receiving
tF
(Notes 2, 4)
20 +
0.1Cb
300
ns
tF,TX
(Notes 2, 5)
20 +
0.1Cb
250
ns
Pulse Width of Spike Suppressed
tSP
(Notes 2, 6)
50
ns
Capacitive Load for Each Bus
Line
Cb
(Note 2)
400
pF
Fall Time of SDA Transmitting
0
_______________________________________________________________________________________
3
MAX7300
ELECTRICAL CHARACTERISTICS (continued)
TIMING CHARACTERISTICS (Figure 2) (continued)
(V+ = 2.5V to 5.5V, TA = TMIN to TMAX, unless otherwise noted.) (Note 1)
Note 1: All parameters tested at TA = +25°C. Specifications over temperature are guaranteed by design.
Note 2: Guaranteed by design.
Note 3: A master device must provide a hold time of at least 300ns for the SDA signal (referred to VIL of the SCL signal) in order to
bridge the undefined region of SCL’s falling edge.
Note 4: Cb = total capacitance of one bus line in pF. tR and tF measured between 0.3V+ and 0.7V+.
Note 5: ISINK ≤ 6mA. Cb = total capacitance of one bus line in pF. tR and tF measured between 0.3V+ and 0.7V+.
Note 6: Input filters on the SDA and SCL inputs suppress noise spikes less than 50ns.
__________________________________________Typical Operating Characteristics
(RISET = 39kΩ, TA = +25°C, unless otherwise noted.)
ALL PORTS
OUTPUT (0)
ALL PORTS
OUTPUT (1)
0.24
0.20
0.16
0.12
0.08
V+ = 3.3V
6
5
1
V+ = 2.5V
ALL PORTS OUTPUT (1)
ALL PORTS OUTPUT (0)
4
ALL PORTS INPUT
(PULLUPS DISABLED)
ALL PORTS INPUT HIGH
0.04
0
0.1
3
-40.0
-12.5
15.0
42.5
70.0
TEMPERATURE (°C)
4
V+ = 5.5V
7
SUPPLY CURRENT (µA)
0.32
0.28
8
SUPPLY CURRENT ( mA)
V+ = 2.5V TO 5.5V
NO LOAD
OPERATING SUPPLY CURRENT vs. V+
(OUTPUTS UNLOADED)
MAX7300 toc02
0.36
MAX7300 toc01
0.40
SHUTDOWN SUPPLY CURRENT
vs. TEMPERATURE
MAX7300 toc03
OPERATING SUPPLY CURRENT
vs. TEMPERATURE
SUPPLY CURRENT (mA)
MAX7300
2-Wire-Interfaced, 2.5V to 5.5V, 20-Port or
28-Port I/O Expander
97.5
125.0
-40.0
-12.5
15.0
42.5
70.0
97.5
125.0
2.0
2.5
3.0
3.5
TEMPERATURE (°C)
_______________________________________________________________________________________
4.0
V+ (V)
4.5
5.0
5.5
2-Wire-Interfaced, 2.5V to 5.5V, 20-Port or
28-Port I/O Expander
GPO SOURCE CURRENT vs. TEMPERATURE
(OUTPUT = 1)
GPO SINK CURRENT vs. TEMPERATURE
(OUTPUT = 0)
14
12
10
8
6
VPORT = 1.4V
8
V+ = 5.5V
7
V+ = 3.3V
6
5
V+ = 2.5V
4
3
4
2
2
-12.5
15.0
42.5
70.0
97.5
-40.0
125.0
-12.5
15.0
42.5
70.0
97.5
TEMPERATURE (°C)
TEMPERATURE (°C)
GPI PULLUP CURRENT
vs. TEMPERATURE
GPO SHORT-CIRCUIT CURRENT
vs. TEMPERATURE
100
PORT CURRENT (mA)
MAX7300 toc06
1000
V+ = 5.5V
100
V+ = 3.3V
125.0
MAX7300 toc07
-40.0
PULLUP CURRENT (µA)
MAX7300 toc05
9
PORT SOURCE CURRENT (mA)
V+ = 2.5V TO 5.5V, VPORT = 0.6V
16
PORT SINK CURRENT (mA)
MAX7300 toc04
18
GPO = 0, PORT
SHORTED TO V+
10
V+ = 2.5V
GPO = 1, PORT
SHORTED TO GND
1
10
-40.0
-12.5
15.0
42.5
70.0
TEMPERATURE (°C)
97.5
125.0
-40.0
-12.5
15.0
42.5
70.0
97.5
125.0
TEMPERATURE (°C)
_______________________________________________________________________________________
5
MAX7300
Typical Operating Characteristics (continued)
(RISET = 39kΩ, TA = +25°C, unless otherwise noted.)
2-Wire-Interfaced, 2.5V to 5.5V, 20-Port or
28-Port I/O Expander
MAX7300
Pin Description
PIN
NAME
FUNCTION
SSOP/DIP
SSOP
QFN
1
1
36
ISET
Bias Current Setting. Connect ISET to GND through a resistor (RISET)
value of 39kΩ to 120kΩ.
2, 3
2, 3
37, 38, 39
GND
Ground
4
4
40
AD0
Address Input 0. Sets device slave address. Connect to either GND,
V+, SCL, SDA to give four logic combinations. See Table 3.
5–24
—
—
P12–P31
I/O Ports. P12 to P31 can be configured as push-pull outputs, CMOSlogic inputs, or CMOS-logic inputs with weak pullup resistor.
—
5–32
1–10, 12–19,
21–30
P4–P31
I/O Ports. P4 to P31 can be configured as push-pull outputs, CMOSlogic inputs, or CMOS-logic inputs with weak pullup resistor.
25
33
32
SDA
I2C-Compatible Serial Data I/O
26
34
33
SCL
I2C-Compatible Serial Clock Input
27
35
34
AD1
Address Input 1. Sets device slave address. Connect to either GND,
V+, SCL, SDA to give four logic combinations. See Table 3.
28
36
35
V+
Positive Supply Voltage. Bypass V+ to GND with minimum 0.047µF
capacitor.
Detailed Description
The MAX7300 general-purpose input/output (GPIO)
peripheral provides up to 28 I/O ports, P4 to P31, controlled through an I2C-compatible serial interface. The
ports can be configured to any combination of logic
inputs and logic outputs, and default to logic inputs on
power-up.
Figure 1 is the MAX7300 functional diagram. Any I/O port
can be configured as a push-pull output (sinking 10mA,
sourcing 4.5mA), or a Schmitt-trigger logic input. Each
input has an individually selectable internal pullup resistor. Additionally, transition detection allows seven ports
(P24 to P30) to be monitored in any maskable combination for changes in their logic status. A detected transition is flagged through a status register bit, as well as an
interrupt pin (port P31), if desired.
The port configuration registers individually set the 28
ports, P4 to P31, as GPIO. A pair of bits in registers
0x09 through 0x0F sets each port’s configuration
(Tables 1 and 2).
The 36-pin MAX7300AAX and 40-pin MAX7300AGL
have 28 ports, P4 to P31. The 28-pin MAX7300ANI and
MAX7300AAI have only 20 ports available, P12 to P31.
The eight unused ports should be configured as outputs on power-up by writing 0x55 to registers 0x09 and
6
0x0A. If this is not done, the eight unused ports remain
as floating inputs and quiescent supply current rises,
although there is no damage to the part.
Register Control of I/O Ports
Across Multiple Drivers
The MAX7300 offers 20 or 28 I/O ports, depending on
package choice. Two addressing methods are available. Any single port (bit) can be written (set/cleared)
at once; or, any sequence of eight ports can be written
(set/cleared) in any combination at once. There are no
boundaries; it is equally acceptable to write P0 to P7,
P1 to P8, or P31 to P38 (P32 to P38 are nonexistent, so
the instructions to these bits are ignored).
Shutdown
When the MAX7300 is in shutdown mode, all ports are
forced to inputs, and the pullup current sources are
turned off. Data in the port and control registers remain
unaltered, so port configuration and output levels are
restored when the MAX7300 is taken out of shutdown.
The MAX7300 can still be programmed while in shutdown mode. For minimum supply current in shutdown
mode, logic inputs should be at GND or V+ potential.
Shutdown mode is exited by setting the S bit in the configuration register (Table 8).
_______________________________________________________________________________________
2-Wire-Interfaced, 2.5V to 5.5V, 20-Port or
28-Port I/O Expander
MAX7300
Table 1. Port Configuration Map
ADDRESS
CODE (HEX)
REGISTER
REGISTER DATA
D7
D6
D5
D4
D3
D2
D1
D0
Port Configuration for P7, P6, P5, P4
0x09
P7
P6
P5
P4
Port Configuration for P11, P10, P9, P8
0x0A
P11
P10
P9
P8
Port Configuration for P15, P14, P13, P12
0x0B
P15
P14
P13
P12
Port Configuration for P19, P18, P17, P16
0x0C
P19
P18
P17
P16
Port Configuration for P23, P22, P21, P20
0x0D
P23
P22
P21
P20
Port Configuration for P27, P26, P25, P24
0x0E
P27
P26
P25
P24
Port Configuration for P31, P30, P29, P28
0x0F
P31
P30
P29
P28
Table 2. Port Configuration Matrix
MODE
PORT
REGISTER
FUNCTION
PIN BEHAVIOR
DO NOT USE THIS SETTING
ADDRESS
CODE (HEX)
PORT
CONFIGURATION
BIT PAIR
UPPER
LOWER
0x09 to 0x0F
0
0
0x09 to 0x0F
0
1
Written Low
Active-low logic output
Written High
Active-high logic output
GPIO Input
without Pullup
Reading Port
Schmitt logic output
0x09 to 0x0F
1
0
GPIO Input with Pullup
Reading Port
Schmitt logic input with pullup
0x09 to 0x0F
1
1
Output
GPIO Output
Input
Input
Serial Interface
Serial Addressing
The MAX7300 operates as a slave that sends and
receives data through an I2C-compatible 2-wire interface. The interface uses a serial data line (SDA) and a
serial clock line (SCL) to achieve bidirectional communication between master(s) and slave(s). A master (typically a microcontroller) initiates all data transfers to and
from the MAX7300, and generates the SCL clock that
synchronizes the data transfer (Figure 2).
The MAX7300 SDA line operates as both an input and
an open-drain output. A pullup resistor, typically 4.7kΩ,
is required on SDA. The MAX7300 SCL line operates
only as an input. A pullup resistor, typically 4.7kΩ, is
required on SCL if there are multiple masters on the 2wire interface, or if the master in a single-master system
has an open-drain SCL output.
Each transmission consists of a START condition
(Figure 3) sent by a master, followed by the MAX7300
7-bit slave address plus R/ W bit (Figure 6), a register
address byte, one or more data bytes, and finally a
STOP condition (Figure 3).
Start and Stop Conditions
Both SCL and SDA remain high when the interface is
not busy. A master signals the beginning of a transmission with a START (S) condition by transitioning SDA
from high to low while SCL is high. When the master
has finished communicating with the slave, it issues a
STOP (P) condition by transitioning SDA from low to
high while SCL is high. The bus is then free for another
transmission (Figure 3).
Bit Transfer
One data bit is transferred during each clock pulse.
The data on SDA must remain stable while SCL is high
(Figure 4).
Acknowledge
The acknowledge bit is a clocked 9th bit, which the
recipient uses to handshake receipt of each byte of
data (Figure 5). Thus, each byte transferred effectively
requires 9 bits. The master generates the 9th clock
pulse, and the recipient pulls down SDA during the
acknowledge clock pulse, such that the SDA line is stable low during the high period of the clock pulse. When
the master is transmitting to the MAX7300, the
MAX7300 generates the acknowledge bit since the
_______________________________________________________________________________________
7
MAX7300
2-Wire-Interfaced, 2.5V to 5.5V, 20-Port or
28-Port I/O Expander
CONFIGURATION
PORT REGISTERS
MASK REGISTER
GPIO
P4 TO P31
CONFIGURATION
REGISTERS
PORT CHANGE
DETECTOR
DATA
CE
R/W
8
GPIO DATA
R/W
8
AD0
COMMAND
REGISTER DECODE
ADDRESS
MATCHER
AD1
7
8
8
DATA BYTE
D0
D1
D2
D3
D4
COMMAND BYTE
D5
D6
7
D7
D8
D9
D10
TO/FROM DATA REGISTERS
7-BIT DEVICE ADDRESS
D11
D12
D13
D14
D15
TO COMMAND REGISTERS
R/W
SDA
SCL
SLAVE ADDRESS BYTE
DATA BYTE
COMMAND BYTE
Figure 1. MAX7300 Functional Diagram
MAX7300 is the recipient. When the MAX7300 is transmitting to the master, the master generates the
acknowledge bit since the master is the recipient.
addresses (Table 3), and therefore a maximum of 16
MAX7300 devices can share the same interface.
Slave Address
Message Format for Writing
the MAX7300
The MAX7300 has a 7-bit-long slave address (Figure 6).
The eighth bit following the 7-bit slave address is the
R/ W bit. It is low for a write command and high for a
read command.
The first 3 bits (MSBs) of the MAX7300 slave address
are always 100. Slave address bits A3, A2, A1, and A0
are selected by the address inputs, AD1 and AD0.
These two input pins can be connected to GND, V+,
SDA, or SCL. The MAX7300 has 16 possible slave
A write to the MAX7300 comprises the transmission of
the MAX7300’s slave address with the R/ W bit set to
zero, followed by at least 1 byte of information. The first
byte of information is the command byte. The command byte determines which register of the MAX7300
is to be written by the next byte, if received. If a STOP
condition is detected after the command byte is
received, then the MAX7300 takes no further action
(Figure 7) beyond storing the command byte.
8
_______________________________________________________________________________________
2-Wire-Interfaced, 2.5V to 5.5V, 20-Port or
28-Port I/O Expander
tBUF
tSU, STA
tSU, DAT
tHD, STA
tLOW
tSU, STO
tHD, DAT
SCL
tHIGH
tHD, STA
tR
tF
REPEATED START CONDITION
START CONDITION
STOP CONDITION
START CONDITION
Figure 2. 2-Wire Serial Interface Timing Details
SDA
SCL
S
P
START
CONDITION
STOP
CONDITION
Figure 3. Start and Stop Conditions
SDA
SCL
DATA LINE STABLE; DATA VALID CHANGE OF DATA ALLOWED
Figure 4. Bit Transfer
Any bytes received after the command byte are considered data bytes. The first data byte goes into the internal register of the MAX7300 selected by the command
byte (Figure 8). If multiple data bytes are transmitted
before a STOP condition is detected, these bytes are
generally stored in subsequent MAX7300 internal registers because the command byte address generally
autoincrements (Table 4).
Message Format for Reading
The MAX7300 is read using the MAX7300’s internally
stored command byte as address pointer, the same way
the stored command byte is used as address pointer for
a write. The pointer generally autoincrements after each
data byte is read using the same rules as for a write
(Table 4). Thus, a read is initiated by first configuring the
MAX7300’s command byte by performing a write (Figure
7). The master can now read ‘n’ consecutive bytes from
the MAX7300, with the first data byte being read from the
register addressed by the initialized command byte
(Figure 9). When performing read-after-write verification,
remember to reset the command byte’s address
because the stored control byte address generally has
been autoincremented after the write (Table 4). Table 5
is the register address map.
__________________________________________________________________________
MAX7300
SDA
MAX7300
2-Wire-Interfaced, 2.5V to 5.5V, 20-Port or
28-Port I/O Expander
START CONDITION
CLOCK PULSE FOR ACKNOWLEDGMENT
SCL
1
2
8
9
SDA
BY TRANSMITTER
S
SDA
BY RECEIVER
Figure 5. Acknowledge
SDA
1
0
0
A3
A2
A1
A0
R/W
ACK
LSB
MSB
SCL
Figure 6. Slave Address
Operation with Multiple Masters
If the MAX7300 is operated on a 2-wire interface with
multiple masters, a master reading the MAX7300 should
use a repeated start between the write, which sets the
MAX7300’s address pointer, and the read(s) that takes
the data from the location(s). This is because it is possible for master 2 to take over the bus after master 1 has
set up the MAX7300’s address pointer, but before
master 1 has read the data. If master 2 subsequently
changes, the MAX7300’s address pointer, then master
1’s delayed read can be from an unexpected location.
Command Address Autoincrementing
Address autoincrementing allows the MAX7300 to be
configured with the shortest number of transmissions
by minimizing the number of times the command
address needs to be sent. The command address
stored in the MAX7300 generally increments after each
data byte is written or read (Table 4).
10
Initial Power-Up
On initial power-up, all control registers are reset and
the MAX7300 enters shutdown mode (Table 6).
Transition (Port Data Change) Detection
Port transition detection allows seven maskable ports
P24 to P30 to be continuously monitored for changes in
their logic status (Figure 10). Enable transition detection by setting the M bit in the configuration register
(Table 9) after setting the mask register. If port 31 is
configured as an output (Tables 1 and 2), then P31
automatically becomes an interrupt request (IRQ) output to flag detected transitions. Port 31 can be configured and used as a general-purpose input port instead,
if not required for use as the IRQ output.
The mask register determines which of the seven ports
P24 to P30 are monitored (Table 10). Set the appropriate mask bit to enable that port for transition detect.
Clear the mask bit if transitions on that port are to be
ignored by the transition detection logic. Ports are monitored regardless of their I/O configuration, both input
and output.
______________________________________________________________________________________
2-Wire-Interfaced, 2.5V to 5.5V, 20-Port or
28-Port I/O Expander
SLAVE ADDRESS
S
0
A
MAX7300
D15 D14 D13 D12 D11 D10 D9
COMMAND BYTE IS STORED ON RECEIPT OF STOP CONDITION
ACKNOWLEDGE FROM MAX7300
D8
A
COMMAND BYTE
P
ACKNOWLEDGE FROM MAX7300
R/W
Figure 7. Command Byte Received
ACKNOWLEDGE FROM MAX7300
D15 D14 D13 D12 D11 D10
HOW COMMAND BYTE AND DATA BYTE MAP INTO MAX7300’s REGISTER
ACKNOWLEDGE FROM MAX7300
S
SLAVE ADDRESS
0
A
COMMAND BYTE
D9
ACKNOWLEDGE FROM MAX7300
D8
D7
A
D6
D5
D4
D3
D2
D1
D0
DATA BYTE
A
P
1 BYTE
R/W
AUTOINCREMENT MEMORY WORD ADDRESS
Figure 8. Command and Single Data Byte Received
The MAX7300 maintains an internal 7-bit snapshot register to hold the comparison copy of the logic states of
ports P24 to P30. The snapshot register is updated with
the condition of P24 to P31 whenever the configuration
register is written with the M bit set. The update action
occurs regardless of the previous state of the M bit so
that it is not necessary to clear the M bit and then reset
it in order to update the snapshot register.
When the data change detection bit is set, the MAX7300
continuously compares the snapshot register against
the changing states of P24 to P31. When a difference
occurs, the IRQ bit (mask register bit D7) is set and IRQ
port P31 goes high if it is configured as an output.
The IRQ bit and IRQ output remain set until the mask
register is next read or written, so if the IRQ is set, then
the mask register reads with bit D7 set. Writing the
mask register clears the IRQ bit and resets the IRQ output, regardless of the value of bit D7 written.
Applications Information
Low-Voltage Operation
The MAX7300 operates down to 2V supply voltage
(although the sourcing and sinking currents are not
guaranteed), providing that the MAX7300 is powered up
initially to at least 2.5V to trigger the device’s internal
reset.
Power-Supply Considerations
The MAX7300 operates with power-supply voltages of
2.5V to 5.5V. Bypass the power supply to GND with a
0.047µF capacitor as close to the device as possible.
Add a 1µF capacitor if the MAX7300 is far away from
the board’s input bulk decoupling capacitor.
Chip Information
TRANSISTOR COUNT: 33,559
PROCESS: CMOS
External Component RISET
The MAX7300 uses an external resistor, RISET, to set
internal biasing. Use a resistor value of 39kΩ.
______________________________________________________________________________________
11
MAX7300
2-Wire-Interfaced, 2.5V to 5.5V, 20-Port or
28-Port I/O Expander
ACKNOWLEDGE FROM MAX7300
ACKNOWLEDGE FROM MAX7300
HOW COMMAND BYTE AND DATA BYTE MAP INTO MAX7300’s REGISTER
D15 D14 D13 D12 D11 D10 D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
ACKNOWLEDGE FROM MAX7300
S
SLAVE ADDRESS
0
COMMAND BYTE
A
DATA BYTE
A
A
P
‘n’ BYTES
R/W
AUTOINCREMENT MEMORY WORD ADDRESS
Figure 9. ‘n’ Data Bytes Received
Table 3. MAX7300 Address Map
PIN
CONNECTION
DEVICE ADDRESS
AD1
AD0
A6
A5
A4
A3
A2
A1
A0
GND
GND
1
0
0
0
0
0
0
GND
V+
1
0
0
0
0
0
1
GND
SDA
1
0
0
0
0
1
0
GND
SCL
1
0
0
0
0
1
1
V+
GND
1
0
0
0
1
0
0
V+
V+
1
0
0
0
1
0
1
V+
SDA
1
0
0
0
1
1
0
V+
SCL
1
0
0
0
1
1
1
SDA
GND
1
0
0
1
0
0
0
SDA
V+
1
0
0
1
0
0
1
SDA
SDA
1
0
0
1
0
1
0
SDA
SCL
1
0
0
1
0
1
1
SCL
GND
1
0
0
1
1
0
0
SCL
V+
1
0
0
1
1
0
1
SCL
SDA
1
0
0
1
1
1
0
SCL
SCL
1
0
0
1
1
1
1
Table 4. Autoincrement Rules
COMMAND BYTE ADDRESS RANGE
x0000000 to x1111110
x1111111
12
AUTOINCREMENT BEHAVIOR
Command address autoincrements after byte read or written
Command address remains at x1111111 after byte written or read
______________________________________________________________________________________
2-Wire-Interfaced, 2.5V to 5.5V, 20-Port or
28-Port I/O Expander
REGISTER
COMMAND ADDRESS
D15
D14
D13
D12
D11
D10
D9
D8
HEX
CODE
No-Op
X
0
0
0
0
0
0
0
0x00
Configuration
X
0
0
0
0
1
0
0
0x04
Transition Detect Mask
X
0
0
0
0
1
1
0
0x06
Factory Reserved; do not write to this port
X
0
0
0
0
1
1
1
0x07
Port Configuration P7, P6, P5, P4
X
0
0
0
1
0
0
1
0x09
Port Configuration P11, P10, P9, P8
X
0
0
0
1
0
1
0
0x0A
Port Configuration P15, P14, P13, P12
X
0
0
0
1
0
1
1
0x0B
Port Configuration P19, P18, P17, P16
X
0
0
0
1
1
0
0
0x0C
Port Configuration P23, P22, P21, P20
X
0
0
0
1
1
0
1
0x0D
Port Configuration P27, P26, P25, P24
X
0
0
0
1
1
1
0
0x0E
Port Configuration P31, P30, P29, P28
X
0
0
0
1
1
1
1
0x0F
Port 0 only (virtual port, no action)
X
0
1
0
0
0
0
0
0x20
Port 1 only (virtual port, no action)
X
0
1
0
0
0
0
1
0x21
Port 2 only (virtual port, no action)
X
0
1
0
0
0
1
0
0x22
Port 3 only (virtual port, no action)
X
0
1
0
0
0
1
1
0x23
Port 4 only
X
0
1
0
0
1
0
0
0x24
Port 5 only
X
0
1
0
0
1
0
1
0x25
Port 6 only
X
0
1
0
0
1
1
0
0x26
Port 7 only
X
0
1
0
0
1
1
1
0x27
Port 8 only
X
0
1
0
1
0
0
0
0x28
Port 9 only
X
0
1
0
1
0
0
1
0x29
Port 10 only
X
0
1
0
1
0
1
0
0x2A
Port 11 only
X
0
1
0
1
0
1
1
0x2B
Port 12 only
X
0
1
0
1
1
0
0
0x2C
Port 13 only
X
0
1
0
1
1
0
1
0x2D
Port 14 only
X
0
1
0
1
1
1
0
0x2E
Port 15 only
X
0
1
0
1
1
1
1
0x2F
Port 16 only
X
0
1
1
0
0
0
0
0x30
Port 17 only
X
0
1
1
0
0
0
1
0x31
Port 18 only
X
0
1
1
0
0
1
0
0x32
Port 19 only
X
0
1
1
0
0
1
1
0x33
Port 20 only
X
0
1
1
0
1
0
0
0x34
Port 21 only
X
0
1
1
0
1
0
1
0x35
Port 22 only
X
0
1
1
0
1
1
0
0x36
Port 23 only
X
0
1
1
0
1
1
1
0x37
Port 24 only
X
0
1
1
1
0
0
0
0x38
Port 25 only
X
0
1
1
1
0
0
1
0x39
______________________________________________________________________________________
13
MAX7300
Table 5. Register Address Map
MAX7300
2-Wire-Interfaced, 2.5V to 5.5V, 20-Port or
28-Port I/O Expander
Table 5. Register Address Map (continued)
COMMAND ADDRESS
D15
D14
D13
D12
D11
D10
D9
D8
HEX
CODE
Port 26 only
X
0
1
1
1
0
1
0
0x3A
Port 27 only
X
0
1
1
1
0
1
1
0x3B
Port 28 only
X
0
1
1
1
1
0
0
0x3C
Port 29 only
X
0
1
1
1
1
0
1
0x3D
Port 30 only
X
0
1
1
1
1
1
0
0x3E
Port 31 only
X
0
1
1
1
1
1
1
0x3F
4 ports 4–7 (data bits D0–D3)
X
1
0
0
0
0
0
0
0x40
5 ports 4–8 (data bits D0–D4)
X
1
0
0
0
0
0
1
0x41
6 ports 4–9 (data bits D0–D5)
X
1
0
0
0
0
1
0
0x42
7 ports 4–10 (data bits D0–D6)
X
1
0
0
0
0
1
1
0x43
8 ports 4–11
X
1
0
0
0
1
0
0
0x44
8 ports 5–12
X
1
0
0
0
1
0
1
0x45
8 ports 6–13
X
1
0
0
0
1
1
0
0x46
8 ports 7–14
X
1
0
0
0
1
1
1
0x47
8 ports 8–15
X
1
0
0
1
0
0
0
0x48
8 ports 9–16
X
1
0
0
1
0
0
1
0x49
8 ports 10–17
X
1
0
0
1
0
1
0
0x4A
8 ports 11–18
X
1
0
0
1
0
1
1
0x4B
8 ports 12–19
X
1
0
0
1
1
0
0
0x4C
8 ports 13–20
X
1
0
0
1
1
0
1
0x4D
8 ports 14–21
X
1
0
0
1
1
1
0
0x4E
8 ports 15–22
X
1
0
0
1
1
1
1
0x4F
8 ports 16–23
X
1
0
1
0
0
0
0
0x50
8 ports 17–24
X
1
0
1
0
0
0
1
0x51
8 ports 18–25
X
1
0
1
0
0
1
0
0x52
8 ports 19–26
X
1
0
1
0
0
1
1
0x53
8 ports 20–27
X
1
0
1
0
1
0
0
0x54
8 ports 21–28
X
1
0
1
0
1
0
1
0x55
8 ports 22–29
X
1
0
1
0
1
1
0
0x56
8 ports 23–30
X
1
0
1
0
1
1
1
0x57
8 ports 24–31
X
1
0
1
1
0
0
0
0x58
7 ports 25–31
X
1
0
1
1
0
0
1
0x59
6 ports 26–31
X
1
0
1
1
0
1
0
0x5A
5 ports 27–31
X
1
0
1
1
0
1
1
0x5B
4 ports 28–31
X
1
0
1
1
1
0
0
0x5C
3 ports 29–31
X
1
0
1
1
1
0
1
0x5D
2 ports 30–31
X
1
0
1
1
1
1
0
0x5E
1 port 31 only
X
1
0
1
1
1
1
1
0x5F
REGISTER
Note: Unused bits read as zero.
14
______________________________________________________________________________________
2-Wire-Interfaced, 2.5V to 5.5V, 20-Port or
28-Port I/O Expander
REGISTER
FUNCTION
POWER-UP CONDITION
ADDRESS
CODE
(HEX)
REGISTER DATA
D7
D6
D5
D4
D3
D2
D1
D0
Port Register
Bits 4 to 31
GPIO Output Low
0x24 to
0x3F
X
X
X
X
X
X
X
0
Configuration
Register
Shutdown Enabled
Transition Detection Disabled
0x04
0
0
X
X
X
X
X
0
All Clear (Masked Off)
0x06
X
0
0
0
0
0
0
0
Port
Configuration
P7, P6, P5, P4: GPIO Inputs without Pullup
0x09
1
0
1
0
1
0
1
0
Port
Configuration
P11, P10, P9, P8: GPIO Inputs without Pullup
0x0A
1
0
1
0
1
0
1
0
Port
Configuration
P15, P14, P13, P12: GPIO Inputs without Pullup
0x0B
1
0
1
0
1
0
1
0
Port
Configuration
P19, P18, P17, P16: GPIO Inputs without Pullup
0x0C
1
0
1
0
1
0
1
0
Port
Configuration
P23, P22, P21, P20: GPIO Inputs without Pullup
0x0D
1
0
1
0
1
0
1
0
Port
Configuration
P27, P26, P25, P24: GPIO Inputs without Pullup
0x0E
1
0
1
0
1
0
1
0
Port
Configuration
P31, P30, P29, P28: GPIO Inputs without Pullup
0x0F
1
0
1
0
1
0
1
0
Input Mask
Register
X = unused bits; if read, zero results.
______________________________________________________________________________________
15
MAX7300
Table 6. Power-Up Configuration
MAX7300
2-Wire-Interfaced, 2.5V to 5.5V, 20-Port or
28-Port I/O Expander
Table 7. Configuration Register Format
REGISTER DATA
FUNCTION
ADDRESS CODE
(HEX)
D7
D6
D5
D4
D3
D2
D1
D0
Configuration Register
0x04
M
0
X
X
X
X
X
S
D2
D1
D0
Table 8. Shutdown Control (S Data Bit D0) Format
REGISTER DATA
ADDRESS CODE
(HEX)
FUNCTION
D7
D6
D5
D4
D3
Shutdown
0x04
M
0
X
X
X
X
X
0
Normal Operation
0x04
M
0
X
X
X
X
X
1
Table 9. Transition Detection Control (M Data Bit D7) Format
REGISTER DATA
FUNCTION
ADDRESS CODE
(HEX)
D7
D6
D5
D4
D3
D2
D1
D0
Disabled
0x04
0
0
X
X
X
X
X
S
Enabled
0x04
1
0
X
X
X
X
X
S
Table 10. Transition Detection Mask Register
FUNCTION
Mask
Register
REGISTER
ADDRESS
(HEX)
READ/
WRITE
REGISTER DATA
D7
D6
D5
D4
D3
D2
D1
D0
Read
IRQ Status*
Write
Unchanged
Port
30
mask
Port
29
mask
Port
28
mask
Port
27
mask
Port
26
mask
Port
25
mask
Port
24
mask
0x06
*IRQ is automatically cleared after it is read.
16
______________________________________________________________________________________
2-Wire-Interfaced, 2.5V to 5.5V, 20-Port or
28-Port I/O Expander
MAX7300
GPIO INPUT
CONDITIONING
GPIO IN
GPIO/PORT
OUTPUT LATCH
GPIO/PORT OUT
IRQ STATUS STORED AS MSB OF MASK REGISTER
P31
IRQ
OUTPUT LATCH
CLOCK PULSE AFTER EACH READ ACCESS TO MASK REGISTER
R
S
CONFIGURATION REGISTER M BIT = 1
GPIO INPUT
CONDITIONING
P30
GPIO IN
D
Q
GPIO/PORT OUT
MASK REGISTER BIT 6
GPIO/PORT OUTPUT LATCH
GPIO INPUT
CONDITIONING
P29
GPIO IN
D
Q
GPIO/PORT OUT
MASK REGISTER BIT 5
GPIO/PORT OUTPUT LATCH
GPIO INPUT
CONDITIONING
P28
GPIO IN
D
Q
GPIO/PORT OUT
MASK REGISTER BIT 4
GPIO/PORT OUTPUT LATCH
GPIO INPUT
CONDITIONING
P27
GPIO IN
D
Q
OR
MASK REGISTER BIT 3
GPIO/PORT OUT
GPIO/PORT OUTPUT LATCH
GPIO INPUT
CONDITIONING
P26
GPIO IN
D
Q
GPIO/PORT OUT
MASK REGISTER BIT 2
GPIO/PORT OUTPUT LATCH
GPIO INPUT
CONDITIONING
P25
GPIO IN
D
Q
GPIO/PORT OUT
MASK REGISTER BIT 1
GPIO/PORT OUTPUT LATCH
GPIO INPUT
CONDITIONING
P24
GPIO IN
D
GPIO/PORT OUT
GPIO/PORT OUTPUT LATCH
Q
MASK REGISTER LSB
CLOCK PULSE WHEN WRITING CONFIGURATION REGISTER WITH M BIT SET
Figure 10. Maskable GPIO Ports P24 to P31
______________________________________________________________________________________
17
MAX7300
2-Wire-Interfaced, 2.5V to 5.5V, 20-Port or
28-Port I/O Expander
Pin Configurations (continued)
N.C.
31
32
33
34
35
GND
ISET
V+
AD1
SCL
SDA
37
36
GND
GND
39
38
AD0
40
TOP VIEW
ISET 1
36 V+
GND
2
35 AD1
P8
1
30
GND
3
34 SCL
2
29
AD0
4
33 SDA
P12
P9
P13
3
28
4
27
P8
5
6
P10
P14
5
P12
7
24
8
23
P29
P7
P28
9
22
P27
10
21
P26
32 P4
MAX7300
31 P31
P9
7
30 P5
P13
8
29 P30
P11
P15
P16
28 P6
P17
18
19
P24
P25
N.C.
24 P27
P17 14
23 P26
P18 15
22 P25
P19 16
21 P24
P20 17
20 P23
P21 18
19 P22
P5
P30
P6
20
17
25 P28
P16 13
16
12
P15 12
15
11
26 P7
14
27 P29
13
P14 10
P11 11
P18
P19
P20
P21
P22
P23
9
25
N.C.
P10
26
MAX7300
6
P4
P31
QFN
SSOP
18
______________________________________________________________________________________
2-Wire-Interfaced, 2.5V to 5.5V, 20-Port or
28-Port I/O Expander
SSOP.EPS
2
1
INCHES
E
H
MILLIMETERS
DIM
MIN
MAX
MIN
MAX
A
0.068
0.078
1.73
1.99
A1
0.002
0.008
0.05
0.21
B
0.010
0.015
0.25
0.38
C
D
0.20
0.09
0.004 0.008
SEE VARIATIONS
E
0.205
e
0.212
0.0256 BSC
5.20
MILLIMETERS
INCHES
D
D
D
D
D
5.38
MIN
MAX
MIN
MAX
0.239
0.239
0.278
0.249
0.249
0.289
6.07
6.07
7.07
6.33
6.33
7.33
0.317
0.397
0.328
0.407
8.07
10.07
8.33
10.33
N
14L
16L
20L
24L
28L
0.65 BSC
H
0.301
0.311
7.65
7.90
L
0.025
0∞
0.037
8∞
0.63
0∞
0.95
8∞
N
A
C
B
e
A1
L
D
NOTES:
1. D&E DO NOT INCLUDE MOLD FLASH.
2. MOLD FLASH OR PROTRUSIONS NOT TO EXCEED .15 MM (.006").
3. CONTROLLING DIMENSION: MILLIMETERS.
4. MEETS JEDEC MO150.
5. LEADS TO BE COPLANAR WITHIN 0.10 MM.
PROPRIETARY INFORMATION
TITLE:
PACKAGE OUTLINE, SSOP, 5.3 MM
APPROVAL
DOCUMENT CONTROL NO.
21-0056
REV.
C
1
1
______________________________________________________________________________________
19
MAX7300
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)
36L,40L, QFN.EPS
MAX7300
2-Wire-Interfaced, 2.5V to 5.5V, 20-Port or
28-Port I/O Expander
20
______________________________________________________________________________________
2-Wire-Interfaced, 2.5V to 5.5V, 20-Port or
28-Port I/O Expander
U
______________________________________________________________________________________
21
MAX7300
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)
SSOP.EPS
MAX7300
2-Wire-Interfaced, 2.5V to 5.5V, 20-Port or
28-Port I/O Expander
36
E
DIM
A
A1
B
C
e
E
H
L
D
H
INCHES
MILLIMETERS
MAX
MIN
0.104
0.096
0.004
0.011
0.017
0.012
0.013
0.009
0.0315 BSC
0.299
0.291
0.398
0.414
0.040
0.020
0.598
0.612
MAX
MIN
2.65
2.44
0.29
0.10
0.44
0.30
0.23
0.32
0.80 BSC
7.40
7.60
10.11
10.51
0.51
15.20
1.02
15.55
1
TOP VIEW
D
A1
e
A
B
C
0∞-8∞
L
FRONT VIEW
SIDE VIEW
PROPRIETARY INFORMATION
TITLE:
PACKAGE OUTLINE, 36L SSOP, 0.80 MM PITCH
APPROVAL
DOCUMENT CONTROL NO.
21-0040
REV.
E
1
1
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
22 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2003 Maxim Integrated Products
Printed USA
is a registered trademark of Maxim Integrated Products.