HCF40174B HEX "D" TYPE FLIP-FLOP ■ ■ ■ ■ ■ ■ STANDARDIZED SYMMETRICAL OUTPUT CHARACTERISTICS QUIESCENT CURRENT SPECIFIED UP TO 20V 5V, 10V, AND 15V PARAMETRIC RATINGS INPUT LEAKAGE CURRENT II = 100nA (MAX) AT VDD = 18V TA = 25°C 100% TESTED FOR QUIESCENT CURRENT MEETS ALL REQUIREMENTS OF JEDEC JESD13B "STANDARD SPECIFICATIONS FOR DESCRIPTION OF B SERIES CMOS DEVICES" DESCRIPTION HCF40174B is a monolithic integrated circuit fabricated in Metal Oxide Semiconductor technology available in DIP and SOP packages. HCF40174B consists of six identical "D" Type flip-flops having independent DATA inputs. The DIP SOP ORDER CODES PACKAGE TUBE T&R DIP SOP HCF40174BEY HCF40174BM1 HCF40174M013TR CLOCK and CLEAR inputs are common in all six units. Data is transferred to the Q outputs on the positive-going transition of the clock pulse. All six flip-flops are simultaneously reset by a low level on the CLEAR input. PIN CONNECTION September 2002 1/9 HCF40174B IINPUT EQUIVALENT CIRCUIT PIN DESCRIPTION PIN No 3, 4, 6, 11, 13, 14 2, 5, 7, 10, 12, 15 9 1 SYMBOL NAME AND FUNCTION D1 to D6 Data Inputs Q1 to Q6 Data Outputs 8 CLOCK CLEAR VSS 16 VDD Common Clock Inputs Common Clear Inputs Negative Supply Voltage Positive Supply Voltage TRUTH TABLE INPUTS CLOCK X X : Don’t Care NC : NO CHANGE FUNCTIONAL DIAGRAM 2/9 OUTPUT DATA CLEAR Q L H L H H H X H NC X L L HCF40174B LOGIC DIAGRAM ABSOLUTE MAXIMUM RATINGS Symbol VDD Parameter Supply Voltage VI DC Input Voltage II DC Input Current Value Unit -0.5 to +22 V -0.5 to VDD + 0.5 ± 10 V mA 200 100 mW mW Top Power Dissipation per Package Power Dissipation per Output Transistor Operating Temperature -55 to +125 °C Tstg Storage Temperature -65 to +150 °C PD Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied. All voltage values are referred to VSS pin voltage. RECOMMENDED OPERATING CONDITIONS Symbol VDD Parameter Supply Voltage VI Input Voltage Top Operating Temperature Value Unit 3 to 20 V 0 to VDD V -55 to 125 °C 3/9 HCF40174B DC SPECIFICATIONS Test Condition Symbol IL VOH VOL VIH VIL IOH IOL II CI Parameter Quiescent Current High Level Output Voltage Low Level Output Voltage VI (V) 0/5 0/10 0/15 0/20 0/5 0/10 0/15 5/0 10/0 15/0 High Level Input Voltage Low Level Input Voltage Output Drive Current Output Sink Current Input Leakage Current Input Capacitance VO (V) 0/5 0/5 0/10 0/15 0/5 0/10 0/15 0/18 0.5/4.5 1/9 1.5/13.5 4.5/0.5 9/1 13.5/1.5 2.5 4.6 9.5 13.5 0.4 0.5 1.5 Value |IO| VDD (µA) (V) <1 <1 <1 <1 <1 <1 <1 <1 <1 <1 <1 <1 <1 <1 <1 <1 <1 <1 <1 Any Input Any Input 5 10 15 20 5 10 15 5 10 15 5 10 15 5 10 15 5 5 10 15 5 10 15 18 TA = 25°C Min. Typ. Max. 0.02 0.02 0.02 0.02 1 2 4 20 4.95 9.95 14.95 -40 to 85°C -55 to 125°C Min. Min. Max. 30 60 120 600 4.95 9.95 14.95 0.05 0.05 0.05 3.5 7 11 4.95 9.95 14.95 3.5 7 11 1.5 3 4 -1.1 -2.6 -0.31 -0.75 -0.68 -1.6 -2.3 -5.4 0.44 1 1.1 2.6 3.0 6.8 ±0.1 5 7.5 0.05 0.05 0.05 1.5 3 4 -0.9 -0.25 -0.54 -1.84 0.36 0.9 2.4 The Noise Margin for both "1" and "0" level is: 1V min. with VDD =5V, 2V min. with VDD=10V, 2.5V min. with VDD=15V 4/9 V V 1.5 3 4 ±1 µA V 3.5 7 11 -0.9 -0.25 -0.54 -1.84 0.36 0.9 2.4 ±10-5 Max. 30 60 120 600 0.05 0.05 0.05 Unit V mA mA ±1 µA pF HCF40174B DYNAMIC ELECTRICAL CHARACTERISTICS (Tamb = 25°C, CL = 50pF, RL = 200KΩ, tr = tf = 20 ns) Test Condition Symbol Parameter tPLH tPHL Propagation Delay Time : Clock to Output tPHL Propagation Delay Time : Clear to Output tTHL, tTLH Transition Time tsetup thold tW tW tr, tf trem fCL Data Setup Time Data Hold Time Clock Input Pulse Widht Low Level Clear Input Pulse Widht HIGH and LOW Clock Input Rise or Fall Time Clear Removal Time Maximum Clock Input Frequency VDD (V) 5 10 15 5 10 15 5 10 15 5 10 15 5 10 15 5 10 15 5 10 15 5 10 15 5 10 15 5 10 15 Value (*) Unit Min. Typ. Max. 300 140 100 200 100 80 200 100 80 40 20 10 80 40 30 130 60 40 100 50 40 150 70 50 100 50 40 100 50 40 20 10 0 40 20 15 65 30 20 50 25 20 -40 -15 -10 7 12 16 ns ns ns ns ns ns 15 15 15 0 0 0 3.5 6 8 ns µs ns MHz (*) Typical temperature coefficient for all VDD value is 0.3 %/°C. 5/9 HCF40174B TEST CIRCUIT CL = 50pF or equivalent (includes jig and probe capacitance) RL = 200KΩ RT = ZOUT of pulse generator (typically 50Ω) WAVEFORM : PROPAGATION DELAY TIMES (f=1MHz; 50% duty cycle) 6/9 HCF40174B Plastic DIP-16 (0.25) MECHANICAL DATA mm. inch DIM. MIN. a1 0.51 B 0.77 TYP MAX. MIN. TYP. MAX. 0.020 1.65 0.030 0.065 b 0.5 0.020 b1 0.25 0.010 D 20 0.787 E 8.5 0.335 e 2.54 0.100 e3 17.78 0.700 F 7.1 0.280 I 5.1 0.201 L Z 3.3 0.130 1.27 0.050 P001C 7/9 HCF40174B SO-16 MECHANICAL DATA DIM. mm. MIN. TYP A a1 inch MAX. MIN. TYP. 1.75 0.1 0.068 0.2 a2 MAX. 0.003 0.007 1.65 0.064 b 0.35 0.46 0.013 0.018 b1 0.19 0.25 0.007 0.010 C 0.5 0.019 c1 45˚ (typ.) D 9.8 E 5.8 10 0.385 6.2 0.228 0.393 0.244 e 1.27 0.050 e3 8.89 0.350 F 3.8 4.0 0.149 0.157 G 4.6 5.3 0.181 0.208 L 0.5 1.27 0.019 0.050 M S 0.62 0.024 8 ˚ (max.) PO13H 8/9 HCF40174B Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. 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