HCF4013B DUAL D-TYPE FLIP FLOP ■ ■ ■ ■ ■ ■ ■ ■ ■ SET - RESET CAPABILITY STATIC FLIP-FLOP OPERATION - RETAINS STATE INDEFINITELY WITH CLOCK LEVEL EITHER "HIGH" OR "LOW" MEDIUM SPEED OPERATION 16MHz (TYP.) CLOCK TOGGLE RATE AT 10V STANDARDIZED SYMMETRICAL OUTPUT CHARACTERISTICS QUIESCENT CURRENT SPECIFIED UP TO 20V 5V, 10V AND 15V PARAMETRIC RATINGS INPUT LEAKAGE CURRENT II = 100nA (MAX) AT VDD = 18V TA = 25°C 100% TESTED FOR QUIESCENT CURRENT MEETS ALL REQUIREMENTS OF JEDEC JESD13B " STANDARD SPECIFICATIONS FOR DESCRIPTION OF B SERIES CMOS DEVICES" DESCRIPTION The HCF4013B is a monolithic integrated circuit fabricated in Metal Oxide Semiconductor technology available in DIP and SOP packages. The HCF4013B consists of two identical, independent data type flip-flops. Each flip-flop has independent data, set, reset, and clock inputs and DIP SOP ORDER CODES PACKAGE TUBE T&R DIP SOP HCF4013BEY HCF4013BM1 HCF4013M013TR Q and Q outputs. This device can be used for shift register applications, and, by connecting Q output to the data input, for counter and toggle applications. The logic level present at the D input is transferred to the Q output during the positive-going transition of the clock pulse. Setting or resetting is independent of the clock and is accomplished by a high level on the set or reset line, respectively PIN CONNECTION September 2001 1/9 HCF4013B INPUT EQUIVALENT CIRCUIT PIN DESCRIPTION PIN No SYMBOL NAME AND FUNCTION 7 CLOCK1 CLOCK2 RESET1 RESET2 SET1, SET2 D1, D2 Q1, Q2 Q1, Q2 VSS 14 VDD 3, 11 4, 10 6, 8 5, 9 1, 13 2, 12 Clock Inputs Reset Inputs Set Inputs Data Inputs Data Outputs Data Outputs Negative Supply Voltage Positive Supply Voltage TRUTH TABLE LOGIC DIAGRAM CLOCK∆ X X X D RESET SET Q Q L L L L H H L L H L X L L Q Q X X X H L H L H H L H H H L H X : Don’t Care ∆ : Low Level ABSOLUTE MAXIMUM RATINGS Symbol VDD Parameter Supply Voltage VI DC Input Voltage II DC Input Current PD Value Unit -0.5 to +22 V -0.5 to VDD + 0.5 ± 10 V mA 200 100 mW mW Top Power Dissipation per Package Power Dissipation per Output Transistor Operating Temperature -55 to +125 °C Tstg Storage Temperature -65 to +150 °C Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied. All voltage values are referred to VSS pin voltage. RECOMMENDED OPERATING CONDITIONS Symbol VDD 2/9 Parameter Supply Voltage VI Input Voltage Top Operating Temperature Value Unit 3 to 20 V 0 to VDD V -55 to 125 °C HCF4013B DC SPECIFICATIONS Test Condition Symbol IL VOH VOL VIH VIL IOH IOL II CI Parameter Quiescent Current High Level Output Voltage Low Level Output Voltage VI (V) 0/5 0/10 0/15 0/20 0/5 0/10 0/15 5/0 10/0 15/0 High Level Input Voltage Low Level Input Voltage Output Drive Current Output Sink Current Input Leakage Current Input Capacitance VO (V) 0/5 0/5 0/10 0/15 0/5 0/10 0/15 0/18 0.5/4.5 1/9 1.5/13.5 4.5/0.5 9/1 13.5/1.5 2.5 4.6 9.5 13.5 0.4 0.5 1.5 Value |IO| VDD (µA) (V) <1 <1 <1 <1 <1 <1 <1 <1 <1 <1 <1 <1 <1 <1 <1 <1 <1 <1 <1 Any Input Any Input 5 10 15 20 5 10 15 5 10 15 5 10 15 5 10 15 5 5 10 15 5 10 15 18 TA = 25°C Min. Typ. Max. 0.02 0.02 0.02 0.04 1 2 4 20 4.95 9.95 14.95 -40 to 85°C -55 to 125°C Min. Min. 30 60 120 600 4.95 9.95 14.95 0.05 0.05 0.05 4.95 9.95 14.95 3.5 7 11 1.5 3 4 -3.2 -1 -2.6 -6.8 1 2.6 6.8 ±0.1 5 7.5 0.05 0.05 0.05 1.5 3 4 V V 1.5 3 4 -1.1 -0.36 -0.9 -2.4 0.36 0.9 2.4 ±1 µA V 3.5 7 11 -1.15 -0.36 -0.9 -2.4 0.36 0.9 2.4 ±10-5 Max. 30 60 120 600 0.05 0.05 0.05 3.5 7 11 -1.36 -0.44 -1.1 -3.0 0.44 1.1 3.0 Max. Unit V mA mA ±1 µA pF The Noise Margin for both "1" and "0" level is: 1V min. with VDD =5V, 2V min. with VDD=10V, 2.5V min. with VDD=15V 3/9 HCF4013B DYNAMIC ELECTRICAL CHARACTERISTICS (Tamb = 25°C, CL = 50pF, RL = 200KΩ, tr = tf = 20 ns) Test Condition Symbol Parameter tTLH tTHL Propagation Delay Time (CLOCK to Q or Q outputs) tPLH tPHL Propagation Delay Time (SET to Q or RESET to Q) Propagation Delay Time(SET to Q or RESET to Q) tTHL tTLH Transition Time fCL (1) tW tr , tf (2) tW tsetup Maximum Clock Input Frequency Clock Pulse Width Clock Input Rise or Fall Time Set or Reset Pulse Width Data Setup Time VDD (V) 5 10 15 5 10 15 5 10 15 5 10 15 5 10 15 5 10 15 5 10 15 5 10 15 5 10 15 Value (*) Unit Min. Typ. Max. 300 130 90 300 130 90 400 170 120 200 100 80 3.5 8 12 140 60 40 150 65 45 150 65 45 200 85 60 100 50 40 7 16 24 70 30 20 90 40 25 20 10 7 ns ns ns MHz ns 15 4 1 180 80 50 40 20 15 ns µs ns ns (*) Typical temperature coefficient for all VDD value is 0.3 %/°C. (1) Input tr, tf = 5ns (2) If more than unit is cascaded in a parallel clocked application, tr should be made less than or equal to the sum of the fixed propagation delay time at 15pF and the transition time of the carry output driving stage for the estimated capacitive load. 4/9 HCF4013B TEST CIRCUIT CL = 50pF or equivalent (includes jig and probe capacitance) RL = 200KΩ RT = ZOUT of pulse generator (typically 50Ω) WAVEFORM 1 : CLOCK TO Qn, Qn PROPAGATION DELAY TIMES, Dn TO CLOCK SETUP AND HOLD TIMES, CLOCK MINIMUM PULSE WITDH, MAXIMUM CLOCK FREQUENCY (f=1MHz; 50% duty cycle) 5/9 HCF4013B WAVEFORM 2 : PROPAGATION DELAY TIMES (Qn, Qn TO SET, RESET), MINIMUM PULSE WIDTH (SET AND RESET) (f=1MHz; 50% duty cycle) 6/9 HCF4013B Plastic DIP-14 MECHANICAL DATA mm. inch DIM. MIN. a1 0.51 B 1.39 TYP MAX. MIN. TYP. MAX. 0.020 1.65 0.055 0.065 b 0.5 0.020 b1 0.25 0.010 D 20 0.787 E 8.5 0.335 e 2.54 0.100 e3 15.24 0.600 F 7.1 0.280 I 5.1 0.201 L Z 3.3 1.27 0.130 2.54 0.050 0.100 P001A 7/9 HCF4013B SO-14 MECHANICAL DATA DIM. mm. MIN. TYP A a1 inch MAX. MIN. TYP. 1.75 0.1 0.068 0.2 a2 MAX. 0.003 0.007 1.65 0.064 b 0.35 0.46 0.013 0.018 b1 0.19 0.25 0.007 0.010 C 0.5 0.019 c1 45° (typ.) D 8.55 8.75 0.336 0.344 E 5.8 6.2 0.228 0.244 e 1.27 0.050 e3 7.62 0.300 F 3.8 4.0 0.149 0.157 G 4.6 5.3 0.181 0.208 L 0.5 1.27 0.019 0.050 M S 0.68 0.026 8° (max.) PO13G 8/9 HCF4013B Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. © The ST logo is a registered trademark of STMicroelectronics © 2001 STMicroelectronics - Printed in Italy - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta - Morocco Singapore - Spain - Sweden - Switzerland - United Kingdom © http://www.st.com 9/9