NTD20N06 Power MOSFET 20 Amps, 60 Volts N–Channel DPAK Designed for low voltage, high speed switching applications in power supplies, converters and power motor controls and bridge circuits. http://onsemi.com Features • • • • • • • 20 AMPERES 60 VOLTS RDS(on) = 46 mΩ Lower RDS(on) Lower VDS(on) Lower Capacitances Lower Total Gate Charge Lower and Tighter VSD Lower Diode Reverse Recovery Time Lower Reverse Recovery Stored Charge N–Channel D Typical Applications • • • • Power Supplies Converters Power Motor Controls Bridge Circuits G 4 MAXIMUM RATINGS (TJ = 25°C unless otherwise noted) Rating Drain–to–Source Voltage Drain–to–Gate Voltage (RGS = 10 MΩ) Gate–to–Source Voltage – Continuous – Non–repetitive (tp10 ms) Drain Current – Continuous @ TA = 25°C – Continuous @ TA = 100°C – Single Pulse (tp10 µs) Total Power Dissipation @ TA = 25°C Derate above 25°C Total Power Dissipation @ TA = 25°C (Note 1.) Total Power Dissipation @ TA = 25°C (Note 2.) Operating and Storage Temperature Range Single Pulse Drain–to–Source Avalanche Energy – Starting TJ = 25°C (VDD = 25 Vdc, VGS = 10 Vdc, L = 1.0 mH, IL(pk) = 18.4 A, VDS = 60 Vdc) Thermal Resistance – Junction–to–Case – Junction–to–Ambient (Note 1.) – Junction–to–Ambient (Note 2.) Maximum Lead Temperature for Soldering Purposes, 1/8″ from case for 10 seconds Symbol Value Unit VDSS VDGR 60 Vdc 60 Vdc VGS VGS 20 30 August, 2001 – Rev. 4 1 2 3 Adc ID ID IDM PD 1 CASE 369A DPAK (Bent Lead) STYLE 2 Vdc NTD20N06 Y WW 20 10 60 Apk 60 0.40 1.88 1.36 W W/°C W W TJ, Tstg –55 to 175 °C 4 Drain EAS 170 mJ YWW NTD 20N06 RθJC RθJA RθJA 2.5 80 110 TL 260 °C/W 2 3 CASE 369 DPAK (Straight Lead) STYLE 2 = Device Code = Year = Work Week MARKING DIAGRAMS & PIN ASSIGNMENTS 4 Drain 1 Gate 2 Drain YWW NTD 20N06 3 Source 1 Gate 3 Source 2 Drain °C 1. When surface mounted to an FR4 board using 1″ pad size, (Cu Area 1.127 in2). 2. When surface mounted to an FR4 board using the minimum recommended pad size, (Cu Area 0.412 in2). Semiconductor Components Industries, LLC, 2001 4 S 1 ORDERING INFORMATION Device NTD20N06 Package Shipping DPAK 75 Units/Rail NTD20N06–1 DPAK Straight Lead 75 Units/Rail NTD20N06T4 DPAK 2500 Tape & Reel Publication Order Number: NTD20N06/D NTD20N06 ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted) Characteristic Symbol Min Typ Max Unit 60 – 71.7 79.4 – – – – – – 1.0 10 – – ±100 2.0 – 2.91 6.9 4.0 – – 37.5 46 – – 0.78 1.57 1.10 – gFS – 13.2 – mhos Ciss – 725 1015 pF Coss – 213 300 Crss – 58 120 td(on) – 9.5 20 OFF CHARACTERISTICS Drain–to–Source Breakdown Voltage (Note NO TAG) (VGS = 0 Vdc, ID = 250 µAdc) Temperature Coefficient (Positive) V(BR)DSS Zero Gate Voltage Drain Current (VDS = 60 Vdc, VGS = 0 Vdc) (VDS = 60 Vdc, VGS = 0 Vdc, TJ = 150°C) IDSS Gate–Body Leakage Current (VGS = ±20 Vdc, VDS = 0 Vdc) IGSS Vdc mV/°C µAdc nAdc ON CHARACTERISTICS (Note NO TAG) Gate Threshold Voltage (Note NO TAG) (VDS = VGS, ID = 250 µAdc) Threshold Temperature Coefficient (Negative) VGS(th) Static Drain–to–Source On–Resistance (Note NO TAG) (VGS = 10 Vdc, ID = 10 Adc) RDS(on) Static Drain–to–Source On–Voltage (Note NO TAG) (VGS = 10 Vdc, ID = 20 Adc) (VGS = 10 Vdc, ID = 10 Adc, TJ = 150°C) VDS(on) Forward Transconductance (Note NO TAG) (VDS = 7.0 Vdc, ID = 6.0 Adc) Vdc mV/°C mΩ Vdc DYNAMIC CHARACTERISTICS Input Capacitance (VDS = 25 Vd Vdc, VGS = 0 Vdc, Vd f = 1.0 MHz) Output Capacitance Transfer Capacitance SWITCHING CHARACTERISTICS (Note NO TAG) Turn–On Delay Time (VDD = 30 Vdc, ID = 20 Adc, VGS = 10 Vdc, Vdc RG = 9.1 Ω) (Note NO TAG) Rise Time Turn–Off Delay Time Fall Time Gate Charge (VDS = 48 Vdc, Vd ID = 20 Adc, Ad VGS = 10 Vdc) (Note NO TAG) ns tr – 60.5 120 td(off) – 27.1 60 tf – 37.1 80 QT – 21.2 30 Q1 – 5.6 – Q2 – 7.3 – VSD – – 1.0 0.87 1.2 – Vdc trr – 42.9 – ns ta – 33 – tb – 9.9 – QRR – 0.084 – nC SOURCE–DRAIN DIODE CHARACTERISTICS Forward On–Voltage (IS = 20 Adc, VGS = 0 Vdc) (Note NO TAG) (IS = 20 Adc, VGS = 0 Vdc, TJ = 150°C) Reverse Recovery Time Ad VGS = 0 Vdc, Vd (IS = 20 Adc, dIS/dt = 100 A/µs) (Note NO TAG) Reverse Recovery Stored Charge 3. Pulse Test: Pulse Width ≤ 300 µs, Duty Cycle ≤ 2%. 4. Switching characteristics are independent of operating junction temperatures. http://onsemi.com 2 µC NTD20N06 40 40 7V ID, DRAIN CURRENT (AMPS) ID, DRAIN CURRENT (AMPS) 32 8V 6V 24 5.5 V 16 5V 8 4.5 V 0 1 3 2 4 5 TJ = 25°C 8 3.4 TJ = –55°C 4.2 5 5.8 6.6 Figure 1. On–Region Characteristics Figure 2. Transfer Characteristics RDS(on), DRAIN–TO–SOURCE RESISTANCE (Ω) VGS, GATE–TO–SOURCE VOLTAGE (VOLTS) TJ = 100°C 0.045 0.035 TJ = 25°C 0.025 TJ = –55°C 0 8 16 40 32 24 7.4 0.065 VGS = 15 V 0.055 TJ = 100°C 0.045 TJ = 25°C 0.035 0.025 0.015 TJ = –55°C 0 8 16 24 32 ID, DRAIN CURRENT (AMPS) ID, DRAIN CURRENT (AMPS) Figure 3. On–Resistance versus Gate–to–Source Voltage Figure 4. On–Resistance versus Drain Current and Gate Voltage 40 10000 VGS = 0 V ID = 10 A VGS = 10 V TJ = 150°C 1000 IDSS, LEAKAGE (nA) RDS(on), DRAIN–TO–SOURCE RESISTANCE (NORMALIZED) 16 VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS) 0.055 1.8 24 0 2.6 VGS = 10 V 2 32 TJ = 100°C 0.065 0.015 VDS ≥ 10 V 6.5 V 9V 0 RDS(on), DRAIN–TO–SOURCE RESISTANCE (Ω) VGS = 10 V 1.6 1.4 1.2 1 TJ = 125°C 100 TJ = 100°C 10 0.8 0.6 –50 –25 1 0 25 50 75 100 125 150 175 0 10 20 30 40 50 TJ, JUNCTION TEMPERATURE (°C) VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS) Figure 5. On–Resistance Variation with Temperature Figure 6. Drain–to–Source Leakage Current versus Voltage http://onsemi.com 3 60 NTD20N06 POWER MOSFET SWITCHING The capacitance (Ciss) is read from the capacitance curve at Switching behavior is most easily modeled and predicted a voltage corresponding to the off–state condition when by recognizing that the power MOSFET is charge calculating td(on) and is read at a voltage corresponding to the controlled. The lengths of various switching intervals (∆t) on–state when calculating td(off). are determined by how fast the FET input capacitance can At high switching speeds, parasitic circuit elements be charged by current from the generator. complicate the analysis. The inductance of the MOSFET The published capacitance data is difficult to use for source lead, inside the package and in the circuit wiring calculating rise and fall because drain–gate capacitance which is common to both the drain and gate current paths, varies greatly with applied voltage. Accordingly, gate produces a voltage at the source which reduces the gate drive charge data is used. In most cases, a satisfactory estimate of current. The voltage is determined by Ldi/dt, but since di/dt average input current (IG(AV)) can be made from a is a function of drain current, the mathematical solution is rudimentary analysis of the drive circuit so that complex. The MOSFET output capacitance also t = Q/IG(AV) complicates the mathematics. And finally, MOSFETs have finite internal gate resistance which effectively adds to the During the rise and fall time interval when switching a resistance of the driving source, but the internal resistance resistive load, VGS remains virtually constant at a level is difficult to measure and, consequently, is not specified. known as the plateau voltage, VSGP. Therefore, rise and fall The resistive switching time variation versus gate times may be approximated by the following: resistance (Figure 9) shows how typical switching tr = Q2 x RG/(VGG – VGSP) performance is affected by the parasitic circuit elements. If tf = Q2 x RG/VGSP the parasitics were not present, the slope of the curves would maintain a value of unity regardless of the switching speed. where The circuit used to obtain the data is constructed to minimize VGG = the gate drive voltage, which varies from zero to VGG common inductance in the drain and gate circuit loops and RG = the gate drive resistance is believed readily achievable with board mounted and Q2 and VGSP are read from the gate charge curve. components. Most power electronic loads are inductive; the data in the figure is taken with a resistive load, which During the turn–on and turn–off delay times, gate current is approximates an optimally snubbed inductive load. Power not constant. The simplest calculation uses appropriate MOSFETs may be safely operated into an inductive load; values from the capacitance curves in a standard equation for however, snubbing reduces switching losses. voltage change in an RC network. The equations are: td(on) = RG Ciss In [VGG/(VGG – VGSP)] td(off) = RG Ciss In (VGG/VGSP) C, CAPACITANCE (pF) 2000 1600 VDS = 0 V VGS = 0 V TJ = 25°C Ciss 1200 Crss Ciss 800 400 Coss Crss 0 10 5 VGS 5 0 10 15 20 25 VDS GATE–TO–SOURCE OR DRAIN–TO–SOURCE VOLTAGE (VOLTS) Figure 7. Capacitance Variation http://onsemi.com 4 1000 12 VDS = 30 V ID = 20 A VGS = 10 V QT 10 8 VGS Q2 Q1 6 t, TIME (ns) VGS , GATE–TO–SOURCE VOLTAGE (VOLTS) NTD20N06 4 100 tf tr td(off) 10 td(on) 2 ID = 20 A TJ = 25°C 0 1 0 4 16 20 8 12 QG, TOTAL GATE CHARGE (nC) 24 1 Figure 8. Gate–To–Source and Drain–To–Source Voltage versus Total Charge 10 RG, GATE RESISTANCE (OHMS) 100 Figure 9. Resistive Switching Time Variation versus Gate Resistance DRAIN–TO–SOURCE DIODE CHARACTERISTICS IS, SOURCE CURRENT (AMPS) 20 VGS = 0 V TJ = 25°C 16 12 8 4 0 0.6 0.8 0.9 0.7 VSD, SOURCE–TO–DRAIN VOLTAGE (VOLTS) 1 Figure 10. Diode Forward Voltage versus Current SAFE OPERATING AREA reliable operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than the rated limit and adjusted for operating conditions differing from those specified. Although industry practice is to rate in terms of energy, avalanche energy capability is not a constant. The energy rating decreases non–linearly with an increase of peak current in avalanche and peak junction temperature. Although many E–FETs can withstand the stress of drain–to–source avalanche at currents up to rated pulsed current (IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the accompanying graph (Figure 12). Maximum energy at currents below rated continuous ID can safely be assumed to equal the values indicated. The Forward Biased Safe Operating Area curves define the maximum simultaneous drain–to–source voltage and drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25°C. Peak repetitive pulsed power limits are determined by using the thermal response data in conjunction with the procedures discussed in AN569, “Transient Thermal Resistance – General Data and Its Use.” Switching between the off–state and the on–state may traverse any load line provided neither rated peak current (IDM) nor rated voltage (VDSS) is exceeded and the transition time (tr,tf) do not exceed 10 µs. In addition the total power averaged over a complete switching cycle must not exceed (TJ(MAX) – TC)/(RθJC). A Power MOSFET designated E–FET can be safely used in switching circuits with unclamped inductive loads. For http://onsemi.com 5 NTD20N06 I D, DRAIN CURRENT (AMPS) 100 VGS = 20 V SINGLE PULSE TC = 25°C 10 10 µs 100 µs 1 ms 10 ms 1 dc RDS(on) LIMIT THERMAL LIMIT PACKAGE LIMIT 0.1 r(t), EFFECTIVE TRANSIENT THERMAL RESISTANCE (NORMALIZED) 0.1 1 10 VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS) 100 EAS , SINGLE PULSE DRAIN–TO–SOURCE AVALANCHE ENERGY (mJ) SAFE OPERATING AREA 180 ID = 18.4 A 160 140 120 100 80 60 40 20 0 25 Figure 11. Maximum Rated Forward Biased Safe Operating Area 150 50 75 100 125 175 TJ, STARTING JUNCTION TEMPERATURE (°C) Figure 12. Maximum Avalanche Energy versus Starting Junction Temperature 1.0 D = 0.5 0.2 0.1 0.1 0.05 P(pk) 0.02 0.01 SINGLE PULSE 0.01 0.00001 t1 t2 DUTY CYCLE, D = t1/t2 0.0001 0.001 0.01 t, TIME (s) RθJC(t) = r(t) RθJC D CURVES APPLY FOR POWER PULSE TRAIN SHOWN READ TIME AT t1 TJ(pk) – TC = P(pk) RθJC(t) 0.1 Figure 13. Thermal Response di/dt IS trr ta tb TIME 0.25 IS tp IS Figure 14. Diode Reverse Recovery Waveform http://onsemi.com 6 1 10 NTD20N06 INFORMATION FOR USING THE DPAK SURFACE MOUNT PACKAGE RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS Surface mount board layout is a critical portion of the total design. The footprint for the semiconductor packages must be the correct size to ensure proper solder connection 0.165 4.191 interface between the board and the package. With the correct pad geometry, the packages will self align when subjected to a solder reflow process. 0.100 2.54 0.118 3.0 0.063 1.6 0.190 4.826 0.243 6.172 inches mm http://onsemi.com 7 NTD20N06 SOLDER STENCIL GUIDELINES pattern of the opening in the stencil for the drain pad is not critical as long as it allows approximately 50% of the pad to be covered with paste. Prior to placing surface mount components onto a printed circuit board, solder paste must be applied to the pads. Solder stencils are used to screen the optimum amount. These stencils are typically 0.008 inches thick and may be made of brass or stainless steel. For packages such as the SC–59, SC–70/SOT–323, SOD–123, SOT–23, SOT–143, SOT–223, SO–8, SO–14, SO–16, and SMB/SMC diode packages, the stencil opening should be the same as the pad size or a 1:1 registration. This is not the case with the DPAK and D2PAK packages. If one uses a 1:1 opening to screen solder onto the drain pad, misalignment and/or “tombstoning” may occur due to an excess of solder. For these two packages, the opening in the stencil for the paste should be approximately 50% of the tab area. The opening for the leads is still a 1:1 registration. Figure 15 shows a typical stencil for the DPAK and D2PAK packages. The ÇÇ ÇÇ ÇÇ ÇÇ ÇÇ ÇÇÇ ÇÇÇ ÇÇÇ ÇÇÇ ÇÇ ÇÇÇ ÇÇÇ ÇÇ ÇÇÇ ÇÇÇ ÇÇÇ SOLDER PASTE OPENINGS STENCIL Figure 15. Typical Stencil for DPAK and D2PAK Packages SOLDERING PRECAUTIONS • When shifting from preheating to soldering, the maximum temperature gradient shall be 5°C or less. • After soldering has been completed, the device should be allowed to cool naturally for at least three minutes. Gradual cooling should be used as the use of forced cooling will increase the temperature gradient and result in latent failure due to mechanical stress. • Mechanical stress or shock should not be applied during cooling. The melting temperature of solder is higher than the rated temperature of the device. When the entire device is heated to a high temperature, failure to complete soldering within a short time could result in device failure. Therefore, the following items should always be observed in order to minimize the thermal stress to which the devices are subjected. • Always preheat the device. • The delta temperature between the preheat and soldering should be 100°C or less.* • When preheating and soldering, the temperature of the leads and the case must not exceed the maximum temperature ratings as shown on the data sheet. When using infrared heating with the reflow soldering method, the difference shall be a maximum of 10°C. • The soldering temperature and time shall not exceed 260°C for more than 10 seconds. * Soldering a device without preheating can cause excessive thermal shock and stress which can result in damage to the device. * Due to shadowing and the inability to set the wave height to incorporate other surface mount components, the D2PAK is not recommended for wave soldering. http://onsemi.com 8 NTD20N06 TYPICAL SOLDER HEATING PROFILE The line on the graph shows the actual temperature that might be experienced on the surface of a test board at or near a central solder joint. The two profiles are based on a high density and a low density board. The Vitronics SMD310 convection/infrared reflow soldering system was used to generate this profile. The type of solder used was 62/36/2 Tin Lead Silver with a melting point between 177–189°C. When this type of furnace is used for solder reflow work, the circuit boards and solder joints tend to heat first. The components on the board are then heated by conduction. The circuit board, because it has a large surface area, absorbs the thermal energy more efficiently, then distributes this energy to the components. Because of this effect, the main body of a component may be up to 30 degrees cooler than the adjacent solder joint. For any given circuit board, there will be a group of control settings that will give the desired heat pattern. The operator must set temperatures for several heating zones, and a figure for belt speed. Taken together, these control settings make up a heating “profile” for that particular circuit board. On machines controlled by a computer, the computer remembers these profiles from one operating session to the next. Figure 16 shows a typical heating profile for use when soldering a surface mount device to a printed circuit board. This profile will vary among soldering systems but it is a good starting point. Factors that can affect the profile include the type of soldering system in use, density and types of components on the board, type of solder used, and the type of board or substrate material being used. This profile shows temperature versus time. STEP 1 PREHEAT ZONE 1 “RAMP” 200°C STEP 2 STEP 3 VENT HEATING “SOAK” ZONES 2 & 5 “RAMP” DESIRED CURVE FOR HIGH MASS ASSEMBLIES STEP 4 HEATING ZONES 3 & 6 “SOAK” 160°C STEP 5 STEP 6 STEP 7 HEATING VENT COOLING ZONES 4 & 7 205° TO 219°C “SPIKE” PEAK AT 170°C SOLDER JOINT 150°C 150°C 100°C 140°C 100°C SOLDER IS LIQUID FOR 40 TO 80 SECONDS (DEPENDING ON MASS OF ASSEMBLY) DESIRED CURVE FOR LOW MASS ASSEMBLIES 5°C TIME (3 TO 7 MINUTES TOTAL) TMAX Figure 16. Typical Solder Heating Profile http://onsemi.com 9 NTD20N06 PACKAGE DIMENSIONS DPAK CASE 369A–13 ISSUE AB –T– C B V NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. SEATING PLANE E R 4 Z A S 1 2 3 U K F J L H D G 2 PL 0.13 (0.005) M T DIM A B C D E F G H J K L R S U V Z INCHES MIN MAX 0.235 0.250 0.250 0.265 0.086 0.094 0.027 0.035 0.033 0.040 0.037 0.047 0.180 BSC 0.034 0.040 0.018 0.023 0.102 0.114 0.090 BSC 0.175 0.215 0.020 0.050 0.020 --0.030 0.050 0.138 --- STYLE 2: PIN 1. 2. 3. 4. http://onsemi.com 10 GATE DRAIN SOURCE DRAIN MILLIMETERS MIN MAX 5.97 6.35 6.35 6.73 2.19 2.38 0.69 0.88 0.84 1.01 0.94 1.19 4.58 BSC 0.87 1.01 0.46 0.58 2.60 2.89 2.29 BSC 4.45 5.46 0.51 1.27 0.51 --0.77 1.27 3.51 --- NTD20N06 PACKAGE DIMENSIONS DPAK CASE 369–07 ISSUE M C B V E R 4 A 1 2 3 S –T– SEATING PLANE K J F H D G 3 PL 0.13 (0.005) M NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. DIM A B C D E F G H J K R S V INCHES MIN MAX 0.235 0.250 0.250 0.265 0.086 0.094 0.027 0.035 0.033 0.040 0.037 0.047 0.090 BSC 0.034 0.040 0.018 0.023 0.350 0.380 0.175 0.215 0.050 0.090 0.030 0.050 STYLE 2: PIN 1. 2. 3. 4. T http://onsemi.com 11 GATE DRAIN SOURCE DRAIN MILLIMETERS MIN MAX 5.97 6.35 6.35 6.73 2.19 2.38 0.69 0.88 0.84 1.01 0.94 1.19 2.29 BSC 0.87 1.01 0.46 0.58 8.89 9.65 4.45 5.46 1.27 2.28 0.77 1.27 NTD20N06 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. PUBLICATION ORDERING INFORMATION Literature Fulfillment: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303–675–2175 or 800–344–3860 Toll Free USA/Canada Fax: 303–675–2176 or 800–344–3867 Toll Free USA/Canada Email: [email protected] JAPAN: ON Semiconductor, Japan Customer Focus Center 4–32–1 Nishi–Gotanda, Shinagawa–ku, Tokyo, Japan 141–0031 Phone: 81–3–5740–2700 Email: [email protected] ON Semiconductor Website: http://onsemi.com For additional information, please contact your local Sales Representative. N. American Technical Support: 800–282–9855 Toll Free USA/Canada http://onsemi.com 12 NTD20N06/D