ETC NTB18N06

NTP18N06, NTB18N06
Power MOSFET
15 Amps, 60 Volts
N–Channel TO–220
Designed for low voltage, high speed switching applications in
power supplies, converters and power motor controls and bridge
circuits.
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15 AMPERES
60 VOLTS
RDS(on) = 90 mΩ
Typical Applications
•
•
•
•
Power Supplies
Converters
Power Motor Controls
Bridge Circuits
N–Channel
D
MAXIMUM RATINGS (TJ = 25°C unless otherwise noted)
Symbol
Value
Unit
Drain–to–Source Voltage
VDSS
60
Vdc
Drain–to–Gate Voltage (RGS = 10 mΩ)
VDGR
60
Vdc
Gate–to–Source Voltage
– Continuous
– Non–Repetitive (tp 10 ms)
VGS
Rating
Drain Current
– Continuous @ TA = 25°C
– Continuous @ TA = 100°C
– Single Pulse (tp 10 s)
Total Power Dissipation @ TA = 25°C
Derate above 25°C
Operating and Storage Temperature Range
Single Pulse Drain–to–Source Avalanche
Energy – Starting TJ = 25°C
(VDD = 25 Vdc, VGS = 10 Vdc, VDS = 60 Vdc,
IL(pk) = 11 A, L = 1.0 mH, RG = 25 Ω)
Thermal Resistance
– Junction–to–Case
– Junction–to–Ambient
Maximum Lead Temperature for Soldering
Purposes, 1/8″ from case for 10 seconds
G
4
Vdc
20
30
S
4
1
ID
ID
IDM
15
8.0
45
Adc
Adc
Apk
PD
48.4
0.32
Watts
W/°C
TJ, Tstg
–55 to
+175
°C
EAS
61
mJ
3
1
D2PAK
CASE 418B
STYLE 2
TO–220AB
CASE 221A
STYLE 5
2
MARKING DIAGRAMS
& PIN ASSIGNMENTS
3
4
Drain
4
Drain
NTx18N06
LLYWW
°C/W
RθJC
RθJA
3.1
72.5
TL
260
2
NTx18N06
LLYWW
°C
1
Gate
3
Source
2
Drain
1
Gate
NTx18N06
x
LL
Y
WW
2
Drain
3
Source
= Device Code
= B or P
= Location Code
= Year
= Work Week
ORDERING INFORMATION
Device
 Semiconductor Components Industries, LLC, 2001
November, 2001 – Rev. 1
1
Package
Shipping
NTP18N06
TO–220AB
50 Units/Rail
NTB18N06
D2PAK
50 Units/Rail
NTB18N06T4
D2PAK
800/Tape & Reel
Publication Order Number:
NTP18N06/D
NTP18N06, NTB18N06
ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted)
Characteristic
Symbol
Min
Typ
Max
Unit
60
–
67
62.4
–
–
–
–
–
–
1.0
10
–
–
±100
2.0
–
2.9
6.2
4.0
–
–
76
90
–
–
1.2
1.08
1.62
–
gFS
–
6.8
–
mhos
Ciss
–
325
450
pF
Coss
–
108
150
Crss
–
34
70
td(on)
–
10
15
tr
–
25
70
td(off)
–
14
50
Fall Time
tf
–
13
50
Gate Charge
Qt
–
12
22
Q1
–
4.1
–
Q2
–
4.5
–
VSD
–
–
0.95
0.84
1.15
–
Vdc
trr
–
35
–
ns
ta
–
27
–
tb
–
7.4
–
QRR
–
0.050
–
OFF CHARACTERISTICS
Drain–to–Source Breakdown Voltage (Note 1)
(VGS = 0 Vdc, ID = 250 µAdc)
Temperature Coefficient (Positive)
V(BR)DSS
Zero Gate Voltage Drain Current
(VGS = 0 Vdc, VDS = 60 Vdc)
(VGS = 0 Vdc, VDS = 60 Vdc, TJ = 150°C)
IDSS
Gate–Body Leakage Current (VGS = ±20 Vdc, VDS = 0 Vdc)
IGSS
Vdc
mV/°C
µAdc
nAdc
ON CHARACTERISTICS (Note 1)
Gate Threshold Voltage (Note 1)
(VDS = VGS, ID = 250 µAdc)
Threshold Temperature Coefficient (Negative)
VGS(th)
Static Drain–to–Source On–Resistance (Note 1)
(VGS = 10 Vdc, ID = 7.5 Adc)
RDS(on)
Static Drain–to–Source On–Voltage (Note 1)
(VGS = 10 Vdc, ID = 15 Adc)
(VGS = 10 Vdc, ID = 7.5 Adc, TJ = 150°C)
VDS(on)
Forward Transconductance (Note 1) (VDS = 7.0 Vdc, ID = 6.0 Adc)
Vdc
mV/°C
mΩ
Vdc
DYNAMIC CHARACTERISTICS
Input Capacitance
Output Capacitance
(VDS = 25 Vd
Vdc, VGS = 0 Vdc,
Vd
f = 1.0 MHz)
Reverse Transfer Capacitance
SWITCHING CHARACTERISTICS (Note 2)
Turn–On Delay Time
Rise Time
Turn–Off Delay Time
(VDD = 30 Vdc, ID = 15 Adc,
VGS = 10 Vdc,
Vdc
RG = 9.1 Ω) (Note 1)
(VDS = 48 Vdc,
Vd ID = 15 Adc,
Ad
VGS = 10 Vdc) (Note 1)
ns
nC
SOURCE–DRAIN DIODE CHARACTERISTICS
Diode Forward On–Voltage
(IS = 15 Adc, VGS = 0 Vdc) (Note 1)
(IS = 15 Adc, VGS = 0 Vdc, TJ = 150°C)
Reverse Recovery Time
(IS = 15 Adc,
Adc VGS = 0 Vdc,
Vdc
dIS/dt = 100 A/µs) (Note 1)
Reverse Recovery Stored
Charge
1. Pulse Test: Pulse Width = 300 µs, Duty Cycle = 2%.
2. Switching characteristics are independent of operating junction temperature.
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2
µC
NTP18N06, NTB18N06
VGS = 10 V
32
9V
7V
24
6.5 V
16
6V
5.5 V
8
5V
4.5 V
0
0
VDS ≥ 10 V
8V
ID, DRAIN CURRENT (AMPS)
ID, DRAIN CURRENT (AMPS)
32
1
2
3
4
VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS)
24
16
TJ = 25°C
8
TJ = 100°C
0
5
3
4
5
6
7
VGS, GATE–TO–SOURCE VOLTAGE (VOLTS)
VGS = 10 V
TJ = 100°C
0.12
TJ = 25°C
0.08
TJ = –55°C
0.04
0
4
8
12
16
20
24
ID, DRAIN CURRENT (AMPS)
28
32
RDS(on), DRAIN–TO–SOURCE RESISTANCE ()
0.2
0
0.2
VGS = 15 V
0.16
0.12
TJ = 100°C
0.08
TJ = 25°C
TJ = –55°C
0.04
0
0
Figure 3. On–Resistance versus
Gate–to–Source Voltage
4
8
12
16
20
24
ID, DRAIN CURRENT (AMPS)
28
32
Figure 4. On–Resistance versus Drain Current
and Gate Voltage
2
1.8
8
Figure 2. Transfer Characteristics
1000
ID = 7.5 A
VGS = 10 V
VGS = 0 V
IDSS, LEAKAGE (nA)
RDS(on), DRAIN–TO–SOURCE RESISTANCE (NORMALIZED)
RDS(on), DRAIN–TO–SOURCE RESISTANCE ()
Figure 1. On–Region Characteristics
0.16
TJ = –55°C
1.6
1.4
1.2
1
TJ = 150°C
100
10
TJ = 100°C
0.8
0.6
–50 –25
0
25
50
75 100 125 150
TJ, JUNCTION TEMPERATURE (°C)
1
175
0
Figure 5. On–Resistance Variation with
Temperature
10
20
30
40
50
VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS)
Figure 6. Drain–to–Source Leakage Current
versus Voltage
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3
60
NTP18N06, NTB18N06
POWER MOSFET SWITCHING
The capacitance (Ciss) is read from the capacitance curve at
Switching behavior is most easily modeled and predicted
a voltage corresponding to the off–state condition when
by recognizing that the power MOSFET is charge
calculating td(on) and is read at a voltage corresponding to the
controlled. The lengths of various switching intervals (∆t)
on–state when calculating td(off).
are determined by how fast the FET input capacitance can
At high switching speeds, parasitic circuit elements
be charged by current from the generator.
complicate
the analysis. The inductance of the MOSFET
The published capacitance data is difficult to use for
source
lead,
inside the package and in the circuit wiring
calculating rise and fall because drain–gate capacitance
which
is
common
to both the drain and gate current paths,
varies greatly with applied voltage. Accordingly, gate
produces
a
voltage
at the source which reduces the gate drive
charge data is used. In most cases, a satisfactory estimate of
current.
The
voltage
is determined by Ldi/dt, but since di/dt
average input current (IG(AV)) can be made from a
is
a
function
of
drain
current, the mathematical solution is
rudimentary analysis of the drive circuit so that
complex. The MOSFET output capacitance also
t = Q/IG(AV)
complicates the mathematics. And finally, MOSFETs have
finite internal gate resistance which effectively adds to the
During the rise and fall time interval when switching a
resistance of the driving source, but the internal resistance
resistive load, VGS remains virtually constant at a level
is difficult to measure and, consequently, is not specified.
known as the plateau voltage, VSGP. Therefore, rise and fall
The resistive switching time variation versus gate
times may be approximated by the following:
resistance
(Figure 9) shows how typical switching
tr = Q2 x RG/(VGG – VGSP)
performance is affected by the parasitic circuit elements. If
tf = Q2 x RG/VGSP
the parasitics were not present, the slope of the curves would
maintain a value of unity regardless of the switching speed.
where
The circuit used to obtain the data is constructed to minimize
VGG = the gate drive voltage, which varies from zero to VGG
common inductance in the drain and gate circuit loops and
RG = the gate drive resistance
is believed readily achievable with board mounted
and Q2 and VGSP are read from the gate charge curve.
components. Most power electronic loads are inductive; the
data in the figure is taken with a resistive load, which
During the turn–on and turn–off delay times, gate current is
approximates an optimally snubbed inductive load. Power
not constant. The simplest calculation uses appropriate
MOSFETs may be safely operated into an inductive load;
values from the capacitance curves in a standard equation for
however, snubbing reduces switching losses.
voltage change in an RC network. The equations are:
td(on) = RG Ciss In [VGG/(VGG – VGSP)]
td(off) = RG Ciss In (VGG/VGSP)
900
C, CAPACITANCE (pF)
800
VDS = 0 V VGS = 0 V
TJ = 25°C
Ciss
700
600
500
Crss
400
Ciss
300
200
Coss
100
Crss
0
10
5
5
0
VGS
10
15
20
25
VDS
GATE–TO–SOURCE OR DRAIN–TO–SOURCE VOLTAGE (VOLTS)
Figure 7. Capacitance Variation
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4
1000
12
VDS = 30 V
ID = 15 A
VGS = 10 V
QT
10
VGS
8
Q1
6
t, TIME (ns)
VGS , GATE–TO–SOURCE VOLTAGE (VOLTS)
NTP18N06, NTB18N06
Q2
tr
td(off)
10
td(on)
tf
4
2
ID = 15 A
TJ = 25°C
0
1
0
2
4
6
8
10
QG, TOTAL GATE CHARGE (nC)
12
1
Figure 8. Gate–To–Source and Drain–To–Source
Voltage versus Total Charge
10
RG, GATE RESISTANCE (Ω)
100
Figure 9. Resistive Switching Time
Variation versus Gate Resistance
DRAIN–TO–SOURCE DIODE CHARACTERISTICS
IS, SOURCE CURRENT (AMPS)
16
VGS = 0 V
TJ = 25°C
12
8
4
0
0.6
0.84
0.92
0.68
0.76
VSD, SOURCE–TO–DRAIN VOLTAGE (VOLTS)
1
Figure 10. Diode Forward Voltage versus Current
SAFE OPERATING AREA
reliable operation, the stored energy from circuit inductance
dissipated in the transistor while in avalanche must be less
than the rated limit and adjusted for operating conditions
differing from those specified. Although industry practice is
to rate in terms of energy, avalanche energy capability is not
a constant. The energy rating decreases non–linearly with an
increase of peak current in avalanche and peak junction
temperature.
Although many E–FETs can withstand the stress of
drain–to–source avalanche at currents up to rated pulsed
current (IDM), the energy rating is specified at rated
continuous current (ID), in accordance with industry custom.
The energy rating must be derated for temperature as shown
in the accompanying graph (Figure 12). Maximum energy at
currents below rated continuous ID can safely be assumed to
equal the values indicated.
The Forward Biased Safe Operating Area curves define
the maximum simultaneous drain–to–source voltage and
drain current that a transistor can handle safely when it is
forward biased. Curves are based upon maximum peak
junction temperature and a case temperature (TC) of 25°C.
Peak repetitive pulsed power limits are determined by using
the thermal response data in conjunction with the procedures
discussed in AN569, “Transient Thermal Resistance –
General Data and Its Use.”
Switching between the off–state and the on–state may
traverse any load line provided neither rated peak current
(IDM) nor rated voltage (VDSS) is exceeded and the
transition time (tr,tf) do not exceed 10 µs. In addition the total
power averaged over a complete switching cycle must not
exceed (TJ(MAX) – TC)/(RθJC).
A Power MOSFET designated E–FET can be safely used
in switching circuits with unclamped inductive loads. For
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5
NTP18N06, NTB18N06
I D, DRAIN CURRENT (AMPS)
100
VGS = 20 V
SINGLE PULSE
TC = 25°C
10 µs
10
100 µs
1 ms
10 ms
1
dc
RDS(on) LIMIT
THERMAL LIMIT
PACKAGE LIMIT
0.1
0.1
1
10
VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS)
100
EAS , SINGLE PULSE DRAIN–TO–SOURCE
AVALANCHE ENERGY (mJ)
SAFE OPERATING AREA
r(t), TRANSIENT THERMAL RESISTANCE
Figure 11. Maximum Rated Forward Biased
Safe Operating Area
80
ID = 11 A
60
40
20
0
25
150
50
75
100
125
175
TJ, STARTING JUNCTION TEMPERATURE (°C)
Figure 12. Maximum Avalanche Energy versus
Starting Junction Temperature
1.0
D = 0.5
0.2
0.1
0.1
0.05
0.02
0.01
0.01
SINGLE PULSE
0.000001
0.00001
0.0001
0.001
t, TIME (s)
0.01
0.1
Figure 13. Thermal Response
di/dt
IS
trr
ta
tb
TIME
0.25 IS
tp
IS
Figure 14. Diode Reverse Recovery Waveform
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6
1
10
NTP18N06, NTB18N06
INFORMATION FOR USING THE D2PAK SURFACE MOUNT PACKAGE
RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS
Surface mount board layout is a critical portion of the
total design. The footprint for the semiconductor packages
must be the correct size to ensure proper solder connection
interface between the board and the package. With the
correct pad geometry, the packages will self align when
subjected to a solder reflow process.
0.33
8.38
0.08
2.032
0.42
10.66
0.24
6.096
0.04
1.016
0.12
3.05
0.63
17.02
inches
mm
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7
NTP18N06, NTB18N06
SOLDER STENCIL GUIDELINES
pattern of the opening in the stencil for the drain pad is not
critical as long as it allows approximately 50% of the pad to
be covered with paste.
Prior to placing surface mount components onto a printed
circuit board, solder paste must be applied to the pads.
Solder stencils are used to screen the optimum amount.
These stencils are typically 0.008 inches thick and may be
made of brass or stainless steel. For packages such as the
SC–59, SC–70/SOT–323, SOD–123, SOT–23, SOT–143,
SOT–223, SO–8, SO–14, SO–16, and SMB/SMC diode
packages, the stencil opening should be the same as the pad
size or a 1:1 registration. This is not the case with the DPAK
and D2PAK packages. If one uses a 1:1 opening to screen
solder onto the drain pad, misalignment and/or
“tombstoning” may occur due to an excess of solder. For
these two packages, the opening in the stencil for the paste
should be approximately 50% of the tab area. The opening
for the leads is still a 1:1 registration. Figure 15 shows a
typical stencil for the DPAK and D2PAK packages. The
ÇÇ
ÇÇ
ÇÇ
ÇÇ
ÇÇ
ÇÇÇ
ÇÇÇ
ÇÇÇ
ÇÇÇ ÇÇ
ÇÇÇ
ÇÇÇ ÇÇ
ÇÇÇ
ÇÇÇ
ÇÇÇ
SOLDER PASTE
OPENINGS
STENCIL
Figure 15. Typical Stencil for DPAK and
D2PAK Packages
SOLDERING PRECAUTIONS
• When shifting from preheating to soldering, the
maximum temperature gradient shall be 5°C or less.
• After soldering has been completed, the device should
be allowed to cool naturally for at least three minutes.
Gradual cooling should be used as the use of forced
cooling will increase the temperature gradient and
result in latent failure due to mechanical stress.
• Mechanical stress or shock should not be applied
during cooling.
The melting temperature of solder is higher than the rated
temperature of the device. When the entire device is heated
to a high temperature, failure to complete soldering within
a short time could result in device failure. Therefore, the
following items should always be observed in order to
minimize the thermal stress to which the devices are
subjected.
• Always preheat the device.
• The delta temperature between the preheat and
soldering should be 100°C or less.*
• When preheating and soldering, the temperature of the
leads and the case must not exceed the maximum
temperature ratings as shown on the data sheet. When
using infrared heating with the reflow soldering
method, the difference shall be a maximum of 10°C.
• The soldering temperature and time shall not exceed
260°C for more than 10 seconds.
* Soldering a device without preheating can cause
excessive thermal shock and stress which can result in
damage to the device.
* Due to shadowing and the inability to set the wave height
to incorporate other surface mount components, the D2PAK
is not recommended for wave soldering.
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8
NTP18N06, NTB18N06
TYPICAL SOLDER HEATING PROFILE
The line on the graph shows the actual temperature that
might be experienced on the surface of a test board at or
near a central solder joint. The two profiles are based on a
high density and a low density board. The Vitronics
SMD310 convection/infrared reflow soldering system was
used to generate this profile. The type of solder used was
62/36/2 Tin Lead Silver with a melting point between
177–189°C. When this type of furnace is used for solder
reflow work, the circuit boards and solder joints tend to
heat first. The components on the board are then heated by
conduction. The circuit board, because it has a large surface
area, absorbs the thermal energy more efficiently, then
distributes this energy to the components. Because of this
effect, the main body of a component may be up to 30
degrees cooler than the adjacent solder joint.
For any given circuit board, there will be a group of
control settings that will give the desired heat pattern. The
operator must set temperatures for several heating zones,
and a figure for belt speed. Taken together, these control
settings make up a heating “profile” for that particular
circuit board. On machines controlled by a computer, the
computer remembers these profiles from one operating
session to the next. Figure 16 shows a typical heating
profile for use when soldering a surface mount device to a
printed circuit board. This profile will vary among
soldering systems but it is a good starting point. Factors that
can affect the profile include the type of soldering system in
use, density and types of components on the board, type of
solder used, and the type of board or substrate material
being used. This profile shows temperature versus time.
STEP 1
PREHEAT
ZONE 1
“RAMP”
200°C
STEP 2
STEP 3
VENT
HEATING
“SOAK” ZONES 2 & 5
“RAMP”
DESIRED CURVE FOR HIGH
MASS ASSEMBLIES
STEP 4
HEATING
ZONES 3 & 6
“SOAK”
160°C
STEP 5
STEP 6
STEP 7
HEATING
VENT
COOLING
ZONES 4 & 7
205° TO 219°C
“SPIKE”
PEAK AT
170°C
SOLDER
JOINT
150°C
150°C
100°C
140°C
100°C
SOLDER IS LIQUID FOR
40 TO 80 SECONDS
(DEPENDING ON
MASS OF ASSEMBLY)
DESIRED CURVE FOR LOW
MASS ASSEMBLIES
5°C
TIME (3 TO 7 MINUTES TOTAL)
TMAX
Figure 16. Typical Solder Heating Profile
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9
NTP18N06, NTB18N06
PACKAGE DIMENSIONS
D2PAK
CASE 418B–03
ISSUE D
C
E
V
–B–
4
A
1
2
3
S
–T–
SEATING
PLANE
K
J
G
D 3 PL
0.13 (0.005)
H
M
T B
M
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
DIM
A
B
C
D
E
G
H
J
K
S
V
INCHES
MIN
MAX
0.340
0.380
0.380
0.405
0.160
0.190
0.020
0.035
0.045
0.055
0.100 BSC
0.080
0.110
0.018
0.025
0.090
0.110
0.575
0.625
0.045
0.055
STYLE 2:
PIN 1.
2.
3.
4.
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10
GATE
DRAIN
SOURCE
DRAIN
MILLIMETERS
MIN
MAX
8.64
9.65
9.65
10.29
4.06
4.83
0.51
0.89
1.14
1.40
2.54 BSC
2.03
2.79
0.46
0.64
2.29
2.79
14.60
15.88
1.14
1.40
NTP18N06, NTB18N06
PACKAGE DIMENSIONS
TO–220
CASE 221A–09
ISSUE AA
–T–
B
SEATING
PLANE
C
F
T
S
4
DIM
A
B
C
D
F
G
H
J
K
L
N
Q
R
S
T
U
V
Z
A
Q
1 2 3
U
H
K
Z
L
R
V
J
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION Z DEFINES A ZONE WHERE ALL
BODY AND LEAD IRREGULARITIES ARE
ALLOWED.
G
D
N
INCHES
MIN
MAX
0.570
0.620
0.380
0.405
0.160
0.190
0.025
0.035
0.142
0.147
0.095
0.105
0.110
0.155
0.018
0.025
0.500
0.562
0.045
0.060
0.190
0.210
0.100
0.120
0.080
0.110
0.045
0.055
0.235
0.255
0.000
0.050
0.045
----0.080
STYLE 5:
PIN 1.
2.
3.
4.
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11
GATE
DRAIN
SOURCE
DRAIN
MILLIMETERS
MIN
MAX
14.48
15.75
9.66
10.28
4.07
4.82
0.64
0.88
3.61
3.73
2.42
2.66
2.80
3.93
0.46
0.64
12.70
14.27
1.15
1.52
4.83
5.33
2.54
3.04
2.04
2.79
1.15
1.39
5.97
6.47
0.00
1.27
1.15
----2.04
NTP18N06, NTB18N06
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes
without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability,
including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or
specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be
validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others.
SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or
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SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable
attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim
alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer.
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