19-3077; Rev 1; 2/04 1.8V, 8-Bit, 250Msps Analog-to-Digital Converter with LVDS Outputs for Wideband Applications Applications ♦ SNR = 48.8dB/48.7dB at fIN = 100MHz/500MHz ♦ SFDR = 68dBc/63.8dBc at fIN = 100MHz/500MHz ♦ Single 1.8V Supply ♦ 477mW Power Dissipation at 250Msps ♦ On-Chip Track-and-Hold and Internal Reference ♦ On-Chip Selectable Divide-by-2 Clock Input ♦ LVDS Digital Outputs with Data Clock Output ♦ Evaluation Kit Available (Order MAX1124EVKIT) Ordering Information PART TEMP RANGE PIN-PACKAGE MAX1121EGK -40°C to +85°C *EP = Exposed paddle. 68 QFN-EP* Pin Configuration 63 62 61 60 59 58 D5P D5N D6N D6P D7N D7P ORN ORP OVCC OGND AVCC AGND 67 66 65 64 AVCC 68 AVCC AGND TOP VIEW AGND For pin-compatible, higher resolution versions of the MAX1121, refer to the MAX1122 (170Msps), the MAX1123 (210Msps), and the MAX1124 (250Msps) data sheets. ♦ 250Msps Conversion Rate T/B The MAX1121 is a monolithic 8-bit, 250Msps analog-todigital converter (ADC) optimized for outstanding dynamic performance at high IF frequencies up to 500MHz. The product operates with conversion rates of up to 250Msps while consuming only 477mW. At 250Msps and an input frequency of 100MHz, the MAX1121 achieves a spurious-free dynamic range (SFDR) of 68dBc. Its excellent signal-to-noise ratio (SNR) of 48.9dB at 10MHz remains flat (within 0.5dB) for input tones up to 500MHz. This makes the MAX1121 ideal for wideband applications such as digital predistortion in cellular base-station transceiver systems. The MAX1121 requires a single 1.8V supply. The analog input is designed for either differential or singleended operation and can be AC- or DC-coupled. The ADC also features a selectable on-chip divide-by-2 clock circuit, which allows the user to apply clock frequencies as high as 500MHz. This helps to reduce the phase noise of the input clock source. A differential LVDS sampling clock is recommended for best performance. The converter’s digital outputs are LVDS compatible, and the data format can be selected to be either two’s complement or offset binary. The MAX1121 is available in a 68-pin QFN with exposed paddle (EP) and is specified over the industrial (-40°C to +85°C) temperature range. Features 57 56 55 54 53 52 AVCC 1 AGND 2 REFIO 3 REFADJ 4 48 D3N Digital Predistortion Receivers AGND 5 47 D2P AVCC 6 46 D2N Communications Test Equipment AGND 7 45 OGND INP 8 INN 9 Wireless and Wired Broadband Communication Digital Oscilloscopes Radar and Satellite Subsystems Antenna Array Processing Instrumentation 51 D4P EP 50 D4N 49 D3P 44 OVCC 43 DCLKP MAX1121 AGND 10 42 DCLKN AVCC 11 41 OVCC AVCC 12 40 D1P AVCC 13 39 D1N AVCC 14 38 D0P AGND 15 37 D0N AGND 16 36 N.C. CLKDIV 17 35 N.C. N.C. N.C. N.C. N.C. N.C. N.C. OVCC OVCC OGND AVCC AGND CLKN CLKP AGND AVCC AGND AGND 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 ________________________________________________________________ Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. 1 MAX1121 General Description MAX1121 1.8V, 8-Bit, 250Msps Analog-to-Digital Converter with LVDS Outputs for Wideband Applications ABSOLUTE MAXIMUM RATINGS AVCC to AGND ......................................................-0.3V to +2.1V OVCC to OGND .....................................................-0.3V to +2.1V AVCC to OVCC .......................................................-0.3V to +2.1V AGND to OGND ....................................................-0.3V to +0.3V Analog Inputs to AGND ...........................-0.3V to (AVCC + 0.3V) Digital Inputs to AGND.............................-0.3V to (AVCC + 0.3V) REF, REFADJ to AGND............................-0.3V to (AVCC + 0.3V) Digital Outputs to OGND .........................-0.3V to (OVCC + 0.3V) ESD on All Pins (Human Body Model).............................±2000V Continuous Power Dissipation (TA = +70°C) 68-Pin QFN (derate 41.7mW/°C above +70°C) .........3333mW Operating Temperature Range ...........................-40°C to +85°C Junction Temperature ......................................................+150°C Storage Temperature Range .............................-60°C to +150°C Lead Temperature (soldering, 10s) .................................+300°C Maximum Current into Any Pin............................................50mA Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (AVCC = OVCC = 1.8V, AGND = OGND = 0, fSAMPLE = 250MHz, differential sine-wave clock input drive, 0.1µF capacitor on REFIO, internal reference, digital output pins differential RL = 100Ω ±1%, CL = 5pF, TA = TMIN to TMAX, unless otherwise noted. ≥25°C guaranteed by production test, <25°C guaranteed by design and characterization. Typical values are at TA = +25°C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS DC ACCURACY Resolution 8 Bits Integral Nonlinearity INL (Note 1) -0.6 ±0.2 +0.6 Differential Nonlinearity DNL No missing codes (Note 1) -0.9 ±0.1 +0.9 LSB Transfer Curve Offset VOS (Note 1) -10 +10 LSB Offset Temperature Drift ±20 LSB µV/°C ANALOG INPUTS (INP, INN) Full-Scale Input Voltage Range VFS (Note 1) 1100 Full-Scale Range Temperature Drift Common-Mode Input Range VCM Input Capacitance CIN Differential Input Resistance RIN Full-Power Analog Bandwidth FPBW 1250 1375 130 ppm/°C 1.38 ±0.18 V 3 3.00 Figure 8 mVP-P 4.4 pF 6.5 600 kΩ MHz REFERENCE (REFIO, REFADJ) Reference Output Voltage VREFIO 1.18 Reference Temperature Drift REFADJ Input High Voltage 1.24 90 VREFADJ Used to disable the internal reference AVCC 0.3 1.30 V ppm/°C V SAMPLING CHARACTERISTICS Maximum Sampling Rate fSAMPLE Minimum Sampling Rate fSAMPLE 2 250 MHz 20 _______________________________________________________________________________________ MHz 1.8V, 8-Bit, 250Msps Analog-to-Digital Converter with LVDS Outputs for Wideband Applications (AVCC = OVCC = 1.8V, AGND = OGND = 0, fSAMPLE = 250MHz, differential sine-wave clock input drive, 0.1µF capacitor on REFIO, internal reference, digital output pins differential RL = 100Ω ±1%, CL = 5pF, TA = TMIN to TMAX, unless otherwise noted. ≥25°C guaranteed by production test, <25°C guaranteed by design and characterization. Typical values are at TA = +25°C.) PARAMETER SYMBOL Clock Duty Cycle CONDITIONS MIN Set by clock management circuit TYP MAX UNITS 40 to 60 % Aperture Delay tAD 350 ps Aperture Jitter tAJ 0.2 psRMS 500 mVP-P 1.25 ±0.25 V CLOCK INPUTS (CLKP, CLKN) Differential Clock Input Amplitude (Note 2) 200 Clock Input Common-Mode Voltage Range Clock Differential Input Resistance RCLK 11 ±25% kΩ Clock Differential Input Capacitance CCLK 5 pF DYNAMIC CHARACTERISTICS (at -0.5dBFS) Signal-to-Noise Ratio SNR fIN = 10MHz, TA ≥ +25°C 47.2 fIN = 100MHz, TA ≥ +25°C 46.2 fIN = 180MHz SINAD SFDR Worst Harmonics (HD2 or HD3) Two-Tone Intermodulation Distortion dB 48.7 fIN = 10MHz, TA ≥ +25°C 47.1 48.8 fIN = 100MHz, TA ≥ +25°C 46.1 48.7 fIN = 180MHz dB 48.7 fIN = 500MHz Spurious-Free Dynamic Range 48.8 48.8 fIN = 500MHz Signal-to-Noise and Distortion 48.9 48.6 fIN = 10MHz, TA ≥ +25°C 60 fIN = 100MHz, TA ≥ +25°C 59 69 68 fIN = 180MHz 69.1 fIN = 500MHz 63.8 fIN = 10MHz -74.6 fIN = 100MHz -68.4 fIN = 180MHz -69.1 fIN = 500MHz -63.8 IMD100 fIN1 = 99MHz at -7dBFS, fIN2 = 101MHz at -7dBFS -70 IMD500 fIN1 = 498.5MHz at -7dBFS, fIN2 = 502.5MHz at -7dBFS -56 dBc dBc dBc LVDS DIGITAL OUTPUTS (D0P/N–D7P/N, DCLKP/N) Differential Output Voltage |VOD| 250 400 mV _______________________________________________________________________________________ 3 MAX1121 ELECTRICAL CHARACTERISTICS (continued) MAX1121 1.8V, 8-Bit, 250Msps Analog-to-Digital Converter with LVDS Outputs for Wideband Applications ELECTRICAL CHARACTERISTICS (continued) (AVCC = OVCC = 1.8V, AGND = OGND = 0, fSAMPLE = 250MHz, differential sine-wave clock input drive, 0.1µF capacitor on REFIO, internal reference, digital output pins differential RL = 100Ω ±1%, CL = 5pF, TA = TMIN to TMAX, unless otherwise noted. ≥25°C guaranteed by production test, <25°C guaranteed by design and characterization. Typical values are at TA = +25°C.) PARAMETER Output Offset Voltage SYMBOL CONDITIONS OVOS MIN TYP 1.125 MAX UNITS 1.310 V 0.2 x AVCC V LVCMOS DIGITAL INPUTS (CLKDIV, T/B) Digital Input Voltage Low VIL Digital Input Voltage High VIH 0.8 x AVCC V TIMING CHARACTERISTICS CLK to Data Propagation Delay tPDL Figure 4 1.5 ns CLK to DCLK Propagation Delay tCPDL Figure 4 2.85 ns Data Valid to DCLK Rising Edge tCPDL tPDL Figure 4 (Note 2) 0.92 1.35 1.86 ns LVDS Output Rise-Time tRISE 20% to 80%, CL = 5pF 460 ps LVDS Output Fall-Time tFALL 20% to 80%, CL = 5pF 460 ps 8 Clock cycles Output Data Pipeline Delay tLATENCY POWER REQUIREMENTS Analog Supply Voltage Range AVCC 1.70 1.80 1.90 1.70 V Digital Supply Voltage Range OVCC 1.80 1.90 V Analog Supply Current IAVCC fIN = 100MHz 220 290 mA Digital Supply Current IOVCC fIN = 100MHz 45 75 mA Analog Power Dissipation PDISS fIN = 100MHz 477 657 Offset 1.6 mV/V Gain 1.9 %FS/V Power-Supply Rejection Ratio (Note 3) PSRR mW Note 1: Static linearity and offset parameters are computed from a best-fit straight line through the code transition points. The fullscale range is defined as 1023 x slope of the line. Note 2: Parameter guaranteed by design and characterization; TA = TMIN to TMAX. Note 3: PSRR is measured with both analog and digital supplies connected to the same potential. 4 _______________________________________________________________________________________ 1.8V, 8-Bit, 250Msps Analog-to-Digital Converter with LVDS Outputs for Wideband Applications FFT PLOT (8192-POINT DATA RECORD, COHERENT SAMPLING) -40 -50 -60 HD2 HD3 -30 -40 -50 HD2 HD3 -60 -30 -40 -50 HD2 -70 -80 -80 -80 -90 -90 40 60 80 100 120 0 140 FFT PLOT (8192-POINT DATA RECORD, COHERENT SAMPLING) -40 HD3 -50 100 120 140 0 40 60 80 100 120 140 SFDR vs. ANALOG INPUT FREQUENCY (fSAMPLE = 250.0057MHz, AIN = -0.5dBFS) 80 MAX1121 toc05 49 20 ANALOG INPUT FREQUENCY (MHz) 48 74 SFDR (dBc) -30 80 50 SNR (dB) FUNDAMENTAL -20 fSAMLE = 250.0057MHz fIN = 500.516MHz AIN = -0.5235MHz SNR = 48.8dB SFDR = 63.8dBc HD2 = -70.8dBc HD3 = -63.8dBc 60 SNR vs. ANALOG INPUT FREQUENCY (fSAMPLE = 250.0057MHz, AIN = -0.5dBFS) MAX1121 toc04 0 40 ANALOG INPUT FREQUENCY (MHz) ANALOG INPUT FREQUENCY (MHz) -10 20 47 MAX1121 toc06 20 HD3 -60 -70 0 fSAMPLE = 250.0057MHz fIN = 183.5064MHz AIN = -0.5245MHz SNR = 48.8dB SFDR = 69.1dBc HD2 = -77.2dBc HD3 = -69.1dBc -20 -70 -90 AMPLITUDE (dB) MAX1121 toc02 -20 0 -10 AMPLITUDE (dB) AMPLITUDE (dB) -30 fSAMPLE = 250.0057MHz fIN = 60.0294MHz AIN = -0.4885MHz SNR = 49dB SFDR = 71.1dBc HD2 = -79.5dBc HD3 = -71.9dBc -10 AMPLITUDE (dB) fSAMPLE = 250.0057MHz fIN = 11.5054MHz AIN = -0.4885MHz SNR = 48.9dB SFDR = 71.5dBc HD2 = -79.2dBc HD3 = -74.6dBc -20 0 MAX1121 toc01 0 -10 FFT PLOT (8192-POINT DATA RECORD, COHERENT SAMPLING) MAX1121 toc03 FFT PLOT (8192-POINT DATA RECORD, COHERENT SAMPLING) 68 62 -60 HD2 -70 56 46 -80 140 0 HD3 -60 200 300 400 0 500 100 200 300 400 500 fIN (MHz) fIN (MHz) SNR vs. ANALOG INPUT AMPLITUDE (fSAMPLE = 250.0057MHz, fIN = 60.0294MHz) SFDR vs. ANALOG INPUT AMPLITUDE (fSAMPLE = 250.0057MHz, fIN = 60.0294MHz) 50 MAX1121 toc07 -50 100 75 MAX1121 toc08 20 40 60 80 100 120 ANALOG INPUT FREQUENCY (MHz) HD2/HD3 vs. ANALOG INPUT FREQUENCY (fSAMPLE = 250.0057MHz, AIN = -0.5dBFS) 45 70 65 40 60 SFDR (dBc) -70 SNR (dB) HD2/HD3 (dBc) 50 45 0 MAX1121 toc09 -90 35 -80 HD2 30 55 50 45 40 -90 25 35 20 -100 0 100 200 300 fIN (MHz) 400 500 30 -30 -25 -20 -15 -10 -5 ANALOG INPUT AMPLITUDE (dBFS) 0 -30 -25 -20 -15 -10 -5 0 ANALOG INPUT AMPLITUDE (dBFS) _______________________________________________________________________________________ 5 MAX1121 Typical Operating Characteristics (AVCC = OVCC = 1.8V, AGND = OGND = 0, fSAMPLE = 250.0057MHz, -0.5dBFS; see TOCs for detailed information on test conditions, differential input drive, differential sine-wave clock input drive, 0.1µF capacitor on REFIO, internal reference, digital output pins differential RL = 100Ω, TA = +25°C.) Typical Operating Characteristics (continued) (AVCC = OVCC = 1.8V, AGND = OGND = 0, fSAMPLE = 250.0057MHz, -0.5dBFS; see TOCs for detailed information on test conditions, differential input drive, differential sine-wave clock input drive, 0.1µF capacitor on REFIO, internal reference, digital output pins differential RL = 100Ω, TA = +25°C.) SNR vs. fSAMPLE (fIN = 60.0294MHz, AIN = -0.5dBFS) 48.0 47.5 -20 -15 -10 -5 60 100 140 180 220 260 20 60 100 140 180 220 ANALOG INPUT AMPLITUDE (dBFS) fSAMPLE (MHz) fSAMPLE (MHz) HD2/HD3 vs. fSAMPLE (fIN = 60.03294MHz, AIN = -0.5dBFS) TWO-TONE IMD PLOT (8192-POINT DATA RECORD, COHERENT SAMPLING) INTEGRAL NONLINEARITY vs. DIGITAL OUTPUT CODE -20 AMPLITUDE (dB) HD2 -84 -30 0.4 0.3 0.2 fIN2 -40 -50 -60 2fIN1 - fIN2 2fIN2 fIN1 -0.4 -90 20 60 100 140 180 220 -0.5 0 260 0 -0.1 -0.3 -80 -100 0.1 -0.2 -70 -92 260 MAX1121 toc15 -10 HD3 -76 fSAMPLE = 250.0057MHz fIN1 = 99.0318MHz fIN2 = 101.046MHz AIN1 = AIN2 = -7dBFS fIN1 IMD = -70dBc INL (LSB) -68 0.5 MAX1121 toc14 0 MAX1121 toc13 -60 20 40 60 80 100 120 140 0 32 64 96 128 160 192 224 256 fSAMPLE (MHz) ANALOG INPUT FREQUENCY (MHz) DIGITAL OUTPUT CODE DIFFERENTIAL NONLINEARITY vs. DIGITAL OUTPUT CODE GAIN BANDWIDTH PLOT (fSAMPLE = 250.0057MHz, AIN = -0.5dBFS) SNR vs. TEMPERATURE (fIN = 65.0108MHz, fSAMPLE = 249.856MHz, AIN = -0.5dBFS) 0.3 50.0 0 49.5 49.0 -2 GAIN (dB) 0.1 0 -0.1 48.5 -4 SNR (dB) 0.2 MAX1121 toc18 0.4 MAX1121 toc17 2 MAX1121 toc16 0.5 -6 48.0 47.5 -0.2 -8 47.0 -0.3 -10 -0.4 -0.5 46.5 46.0 -12 0 32 64 96 128 160 192 224 256 DIGITAL OUTPUT CODE 6 60 40 20 0 70 50 46.5 -25 MAX1121 toc12 80 47.0 -30 HD2/HD3 (dBc) 48.5 SFDR (dBc) HD2 90 MAX1121 toc11 HD3 SFDR vs. fSAMPLE (fIN = 60.0294MHz, AIN = -0.5dBFS) 49.0 MAX1121 toc10 -30 -35 -40 -45 -50 -55 -60 -65 -70 -75 -80 -85 -90 SNR (dB) HD2/HD3 (dBc) HD2/HD3 vs. ANALOG INPUT AMPLITUDE (fSAMPLE = 250.0057MHz, fIN = 60.0294MHz) DNL (LSB) MAX1121 1.8V, 8-Bit, 250Msps Analog-to-Digital Converter with LVDS Outputs for Wideband Applications 10 100 ANALOG INPUT FREQUENCY (MHz) 1000 -40 -15 10 35 TEMPERATURE (°C) _______________________________________________________________________________________ 60 85 1.8V, 8-Bit, 250Msps Analog-to-Digital Converter with LVDS Outputs for Wideband Applications 49.5 70 480 470 460 48.0 47.5 65 PDISS (mW) 48.5 SFDR (dBc) 60 55 420 50 400 46.5 410 46.0 -40 -15 10 35 60 -40 35 60 85 60 20 100 140 180 220 260 SNR vs. SUPPLY VOLTAGE (fIN = 60.0294MHz, AIN = -0.5dBFS) INTERNAL REFERENCE vs. SUPPLY VOLTAGE (fSAMPLE = 250.0057MHz) 1.2350 MAX1121 toc23 MAX1121 toc22 50 AVCC = OVCC 49 MAX1121 toc24 FS VOLTAGE vs. FS ADJUST RESISTOR 1.30 MEASURED AT THE REFIO PIN REFADJ = AVCC = OVCC 1.2340 48 1.26 1.24 47 VREFIO (V) SNR (dB) RESISTOR VALUE APPLIED BETWEEN REFADJ AND AGND 1.22 46 1.2330 1.2320 45 RESISTOR VALUE APPLIED BETWEEN REFADJ AND REFIO 1.2310 44 1.18 43 1.16 1.2300 1.5 0 100 200 300 400 500 600 700 800 900 1000 1.6 1.7 1.8 1.9 2.0 2.1 1.5 1.6 1.7 1.8 1.9 2.0 2.1 FS ADJUST RESISTOR (Ω) SUPPLY VOLTAGE (V) SUPPLY VOLTAGE (V) NOISE HISTOGRAM (DC INPUT, 256k-POINT DATA RECORD) PROPAGATION DELAY TIMES vs. TEMPERATURE SINAD vs. CLOCK DUTY CYCLE (fIN = 1.8148MHz, fSAMPLE = 249.856MHz, AIN = -0.5dBFS) 5 131072 1.2E+05 8.0E+04 4.0E+04 126 0 127 DIGITAL OUTPUT NOISE 128 49.5 49.0 4 tCPDL 3 2 48.5 48.0 47.5 47.0 1 0 50.0 SINAD (dB) PROPAGATION DELAY (ns) 1.6E+05 6 MAX1121 toc26 fSAMPLE = 250MHz MAX1121 toc25 2.0E+05 CODE COUNTS 10 fSAMPLE (MHz) 1.32 0.0E+00 -15 TEMPERATURE (°C) FIGURE 6 VFS (V) 85 TEMPERATURE (°C) 1.34 1.20 440 430 47.0 1.28 450 MAX1121 toc27 SINAD (dB) 49.0 490 MAX1121 toc20 75 MAX1121 toc19 50.0 POWER DISSIPATION vs. fSAMPLE (fIN = 60.0294MHz, AIN = -0.5dBFS) SFDR vs. TEMPERATURE (fIN = 65.0108MHz, fSAMPLE = 249.856MHz, AIN = -0.5dBFS) MAX1121 toc21 SINAD vs. TEMPERATURE (fIN = 65.0108MHz, fSAMPLE = 249.856MHz, AIN = -0.5dBFS) 46.5 tPDL 0 46.0 -40 -15 10 35 TEMPERATURE (°C) 60 85 10 20 30 40 50 60 70 80 90 CLOCK DUTY CYCLE (%) _______________________________________________________________________________________ 7 MAX1121 Typical Operating Characteristics (continued) (AVCC = OVCC = 1.8V, AGND = OGND = 0, fSAMPLE = 250.0057MHz, -0.5dBFS; see TOCs for detailed information on test conditions, differential input drive, differential sine-wave clock input drive, 0.1µF capacitor on REFIO, internal reference, digital output pins differential RL = 100Ω, TA = +25°C.) 1.8V, 8-Bit, 250Msps Analog-to-Digital Converter with LVDS Outputs for Wideband Applications MAX1121 Pin Description 8 PIN NAME 1, 6, 11–14, 20, 25, 62, 63, 65 FUNCTION AVCC Analog Supply Voltage. Bypass each pin with a 0.1µF capacitor for best decoupling results. 2, 5, 7, 10, 15, 16, 18, 19, 21, 24, 64, 66, 67, EP AGND Analog Converter Ground. Connect the converter’s exposed paddle (EP) to AGND. 3 REFIO Reference Input/Output. With REFADJ pulled high through a 1kΩ resistor, this I/O port allows an external reference source to be connected to the MAX1121. With REFADJ pulled low through the same 1kΩ resistor, the internal 1.23V bandgap reference is active. 4 REFADJ Reference-Adjust Input. REFADJ allows for full-scale range adjustments by placing a resistor or trim potentiometer between REFADJ and AGND (decreases FS range) or REFADJ and REFIO (increases FS range). If REFADJ is connected to AVCC through a 1kΩ resistor, the internal reference can be overdriven with an external source connected to REFIO. If REFADJ is connected to AGND through a 1kΩ resistor, the internal reference is used to determine the full-scale range of the data converter. 8 INP Positive Analog Input Terminal 9 INN Negative Analog Input Terminal Clock Divider Input. This LVCMOS-compatible input controls which speed the converter’s digital outputs are updated. CLKDIV has an internal pulldown resistor. CLKDIV = 0: ADC updates digital outputs at one-half the input clock rate. CLKDIV = 1: ADC updates digital outputs at the input clock rate. 17 CLKDIV 22 CLKP True Clock Input. This input requires an LVDS-compatible input level to maintain the converter’s excellent performance. 23 CLKN Complementary Clock Input. This input requires an LVDS-compatible input level to maintain the converter’s excellent performance. 26, 45, 61 OGND Digital Converter Ground. Ground connection for digital circuitry and output drivers. 27, 28, 41, 44, 60 OVCC Digital Supply Voltage. Bypass with a 0.1µF capacitor for best decoupling results. 29–36 N.C. No Connection. Do not connect to these pins. 37 D0N Complementary Output Bit 0 (LSB) 38 D0P True Output Bit 0 (LSB) 39 D1N Complementary Output Bit 1 40 D1P True Output Bit 1 42 DCLKN Complementary Clock Output. This output provides an LVDS-compatible output level and can be used to synchronize external devices to the converter clock. There is a 2.1ns delay between CLKN and DCLKN. 43 DCLKP True Clock Output. This output provides an LVDS-compatible output level and can be used to synchronize external devices to the converter clock. There is a 2.1ns delay between CLKP and DCLKP. 46 D2N Complementary Output Bit 2 47 D2P True Output Bit 2 48 D3N Complementary Output Bit 3 49 D3P True Output Bit 3 _______________________________________________________________________________________ 1.8V, 8-Bit, 250Msps Analog-to-Digital Converter with LVDS Outputs for Wideband Applications PIN NAME 50 D4N Complementary Output Bit 4 51 D4P True Output Bit 4 52 D5N Complementary Output Bit 5 53 D5P True Output Bit 5 54 D6N Complementary Output Bit 6 55 D6P True Output Bit 6 56 D7N Complementary Output Bit 7 57 D7P True Output Bit 7 58 ORN Complementary Output for Out-of-Range Control Bit. If an out-of-range condition is detected, bit ORN flags this condition by transitioning low. 59 ORP True Output for Out-of-Range Control Bit. If an out-of-range condition is detected, bit ORP flags this condition by transitioning high. T/B Two’s Complement or Binary Output Format Selection. This LVCMOS-compatible input controls the digital output format of the MAX1121. T/B has an internal pulldown resistor. T/B = 0: Two’s complement output format T/B = 1: Binary output format 68 FUNCTION CLKDIV CLKP CLOCKDIVIDER CONTROL CLKN INPUT BUFFER INP DCLKP DCLKN CLOCK MANAGEMENT T/H INN 8-BIT PIPELINE QUANTIZER CORE LVDS DATA PORT D0P/N–D7P/N 8 2.2kΩ 2.2kΩ ORP REFERENCE ORN COMMON-MODE BUFFER MAX1121 REFIO REFADJ Figure 1. MAX1121 Block Diagram _______________________________________________________________________________________ 9 MAX1121 Pin Description (continued) MAX1121 1.8V, 8-Bit, 250Msps Analog-to-Digital Converter with LVDS Outputs for Wideband Applications Detailed Description— Theory of Operation The MAX1121 uses a fully differential, pipelined architecture that allows for high-speed conversion, optimized accuracy and linearity, while minimizing power consumption and die size. Both positive (INP) and negative/complementary analog input terminals (INN) are centered around a commonmode voltage of 1.4V, and accept a differential analog input voltage swing of ±0.3125V each, resulting in a typical differential full-scale signal swing of 1.25VP-P. INP and INN are buffered prior to entering each trackand-hold (T/H) stage and are sampled when the differential sampling clock signal transitions high. A 2-bit ADC following the first T/H stage then digitizes the signal, and controls a 2-bit digital-to-analog converter (DAC). Digitized and reference signals are then subtracted, resulting in a fractional residue signal that is amplified before it is passed on to the next stage through another T/H amplifier. This process is repeated until the applied input signal has successfully passed through all stages of the 8-bit quantizer. Finally, the digital outputs of all stages are combined and corrected for in the digital correction logic to generate the final output code. The result is a 8-bit parallel digital output word in user-selectable two’s complement or binary output formats with LVDScompatible output levels. See Figure 1 for a more detailed view of the MAX1121 architecture. biased at a common-mode voltage of 1.4V and allow a differential input voltage swing of 1.25VP-P. Both inputs are self-biased through 2.2kΩ resistors, resulting in a typical differential input resistance of 4.4kΩ. It is recommended to drive the analog inputs of the MAX1121 in AC-coupled configuration to achieve best dynamic performance. See the AC-Coupled Analog Inputs section for a detailed discussion of this configuration. On-Chip Reference Circuit The MAX1121 features an internal 1.23V bandgap reference circuit (Figure 3), which, in combination with an internal reference-scaling amplifier, determines the fullscale range of the MAX1121. Bypass REFIO with a 0.1µF capacitor to AGND. To compensate for gain errors or increase the ADC’s full-scale range, the voltage of this bandgap reference can be indirectly adjusted by adding an external resistor (e.g., 100kΩ trim potentiometer) between REFADJ and AGND or REFADJ and REFIO. See the Applications Information section for a detailed description of this process. Clock Inputs (CLKP, CLKN) Designed for a differential LVDS clock input drive, it is recommended to drive the clock inputs of the MAX1121 with an LVDS-compatible clock to achieve the best dynamic performance. The clock signal source must be a high-quality, low phase noise to avoid any degradation in the noise performance of the ADC. The clock inputs (CLKP, CLKN) are internally biased to 1.2V, accept a differential signal swing of 0.2VP-P to 1.0VP-P Analog Inputs (INP, INN) INP and INN are the fully differential inputs of the MAX1121. Differential inputs usually feature good rejection of even-order harmonics, which allows for enhanced AC performance as the signals are progressing through the analog stages. The MAX1121 analog inputs are self- ADC FULL-SCALE = REFT - REFB REFT G REFB REFERENCE BUFFER REFERENCE SCALING AMPLIFIER REFIO AVCC 0.1µF 1V INP 2.2kΩ TO COMMON-MODE INPUT CONTROL LINE TO DISABLE REFERENCE BUFFER 2.2kΩ 1kΩ TO COMMON-MODE INPUT AGND Figure 2. Simplified Analog Input Architecture 10 REFADJ INN AVCC AVCC / 2 Figure 3. Simplified Reference Architecture ______________________________________________________________________________________ 1.8V, 8-Bit, 250Msps Analog-to-Digital Converter SAMPLING EVENT SAMPLING EVENT SAMPLING EVENT SAMPLING EVENT MAX1121 INN INP tCL tCH tAD CLKN N N+1 N+8 N+9 CLKP tCPDL tLATENCY DCLKP N-8 N-7 N N+1 DCLKN tCPDL - tPDL tPDL D0P/N–D7P/N ORP/N N-8 N-7 N-1 N N+1 tCPDL - tPDL ~ 0.4 x tSAMPLE with tSAMPLE = 1 / fSAMPLE NOTE: THE ADC SAMPLES ON THE RISING EDGE OF CLKP. THE RISING EDGE OF DCLKP CAN BE USED TO EXTERNALLY LATCH THE OUTPUT DATA. Figure 4. System and Output Timing Diagram and are usually driven in AC-coupled configuration. See the Differential, AC-Coupled Clock Input in the Applications Information section for more circuit details on how to drive CLKP and CLKN appropriately. Although not recommended, the clock inputs also accept a single-ended input signal. The MAX1121 also features an internal clock management circuit (duty-cycle equalizer) that ensures that the clock signal applied to inputs CLKP and CLKN is processed to provide a 50% duty cycle clock signal, which desensitizes the performance of the converter to variations in the duty cycle of the input clock source. Note that the clock duty-cycle equalizer cannot be turned off externally and requires a minimum clock frequency of >20MHz to work appropriately and according to data sheet specifications. OVCC VOP 2.2kΩ VON 2.2kΩ Clock Outputs (DCLKP, DCLKN) The MAX1121 features a differential clock output, which can be used to latch the digital output data with an external latch or receiver. Additionally, the clock output can be used to synchronize external devices (e.g., FPGAs) to the ADC. DCLKP and DCLKN are differential outputs with LVDS-compatible voltage levels. There is a 2.1ns delay time between the rising (falling) edge of CLKP (CLKN) and the rising edge of DCLKP (DCLKN). See Figure 4 for timing details. OGND Figure 5. Simplified LVDS Output Architecture ______________________________________________________________________________________ 11 MAX1121 1.8V, 8-Bit, 250Msps Analog-to-Digital Converter with LVDS Outputs for Wideband Applications Divide-by-2 Clock Control (CLKDIV) The MAX1121 offers a clock control line (CLKDIV), which supports the reduction of clock jitter in a system. Connect CLKDIV to OGND to enable the ADC’s internal divide-by-2 clock divider. Data is now updated at onehalf the ADC’s input clock rate. CLKDIV has an internal pulldown resistor and can be left open for applications that only operate with update rates one-half of the converter’s sampling rate. Connecting CLKDIV to OVCC allows data to be updated at the speed of the ADC input clock. System Timing Requirements Figure 4 depicts the relationship between the clock input and output, analog input, sampling event, and data output. The MAX1121 samples on the rising (falling) edge of CLKP (CLKN). Output data is valid on the next rising (falling) edge of the DCLKP (DCLKN) clock, but has an internal latency of nine clock cycles. Digital Outputs (D0P/N–D7P/N, DCLKP/N, ORP/N) and Control Input T/B The digital outputs D0P/N–D7P/N, DCLKP/N, and ORP/N are LVDS compatible, and data on D0P/N–D7P/N is presented in either binary or two’s complement format (Table 1). The T/B control line is an LVCMOS-compatible input, which allows the user to select the desired output format. Pulling T/B low outputs data in two’s complement and pulling it high presents data in offset binary format on the 10-bit parallel bus. T/B has an internal pulldown resistor and may be left unconnected in applications using only two’s complement output format. All LVDS outputs provide a typical voltage swing of 0.4V around a common-mode voltage of approximately 1.2V, and must be terminated at the far end of each transmission line pair (true and complementary) with 100Ω. The LVDS outputs are powered from a separate power supply, which can be operated between 1.7V and 1.9V. The MAX1121 offers an additional differential output pair (ORP, ORN) to flag out-of-range conditions, where out of range is above positive or below negative full scale. An out-of-range condition is identified with ORP (ORN) transitioning high (low). Note: Although differential LVDS reduces single-ended transients to the supply and ground planes, capacitive loading on the digital outputs should still be kept as low as possible. Using LVDS buffers on the digital outputs of the ADC when driving off-board may improve overall performance and reduce system timing constraints. Table 1. MAX1121 Digital Output Coding 12 INP ANALOG VOLTAGE LEVEL INN ANALOG VOLTAGE LEVEL OUT-OF-RANGE ORP (ORN) BINARY DIGITAL OUTPUT CODE (D7–D0) TWO’S COMPLEMENT DIGITAL OUTPUT CODE (D7–D0) > VCM + 0.3125V < VCM - 0.3125V 1 (0) 1111 1111 (exceeds positive full scale, OR set) 0111 1111 (exceeds positive full scale, OR set) VCM + 0.3125V VCM - 0.3125V 0 (1) 1111 1111 (represents positive full scale) 0111 1111 (represents positive full scale) VCM VCM 0 (1) 1000 0000 or 0111 1111 (represents midscale) 0000 0000 or 1111 1111 (represents midscale) VCM - 0.3125V VCM + 0.3125V 0 (1) 0000 0000 (represents negative full scale) 1000 0000 (represents negative full scale) < VCM - 0.3125V > VCM + 0.3125V 1 (0) 0000 0000 (exceeds negative full scale, OR set) 1000 0000 (exceeds negative full scale, OR set) ______________________________________________________________________________________ 1.8V, 8-Bit, 250Msps Analog-to-Digital Converter with LVDS Outputs for Wideband Applications Full-Scale Range Adjustments Using the Internal Bandgap Reference MAX1121 Applications Information ADC FULL-SCALE = REFT - REFB The MAX1121 supports a full-scale adjustment range of 10% (±5%). To decrease the full-scale range, an external resistor value ranging from 13kΩ to 1MΩ may be added between REFADJ and AGND. A similar approach can be taken to increase the ADCs full-scale range. Adding a variable resistor, potentiometer, or predetermined resistor value between REFADJ and REFIO increases the full-scale range of the data converter. Figure 6 shows the two possible configurations and their impact on the overall full-scale range adjustment of the MAX1121. Do not use resistor values of less than 13kΩ to avoid instability of the internal gain regulation loop for the bandgap reference. REFT REFERENCESCALING AMPLIFIER G REFB REFERENCE BUFFER REFIO 1V REFADJ 0.1µF 13kΩ TO 1MΩ CONTROL LINE TO DISABLE REFERENCE BUFFER 13kΩ TO 1MΩ Differential, AC-Coupled, PECL-Compatible Clock Input The preferred method of clocking the MAX1121 is differentially with LVDS- or PECL-compatible input levels. To accomplish this, a 50Ω reverse-terminated clock signal source with low phase noise is AC-coupled into a fast differential receiver such as the MC100LVEL16 (Figure 7). The receiver produces the necessary PECL output levels to drive the clock inputs of the data converter. MAX1121 AVCC AVCC / 2 Figure 6. Circuit Suggestions to Adjust the ADC’s Full-Scale Range VCLK 0.1µF 8 SINGLE-ENDED INPUT TERMINAL 0.1µF 0.1µF 7 2 150Ω MC100LVEL16 6 3 510Ω AVCC OVCC 0.1µF 50Ω 150Ω 510Ω 4 0.01µF INP CLKN CLKP D0P/N–D7P/N 5 MAX1121 8 INN VGND AGND OGND Figure 7. Differential, AC-Coupled, PECL-Compatible Clock Input Configuration ______________________________________________________________________________________ 13 MAX1121 1.8V, 8-Bit, 250Msps Analog-to-Digital Converter with LVDS Outputs for Wideband Applications AVCC SINGLE-ENDED INPUT TERMINAL 0.1µF 15Ω ADT1–1WT OVCC INP D0P/N–D7P/N 25Ω 25Ω 15Ω MAX1121 INN 8 0.1µF AGND OGND Figure 8. Transformer-Coupled Analog Input Configuration with Secondary-Side Termination Differential, AC-Coupled Analog Input An RF transformer provides an excellent solution to convert a single-ended source signal to a fully differential signal, required by the MAX1121 for optimum dynamic performance. In general, the MAX1121 provides the best SFDR and THD with fully differential input signals and it is not recommended to drive the ADC inputs in single-ended configuration. In differential input mode, even-order harmonics are usually lower since INP and INN are balanced, and each of the ADC inputs only requires half the signal swing compared to a single-ended configuration. Figure 8 depicts a secondary-side termination of the 1:1 transformer into two separate 25Ω loads. Terminating the transformer in this fashion reduces the potential effects of transformer parasitics. The source impedance combined with the shunt capacitance provided by a PC board and the ADC’s parasitic capacitance reduce the combined bandwidth to approximately 550MHz. Single-Ended, AC-Coupled Analog Input Although not recommended, the MAX1121 can be used in single-ended mode (Figure 9). Analog signals can be AC-coupled to the positive input INP through a 0.1µF capacitor and terminated with a 50Ω resistor to AGND. The negative input should be 25Ω reverse-terminated and AC grounded with a 0.1µF capacitor. Grounding, Bypassing, and Board Layout Considerations The MAX1121 requires board layout design techniques suitable for high-speed data converters. This ADC provides separate analog and digital power supplies. The analog and digital supply voltage pins accept input voltage ranges of 1.7V to 1.9V. Although both supply 14 AVCC SINGLE-ENDED INPUT TERMINAL OVCC 0.1µF INP D0P/N–D7P/N 50Ω MAX1121 0.1µF INN 8 25Ω AGND OGND Figure 9. Single-Ended AC-Coupled Analog Input Configuration types can be combined and supplied from one source, it is recommended to use separate sources to cut down on performance degradation caused by digital switching currents, which can couple into the analog supply network. Isolate analog and digital supplies (AVCC and OVCC) where they enter the PC board with separate networks of ferrite beads and capacitors to their corresponding grounds (AGND, OGND). To achieve optimum performance, provide each supply with a separate network of a 47µF tantalum capacitor in parallel with 10µF and 1µF ceramic capacitors. Additionally, the ADC requires each supply pin to be bypassed with separate 0.1µF ceramic capacitors (Figure 10). Locate these capacitors directly at the ADC supply pins or as close as possible to the MAX1121. Choose surface-mount capacitors, which are preferably located on the same side as the converter, to save space and minimize the inductance. ______________________________________________________________________________________ 1.8V, 8-Bit, 250Msps Analog-to-Digital Converter with LVDS Outputs for Wideband Applications OVCC AVCC 0.1µF AGND MAX1121 BYPASSING—BOARD LEVEL AVCC BYPASSING—ADC LEVEL 0.1µF 1µF 10µF 47µF 10µF 47µF ANALOG POWERSUPPLY SOURCE OGND D0P/N–D7P/N OVCC MAX1121 8 1µF AGND DIGITAL/OUTPUTDRIVER POWERSUPPLY SOURCE OGND NOTE: EACH POWER-SUPPLY PIN (ANALOG AND DIGITAL) SHOULD BE DECOUPLED WITH AN INDIVIDUAL 0.1µF CAPACITOR CLOSE TO THE ADC. Figure 10. Grounding, Bypassing, and Decoupling Recommendations for the MAX1121 Multilayer boards with separated ground and power planes produce the highest level of signal integrity. Consider the use of a split ground plane arranged to match the physical location of analog and digital ground on the ADC’s package. The two ground planes should be joined at a single point so the noisy digital ground currents do not interfere with the analog ground plane. A major concern with this approach are the dynamic currents that may need to travel long distances before they are recombined at a common source ground, resulting in large and undesirable ground loops. Ground loops can add to digital noise by coupling back to the analog front end of the converter, resulting in increased spur activity and a decreased noise performance. Alternatively, all ground pins could share the same ground plane, if the ground plane is sufficiently isolated from any noisy, digital systems ground. To minimize the effects of digital noise coupling, ground return vias can be positioned throughout the layout to divert digital switching currents away from the sensitive analog sections of the ADC. This does not require additional ground splitting, but can be accomplished by placing substantial ground connections between the analog front end and the digital outputs. The MAX1121 is packaged in a 68-pin QFN-EP package (package code: G6800-4), providing greater design flexibility, increased thermal efficiency, and optimized AC performance of the ADC. The EP must be soldered down to AGND. In this package, the data converter die is attached to an EP lead frame with the back of this frame exposed at the package bottom surface, facing the PC board side of the package. This allows a solid attachment of the package to the PC board with standard infrared (IR) flow soldering techniques. Note that thermal efficiency is not the key factor, since the MAX1121 features low-power operation. The exposed pad is the key element to ensure a solid ground connection between the DAC and the PC board’s analog ground layer. Considerable care must be taken, when routing the digital output traces for a high-speed, high-resolution data converter. It is essential to keep trace lengths at a minimum and place minimal capacitive loading (less than 5pF) on any digital trace to prevent coupling to sensitive analog sections of the ADC. It is recommended to run the LVDS output traces as differential lines with 100Ω characteristic impedance from the ADC to the LVDS load device. ______________________________________________________________________________________ 15 MAX1121 1.8V, 8-Bit, 250Msps Analog-to-Digital Converter with LVDS Outputs for Wideband Applications Static Parameter Definitions CLKP Integral Nonlinearity (INL) Integral nonlinearity is the deviation of the values on an actual transfer function from a straight line. This straight line can be either a best straight-line fit or a line drawn between the end points of the transfer function, once offset and gain errors have been nullified. However, the static linearity parameters for the MAX1121 are measured using the histogram method with an input frequency of 10MHz. CLKN ANALOG INPUT tAD tAJ SAMPLED DATA (T/H) Differential Nonlinearly (DNL) Differential nonlinearity is the difference between an actual step width and the ideal value of 1 LSB. A DNL error specification of less than 1 LSB guarantees no missing codes and a monotonic transfer function. The MAX1121’s DNL specification is measured with the histogram method based on a 10MHz input tone. Dynamic Parameter Definitions Aperture Jitter Figure 11 depicts the aperture jitter (tAJ), which is the sample-to-sample variation in the aperture delay. Aperture Delay Aperture delay (tAD) is the time defined between the falling edge of the sampling clock and the instant when an actual sample is taken (Figure 11). Signal-to-Noise Ratio (SNR) For a waveform perfectly reconstructed from digital samples, the theoretical maximum SNR is the ratio of the full-scale analog input (RMS value) to the RMS quantization error (residual error). The ideal, theoretical minimum analog-to-digital noise is caused by quantization error only and results directly from the ADC’s resolution (N bits): SNRdB[max] = 6.02dB x N + 1.76dB In reality, other noise sources such as thermal noise, clock jitter, signal phase noise, and transfer function nonlinearities are also contributing to the SNR calculation and should be considered when determining the SNR in ADC. T/H HOLD TRACK Figure 11. Aperture Jitter/Delay Specifications Spurious-Free Dynamic Range (SFDR) SFDR is the ratio of RMS amplitude of the carrier frequency (maximum signal component) to the RMS value of the next-largest noise or harmonic distortion component. SFDR is usually measured in dBc with respect to the carrier frequency amplitude or in dBFS with respect to the ADC’s full-scale range. Two-Tone Intermodulation Distortion (IMD) The two-tone IMD is the ratio expressed in decibels of either input tone to the worst 3rd-order (or higher) intermodulation products. The individual input tone levels are at -7dB full scale. Pin-Compatible Higher Resolution Versions RESOLUTION (Bits) SPEED GRADE (Msps) MAX1122 10 170 MAX1123 10 210 MAX1124 10 250 PART Signal-to-Noise Plus Distortion (SINAD) SINAD is computed by taking the ratio of the RMS signal to all spectral components excluding the fundamental and the DC offset. In case of the MAX1121, SINAD is computed from a curve fit. 16 TRACK ______________________________________________________________________________________ 1.8V, 8-Bit, 250Msps Analog-to-Digital Converter with LVDS Outputs for Wideband Applications 68L QFN.EPS PACKAGE OUTLINE, 68L QFN, 10x10x0.9 MM 1 C 21-0122 2 PACKAGE OUTLINE, 68L QFN, 10x10x0.9 MM 1 C 21-0122 2 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 17 © 2004 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products. MAX1121 Package Information (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.)