MAXIM MAX1123

19-3028; Rev 1; 2/04
1.8V, 10-Bit, 210Msps Analog-to-Digital Converter
with LVDS Outputs for Wideband Applications
Applications
Wireless and Wired Broadband Communication
Cable-Head End Systems
Digital Predistortion Receivers
Communications Test Equipment
Radar and Satellite Subsystems Antenna Array
Processing
♦ SNR = 57.4dB/56dB at fIN = 100MHz/500MHz
♦ SFDR = 74.5dBc/62.6dBc at fIN = 100MHz/500MHz
♦ NPR = 53.6dB at fNOTCH = 28.8MHz
♦ Single 1.8V Supply
♦ 460mW Power Dissipation at 210Msps
♦ On-Chip Track-and-Hold and Internal Reference
♦ On-Chip Selectable Divide-by-2 Clock Input
♦ LVDS Digital Outputs with Data Clock Output
♦ Evaluation Kit Available (Order MAX1124EVKIT)
Ordering Information
PART
MAX1123EGK
TEMP RANGE
PIN-PACKAGE
-40°C to +85°C
68 QFN-EP*
*EP = Exposed paddle.
Pin Configuration
63 62 61 60 59 58
D7P
D7N
D8N
D8P
D9N
D9P
ORN
ORP
OVCC
OGND
AVCC
AGND
67 66 65 64
AVCC
68
AVCC
AGND
TOP VIEW
AGND
For pin-compatible, lower and higher speed versions of
the MAX1123, refer to the MAX1122 (170Msps) and the
MAX1124 (250Msps) data sheets. For a higher speed,
pin-compatible 8-bit version of the MAX1123, refer to
the MAX1121 data sheet.
♦ 210Msps Conversion Rate
T/B
The MAX1123 is a monolithic 10-bit, 210Msps analogto-digital converter (ADC) optimized for outstanding
dynamic performance at high IF frequencies up to
500MHz. The product operates with conversion rates of
up to 210Msps while consuming only 460mW.
At 210Msps and an input frequency of 100MHz, the
MAX1123 achieves a spurious-free dynamic range
(SFDR) of 74.5dBc. Its excellent signal-to-noise ratio
(SNR) of 57.4dB at 10MHz remains flat (within 1.5dB)
for input tones up to 500MHz. This makes the MAX1123
ideal for wideband applications such as digital predistortion in cellular base-station transceiver systems.
The MAX1123 requires a single 1.8V supply. The analog input is designed for either differential or singleended operation and can be AC- or DC-coupled. The
ADC also features a selectable on-chip divide-by-2
clock circuit, which allows the user to apply clock frequencies as high as 420MHz. This helps to reduce the
phase noise of the input clock source. A differential
LVDS sampling clock is recommended for best performance. The converter’s digital outputs are LVDS compatible, and the data format can be selected to be
either two’s complement or offset binary.
The MAX1123 is available in a 68-pin QFN with
exposed paddle (EP) and is specified over the industrial (-40°C to +85°C) temperature range.
Features
57 56 55 54 53 52
AVCC
1
AGND
2
REFIO
3
REFADJ
4
48 D5N
AGND
5
47 D4P
51 D6P
50 D6N
EP
49 D5P
AVCC
6
46 D4N
AGND
7
45 OGND
INP
8
INN
9
44 OVCC
43 DCLKP
MAX1123
AGND 10
42 DCLKN
AVCC 11
41 OVCC
AVCC 12
40 D3P
AVCC 13
39 D3N
AVCC 14
38 D2P
AGND 15
37 D2N
AGND 16
36 D1P
CLKDIV 17
35 D1N
D0P
D0N
N.C.
N.C.
N.C.
N.C.
OVCC
OVCC
OGND
AVCC
AGND
CLKN
CLKP
AGND
AVCC
AGND
AGND
18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
________________________________________________________________ Maxim Integrated Products
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
1
MAX1123
General Description
MAX1123
1.8V, 10-Bit, 210Msps Analog-to-Digital Converter
with LVDS Outputs for Wideband Applications
ABSOLUTE MAXIMUM RATINGS
AVCC to AGND ......................................................-0.3V to +2.1V
OVCC to OGND .....................................................-0.3V to +2.1V
AGND to OGND ....................................................-0.3V to +0.3V
Analog Inputs to AGND ...........................-0.3V to (AVCC + 0.3V)
Digital Inputs to AGND.............................-0.3V to (AVCC + 0.3V)
REF, REFADJ to AGND............................-0.3V to (AVCC + 0.3V)
Digital Outputs to OGND .........................-0.3V to (OVCC + 0.3V)
ESD on All Pins (Human Body Model).............................±2000V
Continuous Power Dissipation (TA = +70°C)
68-Pin QFN (derate 41.7mW/°C above +70°C) .........3333mW
Operating Temperature Range ...........................-40°C to +85°C
Junction Temperature ......................................................+150°C
Storage Temperature Range .............................-60°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
Maximum Current into Any Pin............................................50mA
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(AVCC = OVCC = 1.8V, AGND = OGND = 0, fSAMPLE = 210MHz, differential sine-wave clock input drive, 0.1µF capacitor on REFIO,
internal reference, digital output pins differential RL = 100Ω ±1%, CL = 5pF, TA = TMIN to TMAX, unless otherwise noted. ≥25°C guaranteed by production test, <25°C guaranteed by design and characterization. Typical values are at TA = +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
DC ACCURACY
Resolution
10
Integral Nonlinearity
INL
(Note 1)
Differential Nonlinearity
DNL
No missing codes (Note 1)
Transfer Curve Offset
VOS
(Note 1)
Bits
-2
±0.4
+2
LSB
-1.0
±0.3
+1.5
LSB
TA ≥ +25°C
-25
+25
(Note 2)
-37
+37
Offset Temperature Drift
±20
LSB
µV/°C
ANALOG INPUTS (INP, INN)
Full-Scale Input Voltage Range
VFS
(Note 1)
1100
Full-Scale Range Temperature
Drift
Common-Mode Input Range
VCM
Input Capacitance
CIN
Differential Input Resistance
RIN
Full-Power Analog Bandwidth
FPBW
1250
1375
130
ppm/°C
1.38
±0.18
V
3
3.00
Figure 8
mVP-P
4.3
pF
6.25
600
kΩ
MHz
REFERENCE (REFIO, REFADJ)
Reference Output Voltage
VREFIO
1.18
VREFADJ
AVCC 0.3
Reference Temperature Drift
REFADJ Input High Voltage
1.24
90
Used to disable the internal reference
1.30
V
ppm/°C
V
SAMPLING CHARACTERISTICS
Maximum Sampling Rate
fSAMPLE
Minimum Sampling Rate
fSAMPLE
2
210
MHz
20
_______________________________________________________________________________________
MHz
1.8V, 10-Bit, 210Msps Analog-to-Digital Converter
with LVDS Outputs for Wideband Applications
(AVCC = OVCC = 1.8V, AGND = OGND = 0, fSAMPLE = 210MHz, differential sine-wave clock input drive, 0.1µF capacitor on REFIO,
internal reference, digital output pins differential RL = 100Ω ±1%, CL = 5pF, TA = TMIN to TMAX, unless otherwise noted. ≥25°C guaranteed by production test, <25°C guaranteed by design and characterization. Typical values are at TA = +25°C.)
PARAMETER
SYMBOL
Clock Duty Cycle
CONDITIONS
MIN
Set by clock management circuit
TYP
MAX
UNITS
40 to 60
%
Aperture Delay
tAD
350
ps
Aperture Jitter
tAJ
0.21
psRMS
500
mVP-P
1.15
±0.2
V
CLOCK INPUTS (CLKP, CLKN)
Differential Clock Input Amplitude
(Note 2)
200
Clock Input Common-Mode
Voltage Range
Clock Differential Input
Resistance
RCLK
11 ±
25%
kΩ
Clock Differential Input
Capacitance
CCLK
5
pF
DYNAMIC CHARACTERISTICS (at -0.5dBFS)
Signal-to-Noise Ratio
Signal-to-Noise
and Distortion
SNR
SINAD
fIN = 10MHz, TA ≥ +25°C
56
57.5
fIN = 100MHz, TA ≥ +25°C
55.5
57.1
fIN = 180MHz
57
fIN = 500MHz
56
fIN = 10MHz, TA ≥ +25°C
55.5
fIN = 100MHz, TA ≥ +25°C
55
fIN = 180MHz
SFDR
Worst Harmonics
(HD2 or HD3)
Two-Tone Intermodulation
Distortion
57.4
57
dB
56.5
fIN = 500MHz
Spurious-Free
Dynamic Range
dB
55
fIN = 10MHz, TA ≥ +25°C
63
77
fIN = 100MHz, TA ≥ +25°C
61
72
fIN = 180MHz
66.3
fIN = 500MHz
62.5
fIN = 10MHz
-77
fIN = 100MHz
-72
fIN = 180MHz
-66.3
fIN = 500MHz
-62.5
IMD100
fIN1 = 99MHz at -7dBFS,
fIN2 = 101MHz at -7dBFS
-75
IMD500
fIN1 = 498.5MHz at -7dBFS,
fIN2 = 502.5MHz at -7dBFS
-58
dBc
dBc
dBc
LVDS DIGITAL OUTPUTS (D0P/N–D9P/N, DCLKP/N)
Differential Output Voltage
|VOD|
250
400
mV
_______________________________________________________________________________________
3
MAX1123
ELECTRICAL CHARACTERISTICS (continued)
MAX1123
1.8V, 10-Bit, 210Msps Analog-to-Digital Converter
with LVDS Outputs for Wideband Applications
ELECTRICAL CHARACTERISTICS (continued)
(AVCC = OVCC = 1.8V, AGND = OGND = 0, fSAMPLE = 210MHz, differential sine-wave clock input drive, 0.1µF capacitor on REFIO,
internal reference, digital output pins differential RL = 100Ω ±1%, CL = 5pF, TA = TMIN to TMAX, unless otherwise noted. ≥25°C guaranteed by production test, <25°C guaranteed by design and characterization. Typical values are at TA = +25°C.)
PARAMETER
Output Offset Voltage
SYMBOL
CONDITIONS
OVOS
MIN
TYP
1.125
MAX
UNITS
1.310
V
0.2 x
AVCC
V
LVCMOS DIGITAL INPUTS (CLKDIV, T/B)
Digital Input Voltage Low
VIL
Digital Input Voltage High
VIH
0.8 x
AVCC
V
TIMING CHARACTERISTICS
CLK to Data Propagation Delay
tPDL
Figure 4
1.5
ns
CLK to DCLK Propagation Delay
tCPDL
Figure 4
3.01
ns
Data Valid to DCLK Rising Edge
tCPDL tPDL
Figure 4 (Note 2)
1.23
1.51
1.84
ns
LVDS Output Rise-Time
tRISE
20% to 80%, CL = 5pF
460
LVDS Output Fall-Time
tFALL
20% to 80%, CL = 5pF
460
ps
8
Clock
cycles
Output Data Pipeline Delay
tLATENCY
ps
POWER REQUIREMENTS
Analog Supply Voltage Range
AVCC
1.7
1.8
1.9
V
Digital Supply Voltage Range
OVCC
1.7
1.8
1.9
V
mA
Analog Supply
IAVCC
fIN = 100MHz
210
280
Digital Supply Current
IOVCC
fIN = 100MHz
45
75
mA
Analog Power Dissipation
PDISS
fIN = 100MHz
460
640
mW
Power-Supply Rejection Ratio
(Note 3)
PSRR
Offset
1.6
mV/V
Gain
1.9
%FS/V
Note 1: Static linearity and offset parameters are computed from a best-fit straight line through the code transition points. The fullscale range is defined as 1023 x slope of the line.
Note 2: Parameter guaranteed by design and characterization; TA = TMIN to TMAX.
Note 3: PSRR is measured with both analog and digital supplies connected to the same potential.
4
_______________________________________________________________________________________
1.8V, 10-Bit, 210Msps Analog-to-Digital Converter
with LVDS Outputs for Wideband Applications
FFT PLOT (8192-POINT DATA RECORD,
COHERENT SAMPLING)
-40
-30
-50
-60
-70
HD2
-40
-60
HD3
-40
-50
-90
-90
-90
-100
-100
60
80
100
120
0
-40
-50
0
58
57
HD2
54
51
-100
50
20
40
60
80
100
100
120
80
75
65
60
55
50
45
40
35
30
0
120
80
70
55
-90
60
85
52
-80
40
SFDR vs. ANALOG INPUT FREQUENCY
(fSAMPLE = 210.0057MHz, AIN = -0.5dBFS)
53
-70
0
20
ANALOG INPUT FREQUENCY (MHz)
56
HD3
-60
120
SFDR (dBc)
-30
100
59
SNR (dB)
-20
80
MAX1123 toc05
fSAMPLE = 210.0057MHz
fIN = 500.0196MHz
AIN = -0.4975dBFS
SNR = 55.9dB
SFDR = 62.5dBc
HD2 = -69.5dBc
HD3 = -62.5dBc
60
SNR vs. ANALOG INPUT FREQUENCY
(fSAMPLE = 210.0057MHz, AIN = -0.5dBFS)
MAX1123 toc04
0
40
ANALOG INPUT FREQUENCY (MHz)
FFT PLOT (8192-POINT DATA RECORD,
COHERENT SAMPLING)
-10
20
MAX1123 toc06
40
HD2
-80
-100
20
HD3
-60
-70
HD2
ANALOG INPUT FREQUENCY (MHz)
100
200
300
400
500
100
0
200
300
400
500
ANALOG INPUT FREQUENCY (MHz)
fIN (MHz)
fIN (MHz)
HD2/HD3 vs. ANALOG INPUT FREQUENCY
(fSAMPLE = 210.0057MHz, AIN = -0.5dBFS)
SNR vs. ANALOG INPUT AMPLITUDE
(fSAMPLE = 210.0057MHz, fIN = 60.0126MHz)
SFDR vs. ANALOG INPUT AMPLITUDE
(fSAMPLE = 210.0057MHz, fIN = 60.0126MHz)
80
57
MAX1123 toc09
HD3
-60
62
MAX1123 toc07
-50
MAX1123 toc08
AMPLITUDE (dB)
-20
-80
0
fSAMPLE = 210.0057MHz
fIN = 183.5242MHz
AIN = -0.5245dBFS
SNR = 57dB
SFDR = 66.6dBc
HD2 = -82.9dBc
HD3 = -66.9dBc
-10
-30
-50
-70
HD3
-80
0
MAX1123 toc03
-20
AMPLITUDE (dB)
AMPLITUDE (dB)
-30
fSAMPLE = 210.0057MHz
fIN = 60.1152MHz
AIN = -0.4885dBFS
SNR = 57.4dB
SFDR = 76.2dBc
HD2 = -83.9dBc
HD3 = -76.2dBc
-10
AMPLITUDE (dB)
fSAMPLE = 210.0057MHz
fIN = 11.5103MHz
AIN = -0.542dBFS
SNR = 57.5dB
SFDR = 79.5dBc
HD2 = -82dBc
HD3 = -86.3dBc
-20
0
MAX1123 toc01
0
-10
FFT PLOT (8192-POINT DATA RECORD,
COHERENT SAMPLING)
MAX1123 toc02
FFT PLOT (8192-POINT DATA RECORD,
COHERENT SAMPLING)
75
-80
HD2
SFDR (dBc)
70
SNR (dB)
HD2/HD3 (dBc)
52
-70
47
42
60
37
-90
55
32
-100
27
0
100
200
300
fIN (MHz)
400
500
65
50
-28
-24
-20
-16
-12
-8
-4
ANALOG INPUT AMPLITUDE (dBFS)
0
-28
-24
-20
-16
-12
-8
-4
0
ANALOG INPUT AMPLITUDE (dBFS)
_______________________________________________________________________________________
5
MAX1123
Typical Operating Characteristics
(AVCC = OVCC = 1.8V, AGND = OGND = 0, fSAMPLE = 210.0057MHz, -0.5dBFS; see TOCs for detailed information on test conditions, differential input drive, differential sine-wave clock input drive, 0.1µF capacitor on REFIO, internal reference, digital output pins
differential RL = 100Ω, TA = +25°C.)
Typical Operating Characteristics (continued)
(AVCC = OVCC = 1.8V, AGND = OGND = 0, fSAMPLE = 210.0057MHz, -0.5dBFS; see TOCs for detailed information on test conditions, differential input drive, differential sine-wave clock input drive, 0.1µF capacitor on REFIO, internal reference, digital output pins
differential RL = 100Ω, TA = +25°C.)
SNR vs. fSAMPLE
(fIN = 60.0126MHz, AIN = -0.5dBFS)
59
58
HD3
-65
56
SNR (dB)
-70
HD2
-75
80
57
SFDR (dBc)
-60
90
MAX1123 toc11
-55
HD2/HD3 (dBc)
60
MAX1123 toc10
-50
SFDR vs. fSAMPLE
(fIN = 60.0126MHz, AIN = -0.5dBFS)
MAX1123 toc12
HD2/HD3 vs. ANALOG INPUT AMPLITUDE
(fSAMPLE = 210.0057MHz, fIN = 60.0126MHz)
55
54
70
60
53
-80
52
-85
50
51
40
50
-90
10 30 50 70 90 110 130 150 170 190 210
10 30 50 70 90 110 130 150 170 190 210
ANALOG INPUT AMPLITUDE (dBFS)
fSAMPLE (MHz)
fSAMPLE (MHz)
HD2/HD3 vs. fSAMPLE
(fIN = 60.0126MHz, AIN = -0.5dBFS)
TWO-TONE IMD PLOT (8192-POINT
DATA RECORD, COHERENT SAMPLING)
INTEGRAL NONLINEARITY
vs. DIGITAL OUTPUT CODE
-16
-12
-8
-4
0
MAX1123 toc13
-60
0
-20
HD3
AMPLITUDE (dB)
HD2/HD3 (dBc)
-30
-76
-84
-40
HD2
-100
10 30 50 70 90 110 130 150 170 190 210
2fIN2 fIN1
2fIN1 - fIN2
0.1
0
-0.1
-0.2
-80
-0.3
-90
-0.4
-0.5
-100
0
20
40
60
80
100
0
120
128 256 384 512 640 768 896 1024
fSAMPLE (MHz)
ANALOG INPUT FREQUENCY (MHz)
DIGITAL OUTPUT CODE
DIFFERENTIAL NONLINEARITY
vs. DIGITAL OUTPUT CODE
GAIN BANDWIDTH PLOT
(fSAMPLE = 210.0057MHz, AIN = -0.5dBFS)
SNR vs. TEMPERATURE (fIN = 64.9974MHz,
fSAMPLE = 210.0428MHz, AIN = -0.5dBFS)
2
MAX1123 toc16
0.5
0.4
0.3
0
60
59
58
-2
GAIN (dB)
0.1
0
-0.1
-0.2
57
SNR (dB)
0.2
-4
-6
56
55
54
53
-8
-0.3
52
-10
-0.4
-0.5
51
50
-12
0
128 256 384 512 640 768 896 1024
DIGITAL OUTPUT CODE
6
0.3
MAX1123 toc17
-92
fIN2
-50
-70
0.4
0.2
fIN1
-60
0.5
MAX1123 toc18
-68
fSAMPLE = 210.0057MHz
fIN1 = 99.0298MHz
fIN2 = 101.0293MHz
AIN1 = AIN2 = -7dBFS
IMD = -75dBc
-10
MAX1123 toc15
-20
INL (LSB)
-24
MAX1123 toc14
-28
DNL (LSB)
MAX1123
1.8V, 10-Bit, 210Msps Analog-to-Digital Converter
with LVDS Outputs for Wideband Applications
10
100
ANALOG INPUT FREQUENCY (MHz)
1000
-40
-15
10
35
TEMPERATURE (°C)
_______________________________________________________________________________________
60
85
1.8V, 10-Bit, 210Msps Analog-to-Digital Converter
with LVDS Outputs for Wideband Applications
58
75
485
475
56
55
54
PDISS (mW)
70
SFDR (dBc)
SINAD (dBc)
57
495
65
60
53
52
55
10
35
60
425
-15
-40
85
TEMPERATURE (°C)
1.30
60
MAX1123 toc22
FIGURE 6
1.32
59
10 30 50 70 90 110 130 150 170 190 210
85
fSAMPLE (MHz)
AVCC = OVCC
58
INTERNAL REFERENCE vs. SUPPLY VOLTAGE
(fSAMPLE = 210.0057MHz)
1.2325
MEASURED AT THE REFIO PIN
REFADJ = AVCC = OVCC
1.2320
57
1.26
1.24
1.22
56
VREFIO (V)
SNR (dB)
RESISTOR VALUE APPLIED
BETWEEN REFADJ AND AGND
55
54
1.2315
1.2310
53
RESISTOR VALUE APPLIED
BETWEEN REFADJ AND REFIO
1.2305
52
1.18
51
1.2300
50
1.16
1.5
0 100 200 300 400 500 600 700 800 900 1000
1.6
1.7
1.8
1.9
2.0
1.5
2.1
1.6
3.0E+05
2.0E+04
174671
1.0E+04
1.9
2.0
2.1
MAX1123 toc26
5
PROPAGATION DELAY (ns)
4.0E+05
6
MAX1123 toc25
fSAMPLE = 210MHz
467263
1.8
PROPAGATION DELAY TIMES
vs. TEMPERATURE
NOISE HISTOGRAM
(DC INPUT, 256k-POINT DATA RECORD)
5.0E+05
1.7
SUPPLY VOLTAGE (V)
VOLTAGE SUPPLY (V)
FS ADJUST RESISTOR (Ω)
CODE COUNTS
VFS (V)
60
SNR vs. VOLTAGE SUPPLY
(fIN = 60.0126MHz, AIN = -0.5dBFS)
FS VOLTAGE vs. FS ADJUST RESISTOR
1.20
35
TEMPERATURE (°C)
1.34
1.28
10
MAX1123 toc23
-15
455
435
50
-40
465
445
51
50
MAX1123 toc21
59
MAX1123 toc20
80
MAX1123 toc19
60
POWER DISSIPATION vs. fSAMPLE
(fIN = 60.0126MHz, AIN = -0.5dBFS)
SFDR vs. TEMPERATURE (fIN = 64.9974MHz,
fSAMPLE = 210.0428MHz, AIN = -0.5dBFS)
MAX1123 toc24
SINAD vs. TEMPERATURE (fIN = 64.9974MHz,
fSAMPLE = 210.0428MHz, AIN = -0.5dBFS)
4
tCPDL
3
2
1
13207
511
tPDL
219
0.0E+00
512
513
514
DIGITAL OUTPUT NOISE
0
515
-40
-15
10
35
60
85
TEMPERATURE (°C)
_______________________________________________________________________________________
7
MAX1123
Typical Operating Characteristics (continued)
(AVCC = OVCC = 1.8V, AGND = OGND = 0, fSAMPLE = 210.0057MHz, -0.5dBFS; see TOCs for detailed information on test conditions, differential input drive, differential sine-wave clock input drive, 0.1µF capacitor on REFIO, internal reference, digital output pins
differential RL = 100Ω, TA = +25°C.)
Typical Operating Characteristics (continued)
(AVCC = OVCC = 1.8V, AGND = OGND = 0, fSAMPLE = 210.0057MHz, -0.5dBFS; see TOCs for detailed information on test conditions, differential input drive, differential sine-wave clock input drive, 0.1µF capacitor on REFIO, internal reference, digital output pins
differential RL = 100Ω, TA = +25°C.)
SINAD vs. CLOCK DUTY CYCLE (fIN = 1.4106MHz,
fSAMPLE = 210.0428MHz, AIN = -0.5dBFS)
58
57
56
55
54
53
52
MAX1123 toc28
59
NOISE POWER RATIO PLOT
-40
POWER SPECTRAL DENSITY (dB)
MAX1123 toc27
60
SINAD (dB)
MAX1123
1.8V, 10-Bit, 210Msps Analog-to-Digital Converter
with LVDS Outputs for Wideband Applications
-50
-60
-70
-80
-90
fSAMPLE = 210MHz
fNOTCH = 28.8MHz
NPR = 53.6dB
-100
51
50
30
36
42
48
54
60
66
72
CLOCK DUTY CYCLE (%)
5
10
15
20
25
30
35
ANALOG INPUT FREQUENCY (MHz)
Pin Description
PIN
NAME
1, 6, 11–14, 20, 25,
62, 63, 65
AVCC
Analog Supply Voltage. Bypass each pin with a 0.1µF capacitor for best decoupling results.
2, 5, 7, 10, 15, 16,
18, 19, 21, 24, 64,
66, 67, EP
AGND
Analog Converter Ground. Connect the converter’s exposed paddle (EP) to AGND.
3
REFIO
Reference Input/Output. With REFADJ pulled high through a 1kΩ resistor, this I/O port allows
an external reference source to be connected to the MAX1123. With REFADJ pulled low
through the same 1kΩ resistor, the internal 1.23V bandgap reference is active.
REFADJ
Reference-Adjust Input. REFADJ allows for full-scale range adjustments by placing a resistor
or trim potentiometer between REFADJ and AGND (decreases FS range) or REFADJ and
REFIO (increases FS range). If REFADJ is connected to AVCC through a 1kΩ resistor, the
internal reference can be overdriven with an external source connected to REFIO. If REFADJ
is connected to AGND through a 1kΩ resistor, the internal reference is used to determine the
full-scale range of the data converter.
4
8
FUNCTION
8
INP
Positive Analog Input Terminal
9
INN
Negative Analog Input Terminal
Clock Divider Input. This LVCMOS-compatible input controls which speed the converter’s
digital outputs are updated. CLKDIV has an internal pulldown resistor.
CLKDIV = 0: ADC updates digital outputs at one-half the input clock rate.
CLKDIV = 1: ADC updates digital outputs at the input clock rate.
17
CLKDIV
22
CLKP
True Clock Input. This input requires an LVDS-compatible input level to maintain the
converter’s excellent performance.
23
CLKN
Complementary Clock Input. This input requires an LVDS-compatible input level to maintain
the converter’s excellent performance.
_______________________________________________________________________________________
1.8V, 10-Bit, 210Msps Analog-to-Digital Converter
with LVDS Outputs for Wideband Applications
PIN
NAME
FUNCTION
26, 45, 61
OGND
Digital Converter Ground. Ground connection for digital circuitry and output drivers.
27, 28, 41, 44, 60
OVCC
Digital Supply Voltage. Bypass with a 0.1µF capacitor for best decoupling results.
29–32
N.C.
No Connection. Do not connect to these pins.
33
D0N
Complementary Output Bit 0 (LSB)
34
D0P
True Output Bit 0 (LSB)
35
D1N
Complementary Output Bit 1
36
D1P
True Output Bit 1
37
D2N
Complementary Output Bit 2
38
D2P
True Output Bit 2
39
D3N
Complementary Output Bit 3
40
D3P
True Output Bit 3
42
DCLKN
Complementary Clock Output. This output provides an LVDS-compatible output level and can
be used to synchronize external devices to the converter clock. There is a 2.1ns delay
between CLKP and DCLKP.
43
DCLKP
True Clock Output. This output provides an LVDS-compatible output level and can be used to
synchronize external devices to the converter clock. There is a 2.1ns delay between CLKN
and DCLKN.
46
D4N
Complementary Output Bit 4
47
D4P
True Output Bit 4
48
D5N
Complementary Output Bit 5
49
D5P
True Output Bit 5
50
D6N
Complementary Output Bit 6
51
D6P
True Output Bit 6
52
D7N
Complementary Output Bit 7
53
D7P
True Output Bit 7
54
D8N
Complementary Output Bit 8
55
D8P
True Output Bit 8
56
D9N
Complementary Output Bit 9 (MSB)
57
D9P
True Output Bit 9 (MSB)
58
ORN
Complementary Output for Out-of-Range Control Bit. If an out-of-range condition is detected,
bit ORN flags this condition by transitioning low.
59
ORP
True Output for Out-of-Range Control Bit. If an out-of-range condition is detected, bit ORP
flags this condition by transitioning high.
T/B
Two’s Complement or Binary Output Format Selection. This LVCMOS-compatible input
controls the digital output format of the MAX1123. T/B has an internal pulldown resistor.
T/B = 0: Two’s complement output format
T/B = 1: Binary output format
68
_______________________________________________________________________________________
9
MAX1123
Pin Description (continued)
MAX1123
1.8V, 10-Bit, 210Msps Analog-to-Digital Converter
with LVDS Outputs for Wideband Applications
CLKDIV
CLKP
CLOCKDIVIDER
CONTROL
CLKN
INPUT
BUFFER
INP
DCLKP
DCLKN
CLOCK
MANAGEMENT
T/H
INN
LVDS
DATA PORT
10-BIT PIPELINE
QUANTIZER CORE
D0P/N–D9P/N
10
2.2kΩ
2.2kΩ
ORP
REFERENCE
ORN
COMMON-MODE
BUFFER
MAX1123
REFIO REFADJ
Figure 1. MAX1123 Block Diagram
AVCC
ADC FULL-SCALE = REFT - REFB
REFT
INP
2.2kΩ
G
REFB
INN
REFERENCESCALING
AMPLIFIER
REFERENCE
BUFFER
2.2kΩ
REFIO
0.1µF
1V
TO COMMON-MODE INPUT
TO COMMON-MODE INPUT
REFADJ
AGND
Figure 2. Simplified Analog Input Architecture
Detailed Description—Theory
of Operation
The MAX1123 uses a fully differential, pipelined architecture that allows for high-speed conversion, optimized accuracy and linearity, while minimizing power
consumption and die size.
Both positive (INP) and negative/complementary analog
input terminals (INN) are centered around a commonmode voltage of 1.4V, and accept a differential analog
input voltage swing of ±0.3125V each, resulting in a typical differential full-scale signal swing of 1.25VP-P.
INP and INN are buffered prior to entering each trackand-hold (T/H) stage and are sampled when the differential sampling clock signal transitions high. A 2-bit ADC
following the first T/H stage then digitizes the signal, and
controls a 2-bit digital-to-analog converter (DAC).
Digitized and reference signals are then subtracted,
10
CONTROL LINE TO
DISABLE REFERENCE
BUFFER
AVCC
1kΩ
AVCC / 2
Figure 3. Simplified Reference Architecture
resulting in a fractional residue signal that is amplified
before it is passed on to the next stage through another
T/H amplifier. This process is repeated until the applied
input signal has successfully passed through all stages
of the 10-bit quantizer. Finally, the digital outputs of all
stages are combined and corrected for in the digital correction logic to generate the final output code. The result
is a 10-bit parallel digital output word in user-selectable
two’s complement or binary output formats with LVDScompatible output levels. See Figure 1 for a more
detailed view of the MAX1123 architecture.
______________________________________________________________________________________
1.8V, 10-Bit, 210Msps Analog-to-Digital Converter
with LVDS Outputs for Wideband Applications
SAMPLING EVENT
SAMPLING EVENT
MAX1123
SAMPLING EVENT
SAMPLING EVENT
INN
INP
tCH
tAD
tCL
CLKN
N
N+1
N+8
N+9
CLKP
tCPDL
tLATENCY
DCLKP
N-8
N-7
N
N+1
DCLKN
tCPDL - tPDL
tPDL
D0P/N–D9P/N
ORP/N
N-8
N-7
N-1
N
N+1
tCPDL - tPDL ~ 0.4 x tSAMPLE with tSAMPLE = 1/fSAMPLE
NOTE: THE ADC SAMPLES ON THE RISING EDGE OF CLKP. THE RISING EDGE OF DCLKP CAN BE USED TO EXTERNALLY LATCH THE OUTPUT DATA.
Figure 4. System and Output Timing Diagram
Analog Inputs (INP, INN)
INP and INN are the fully differential inputs of the
MAX1123. Differential inputs usually feature good rejection of even-order harmonics, which allows for enhanced
AC performance as the signals are progressing through
the analog stages. The MAX1123 analog inputs are selfbiased at a common-mode voltage of 1.4V and allow a
differential input voltage swing of 1.25VP-P. Both inputs
are self-biased through 2.2kΩ resistors, resulting in a
typical differential input resistance of 4.4kΩ. It is recommended to drive the analog inputs of the MAX1123 in
AC-coupled configuration to achieve best dynamic performance. See the AC-Coupled Analog Inputs section for
a detailed discussion of this configuration.
OVCC
VOP
2.2kΩ
VON
2.2kΩ
On-Chip Reference Circuit
The MAX1123 features an internal 1.23V bandgap reference circuit (Figure 3), which, in combination with an
internal reference-scaling amplifier, determines the fullscale range of the MAX1123. Bypass REFIO with a
0.1µF capacitor to AGND. To compensate for gain
errors or increase the ADC’s full-scale range, the voltage of this bandgap reference can be indirectly adjusted by adding an external resistor (e.g., 100kΩ trim
potentiometer) between REFADJ and AGND or
REFADJ and REFIO. See the Applications Information
section for a detailed description of this process.
OGND
Figure 5. Simplified LVDS Output Architecture
______________________________________________________________________________________
11
MAX1123
1.8V, 10-Bit, 210Msps Analog-to-Digital Converter
with LVDS Outputs for Wideband Applications
Table 1. MAX1123 Digital Output Coding
INP ANALOG
VOLTAGE LEVEL
INN ANALOG
VOLTAGE LEVEL
OUT-OF-RANGE
ORP (ORN)
BINARY
DIGITAL OUTPUT CODE
(D9–D0)
TWO’S COMPLEMENT
DIGITAL OUTPUT CODE
(D9–D0)
> VCM + 0.3125V
< VCM - 0.3125V
1 (0)
11 1111 1111
(exceeds positive full scale,
OR set)
01 1111 1111
(exceeds positive full scale,
OR set)
VCM + 0.3125V
VCM - 0.3125V
0 (1)
11 1111 1111
(represents positive full
scale)
01 1111 1111
(represents positive full
scale)
VCM
VCM
0 (1)
10 0000 0000 or
01 1111 1111
(represents midscale)
00 0000 0000 or
11 1111 1111
(represents midscale)
VCM - 0.3125V
VCM + 0.3125V
0 (1)
00 0000 0000
(represents negative full
scale)
10 0000 0000
(represents negative full
scale)
< VCM - 0.3125V
> VCM + 0.3125V
1 (0)
00 0000 0000
(exceeds negative full scale,
OR set)
10 0000 0000
(exceeds negative full scale,
OR set)
Clock Inputs (CLKP, CLKN)
Clock Outputs (DCLKP, DCLKN)
Designed for a differential LVDS clock input drive, it is
recommended to drive the clock inputs of the MAX1123
with an LVDS-compatible clock to achieve the best
dynamic performance. The clock signal source must be
a high-quality, low phase noise to avoid any degradation in the noise performance of the ADC. The clock
inputs (CLKP, CLKN) are internally biased to 1.2V,
accept a differential signal swing of 0.2VP-P to 1.0VP-P
and are usually driven in AC-coupled configuration.
See the Differential, AC-Coupled Clock Input in the
Applications Information section for more circuit details
on how to drive CLKP and CLKN appropriately.
Although not recommended, the clock inputs also
accept a single-ended input signal.
The MAX1123 also features an internal clock management circuit (duty-cycle equalizer) that ensures that the
clock signal applied to inputs CLKP and CLKN is
processed to provide a 50% duty cycle clock signal,
which desensitizes the performance of the converter to
variations in the duty cycle of the input clock source.
Note that the clock duty-cycle equalizer cannot be
turned off externally and requires a minimum clock frequency of >20MHz to work appropriately and according to data sheet specifications.
The MAX1123 features a differential clock output, which
can be used to latch the digital output data with an
external latch or receiver. Additionally, the clock output
can be used to synchronize external devices (e.g.,
FPGAs) to the ADC. DCLKP and DCLKN are differential
outputs with LVDS-compatible voltage levels. There is a
2.1ns delay time between the rising (falling) edge of
CLKP (CLKN) and the rising edge of DCLKP (DCLKN).
See Figure 4 for timing details.
12
Divide-by-2 Clock Control (CLKDIV)
The MAX1123 offers a clock control line (CLKDIV),
which supports the reduction of clock jitter in a system.
Connect CLKDIV to OGND to enable the ADC’s internal
divide-by-2 clock divider. Data is now updated at onehalf the ADC’s input clock rate. CLKDIV has an internal
pulldown resistor and can be left open for applications
that only operate with update rates one-half of the converter’s sampling rate. Connecting CLKDIV to OVCC
allows data to be updated at the speed of the ADC input
clock.
System Timing Requirements
Figure 4 depicts the relationship between the clock
input and output, analog input, sampling event, and
data output. The MAX1123 samples on the rising
(falling) edge of CLKP (CLKN). Output data is valid on
the next rising (falling) edge of the DCLKP (DCLKN)
clock, but has an internal latency of eight clock cycles.
______________________________________________________________________________________
1.8V, 10-Bit, 210Msps Analog-to-Digital Converter
with LVDS Outputs for Wideband Applications
REFERENCESCALING
AMPLIFIER
ADC FULL-SCALE = REFT - REFB
The digital outputs D0P/N–D9P/N, DCLKP/N, and
ORP/N are LVDS compatible, and data on
D0P/N–D9P/N is presented in either binary or two’s
complement format (Table 1). The T/B control line is an
LVCMOS-compatible input, which allows the user to
select the desired output format. Pulling T/B low outputs data in two’s complement and pulling it high presents data in offset binary format on the 10-bit parallel
bus. T/B has an internal pulldown resistor and may be
left unconnected in applications using only two’s complement output format. All LVDS outputs provide a typical voltage swing of 0.4V around a common-mode
voltage of approximately 1.2V, and must be terminated
at the far end of each transmission line pair (true and
complementary) with 100Ω. The LVDS outputs are powered from a separate power supply, which can be
operated between 1.7V and 1.9V.
The MAX1123 offers an additional differential output
pair (ORP, ORN) to flag out-of-range conditions, where
out of range is above positive or below negative full
scale. An out-of-range condition is identified with ORP
(ORN) transitioning high (low).
Note: Although differential LVDS reduces single-ended
transients to the supply and ground planes, capacitive
loading on the digital outputs should still be kept as low
as possible. Using LVDS buffers on the digital outputs
of the ADC when driving off-board may improve overall
performance and reduce system timing constraints.
REFT
G
REFB
REFERENCE
BUFFER
REFIO
0.1µF
13kΩ TO 1MΩ
1V
REFADJ
CONTROL LINE TO
DISABLE REFERENCE
BUFFER
AVCC
13kΩ TO 1MΩ
AVCC / 2
Figure 6. Circuit Suggestions to Adjust the ADC’s Full-Scale
Range
Applications Information
Full-Scale Range Adjustments Using the
Internal Bandgap Reference
The MAX1123 supports a full-scale adjustment range of
10% (±5%). To decrease the full-scale range, an external resistor value ranging from 13kΩ to 1MΩ may be
added between REFADJ and AGND. A similar
approach can be taken to increase the ADCs full-scale
range. Adding a variable resistor, potentiometer, or
VCLK
0.1µF
8
SINGLE-ENDED
INPUT TERMINAL 0.1µF
0.1µF
7
2
150Ω
MC100LVEL16
6
3
510Ω
AVCC OVCC
0.1µF
50Ω
150Ω
510Ω
4
0.01µF
INP
CLKN CLKP
D0P/N–D9P/N
5
MAX1123
10
INN
VGND
AGND
OGND
Figure 7. Differential, AC-Coupled, PECL-Compatible Clock Input Configuration
______________________________________________________________________________________
13
MAX1123
Digital Outputs (D0P/N–D9P/N, DCLKP/N,
ORP/N) and Control Input T/B
MAX1123
1.8V, 10-Bit, 210Msps Analog-to-Digital Converter
with LVDS Outputs for Wideband Applications
OVCC
AVCC
SINGLE-ENDED
INPUT TERMINAL 0.1µF
15Ω
ADT1–1WT
INP
D0P/N–D9P/N
25Ω
15Ω
25Ω
MAX1123
INN
10
0.1µF
AGND
OGND
Figure 8. Transformer-Coupled Analog Input Configuration with Secondary-Side Termination
predetermined resistor value between REFADJ and
REFIO increases the full-scale range of the data converter. Figure 6 shows the two possible configurations
and their impact on the overall full-scale range adjustment of the MAX1123. Do not use resistor values of less
than 13kΩ to avoid instability of the internal gain regulation loop for the bandgap reference.
Differential, AC-Coupled, PECL-Compatible
Clock Input
The preferred method of clocking the MAX1123 is differentially with LVDS- or PECL-compatible input levels. To
accomplish this, a 50Ω reverse-terminated clock signal
source with low phase noise is AC-coupled into a fast
differential receiver such as the MC100LVEL16
(Figure 7). The receiver produces the necessary PECL
output levels to drive the clock inputs of the data converter.
Differential, AC-Coupled Analog Input
An RF transformer provides an excellent solution to
convert a single-ended source signal to a fully differential signal, required by the MAX1123 for optimum
dynamic performance. In general, the MAX1123 provides the best SFDR and THD with fully differential
input signals and it is not recommended to drive the
ADC inputs in single-ended configuration. In differential
input mode, even-order harmonics are usually lower
since INP and INN are balanced, and each of the ADC
inputs only requires half the signal swing compared to
a single-ended configuration.
Figure 8 depicts a secondary-side termination of the 1:1
transformer into two separate 25Ω loads. Terminating the
transformer in this fashion reduces the potential effects of
transformer parasitics. The source impedance combined
with the shunt capacitance provided by a PC board and
the ADC’s parasitic capacitance reduce the combined
bandwidth to approximately 550MHz.
14
AVCC
SINGLE-ENDED
INPUT TERMINAL
OVCC
0.1µF
INP
D0P/N–D9P/N
50Ω
MAX1123
0.1µF
INN
10
25Ω
AGND
OGND
Figure 9. Single-Ended AC-Coupled Analog Input
Configuration
Single-Ended, AC-Coupled Analog Input
Although not recommended, the MAX1123 can be
used in single-ended mode (Figure 9). Analog signals
can be AC-coupled to the positive input INP through a
0.1µF capacitor and terminated with a 50Ω resistor to
AGND. The negative input should be 25Ω reverse-terminated and AC grounded with a 0.1µF capacitor.
Grounding, Bypassing, and Board
Layout Considerations
The MAX1123 requires board layout design techniques
suitable for high-speed data converters. This ADC provides separate analog and digital power supplies. The
analog and digital supply voltage pins accept input
voltage ranges of 1.7V to 1.9V. Although both supply
types can be combined and supplied from one source,
it is recommended to use separate sources to cut down
on performance degradation caused by digital switching currents, which can couple into the analog supply
network. Isolate analog and digital supplies (AVCC and
______________________________________________________________________________________
1.8V, 10-Bit, 210Msps Analog-to-Digital Converter
with LVDS Outputs for Wideband Applications
BYPASSING—BOARD LEVEL
AVCC
OVCC
AVCC
0.1µF
0.1µF
1µF
AGND
MAX1123
BYPASSING—ADC LEVEL
10µF
47µF
10µF
47µF
ANALOG POWERSUPPLY SOURCE
OGND
D0P/N–D9P/N
OVCC
MAX1123
10
1µF
AGND
OGND
DIGITAL/OUTPUTDRIVER POWERSUPPLY SOURCE
NOTE: EACH POWER-SUPPLY PIN (ANALOG AND DIGITAL)
SHOULD BE DECOUPLED WITH AN INDIVIDUAL 0.1µF CAPACITOR CLOSE TO THE ADC.
Figure 10. Grounding, Bypassing, and Decoupling Recommendations for the MAX1123
OVCC) where they enter the PC board with separate
networks of ferrite beads and capacitors to their corresponding grounds (AGND, OGND).
To achieve optimum performance, provide each supply
with a separate network of a 47µF tantalum capacitor in
parallel with 10µF and 1µF ceramic capacitors.
Additionally, the ADC requires each supply pin to be
bypassed with separate 0.1µF ceramic capacitors
(Figure 10). Locate these capacitors directly at the ADC
supply pins or as close as possible to the MAX1123.
Choose surface-mount capacitors, which are preferably
located on the same side as the converter, to save
space and minimize the inductance.
Multilayer boards with separated ground and power
planes produce the highest level of signal integrity.
Consider the use of a split ground plane arranged to
match the physical location of analog and digital
ground on the ADC’s package. The two ground planes
should be joined at a single point so the noisy digital
ground currents do not interfere with the analog ground
plane. A major concern with this approach are the
dynamic currents that may need to travel long distances before they are recombined at a common
source ground, resulting in large and undesirable
ground loops. Ground loops can add to digital noise by
coupling back to the analog front end of the converter,
resulting in increased spur activity and a decreased
noise performance.
Alternatively, all ground pins could share the same
ground plane, if the ground plane is sufficiently isolated
from any noisy, digital systems ground. To minimize the
effects of digital noise coupling, ground return vias can
be positioned throughout the layout to divert digital
switching currents away from the sensitive analog sections of the ADC. This does not require additional
ground splitting, but can be accomplished by placing
substantial ground connections between the analog
front end and the digital outputs.
The MAX1123 is packaged in a 68-pin QFN-EP package (package code: G6800-4), providing greater
design flexibility, increased thermal efficiency, and optimized AC performance of the ADC. The EP must be
soldered down to AGND.
In this package, the data converter die is attached to
an EP lead frame with the back of this frame exposed
at the package bottom surface, facing the PC board
side of the package. This allows a solid attachment of
the package to the PC board with standard infrared (IR)
flow soldering techniques.
Note that thermal efficiency is not the key factor, since
the MAX1123 features low-power operation. The
exposed pad is the key element to ensure a solid
ground connection between the DAC and the PC
board’s analog ground layer.
Considerable care must be taken, when routing the
digital output traces for a high-speed, high-resolution
data converter. It is essential to keep trace lengths at a
minimum and place minimal capacitive loading—less
than 5pF—on any digital trace to prevent coupling to
sensitive analog sections of the ADC. It is recommended to run the LVDS output traces as differential lines
with 100Ω characteristic impedance from the ADC to
the LVDS load device.
______________________________________________________________________________________
15
MAX1123
1.8V, 10-Bit, 210Msps Analog-to-Digital Converter
with LVDS Outputs for Wideband Applications
Static Parameter Definitions
CLKP
Integral Nonlinearity (INL)
Integral nonlinearity is the deviation of the values on an
actual transfer function from a straight line. This straight
line can be either a best straight-line fit or a line drawn
between the end points of the transfer function, once
offset and gain errors have been nullified. However, the
static linearity parameters for the MAX1123 are measured using the histogram method with an input frequency of 10MHz.
CLKN
ANALOG
INPUT
tAD
tAJ
SAMPLED
DATA (T/H)
Differential Nonlinearly (DNL)
Differential nonlinearity is the difference between an
actual step width and the ideal value of 1 LSB. A DNL
error specification of less than 1 LSB guarantees no
missing codes and a monotonic transfer function. The
MAX1123’s DNL specification is measured with the histogram method based on a 10MHz input tone.
Dynamic Parameter Definitions
Aperture Jitter
Figure 11 depicts the aperture jitter (tAJ), which is the
sample-to-sample variation in the aperture delay.
Aperture Delay
Aperture delay (tAD) is the time defined between the
falling edge of the sampling clock and the instant when
an actual sample is taken (Figure 11).
Signal-to-Noise Ratio (SNR)
For a waveform perfectly reconstructed from digital
samples, the theoretical maximum SNR is the ratio of
the full-scale analog input (RMS value) to the RMS
quantization error (residual error). The ideal, theoretical
minimum analog-to-digital noise is caused by quantization error only and results directly from the ADC’s resolution (N bits):
SNRdB[max] = 6.02dB x N + 1.76dB
In reality, other noise sources such as thermal noise,
clock jitter, signal phase noise, and transfer function
nonlinearities are also contributing to the SNR calculation and should be considered when determining the
SNR in ADC.
T/H
HOLD
TRACK
Figure 11. Aperture Jitter/Delay Specifications
Spurious-Free Dynamic Range (SFDR)
SFDR is the ratio of RMS amplitude of the carrier frequency (maximum signal component) to the RMS value
of the next-largest noise or harmonic distortion component. SFDR is usually measured in dBc with respect to
the carrier frequency amplitude or in dBFS with respect
to the ADC’s full-scale range.
Two-Tone Intermodulation Distortion (IMD)
The two-tone IMD is the ratio expressed in decibels of
either input tone to the worst 3rd-order (or higher) intermodulation products. The individual input tone levels
are at -7dB full scale.
Pin-Compatible Higher Speed/
Lower Resolution Versions
RESOLUTION
(Bits)
SPEED GRADE
(Msps)
MAX1122
10
170
MAX1124
10
250
MAX1121
8
250
PART
Signal-to-Noise Plus Distortion (SINAD)
SINAD is computed by taking the ratio of the RMS signal to all spectral components excluding the fundamental and the DC offset. In case of the MAX1123, SINAD
is computed from a curve fit.
16
TRACK
______________________________________________________________________________________
1.8V, 10-Bit, 210Msps Analog-to-Digital Converter
with LVDS Outputs for Wideband Applications
68L QFN.EPS
PACKAGE OUTLINE, 68L QFN, 10x10x0.9 MM
1
C
21-0122
2
PACKAGE OUTLINE, 68L QFN, 10x10x0.9 MM
1
C
21-0122
2
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 17
© 2004 Maxim Integrated Products
Printed USA
is a registered trademark of Maxim Integrated Products.
MAX1123
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)