ETC ICS8530

ICS8530-01
Integrated
Circuit
Systems, Inc.
LOW SKEW 1-TO-16
3.3V LVPECL FANOUT BUFFER
GENERAL DESCRIPTION
FEATURES
The ICS8530-01 is a very low skew, 1-to-16
LVPECL Fanout Buffer and a member of the
HiPerClockS™ HiPerClockS™ family of High Performance
Clock Solutions from ICS. The ICS8530-01
is designed to translate any differential signal
level to 3.3V PECL levels.
• Sixteen 3.3V LVPECL outputs
Guaranteed output and part-to-part skew characteristics
make the ICS8530-01 ideal for those clock distribution applications demanding well defined performance and repeatability.
• Translates any single-ended input signal to inverted LVPECL
levels with resistor bias on CLK input
,&6
• Translates any differential input signal(PECL, HSTL,
LVDS) to LVPECL levels without external bias networks
• Translates any single-ended input signal to LVPECL levels
with resistor bias on nCLK input
• Output frequency up to 500MHz
• 75ps output skew
• 3.3V operating supply voltage
• 48 lead low-profile QFP(LQFP), 7mm x 7mm x 1.4mm
package body, 0.5mm package lead pitch
• 0°C to 70°C ambient operating temperature
BLOCK DIAGRAM
PIN ASSIGNMENT
nCLK
VCCO
Q15
nQ15
Q14
nQ14
VEE
Q13
nQ13
Q12
nQ12
VCCO
CLK
nCLK
Q15
nQ15
Q1
nQ1
Q14
nQ14
Q2
nQ2
Q13
nQ13
Q3
nQ3
Q12
nQ12
Q4
nQ4
Q11
nQ11
Q5
nQ5
Q10
nQ10
Q6
nQ6
Q9
nQ9
Q7
nQ7
Q8
nQ8
VCCO
Q11
nQ11
Q10
nQ10
VEE
Q9
nQ9
Q8
nQ8
VCCO
VCCI
48 47 46 45 44 43 42 41 40 39 38 37
1
36
2
35
3
34
4
33
5
32
6
31
7
30
8
29
9
28
10
27
11
26
12
25
13 14 15 16 17 18 19 20 21 22 23 24
ICS8530-01
CLK
VCCO
nQ0
Q0
nQ1
Q1
VEE
nQ2
Q2
nQ3
Q3
VCCO
VCCO
nQ4
Q4
nQ5
Q5
VEE
nQ6
Q6
nQ7
Q7
VCCO
VCCI
Q0
nQ0
48-Pin LQFP
Y Package
Top View
8530-01
www.icst.com
1
REV. A - OCTOBER 2, 2000
Integrated
Circuit
Systems, Inc.
ICS8530-01
LOW SKEW 1-TO-16
3.3V LVPECL FANOUT BUFFER
TABLE 1. PIN DESCRIPTIONS
Number
1, 11,
14, 24,
25, 35,
38, 48
Name
Type
VCCO
Description
Power
Output power supply pin. Connect to 3.3V.
2, 3
Q11, nQ11
Output
Differential output. 3.3V PECL interface levels.
4, 5
Q10, nQ10
Output
Differential output. 3.3V PECL interface levels.
6, 19,
30, 43
VEE
Power
Power supply pin. Connect to ground.
7, 8
Q9, nQ9
Output
Differential output. 3.3V PECL interface levels.
9, 10
Q8, nQ8
Output
Differential output. 3.3V PECL interface levels.
12, 13
VCCI
Power
Input power supply pin. Connect to 3.3V.
15, 16
Q7, nQ7
Output
Differential output. 3.3V PECL interface levels.
17, 18
Q6, nQ6
Output
Differential output. 3.3V PECL interface levels.
20, 21
Q5, nQ5
Output
Differential output. 3.3V PECL interface levels.
22, 23
Q4, nQ4
Output
Differential output. 3.3V PECL interface levels.
26, 27
Q3, nQ3
Output
Differential output. 3.3V PECL interface levels.
28, 29
Q2, nQ2
Output
36
CLK
Input
Pulldown
37
nCLK
Input
Pullup
Differential output. 3.3V PECL interface levels.
Non inver ting differential clock input. Any differential input interface levels.
Inver ting differential clock input. Any differential input interface levels.
39, 40
Q15, nQ15
Output
Differential output. 3.3V PECL interface levels.
41, 42
Q14, nQ14
Output
Differential output. 3.3V PECL interface levels.
44, 45
Q13, nQ13
Output
Differential output. 3.3V PECL interface levels.
46, 47
Q12, nQ12
Output
Differential output. 3.3V PECL interface levels.
TABLE 2. PIN CHARACTERISTICS
Symbol
Parameter
CIN
Input Capacitance
Test Conditions
Minimum
Typical
Maximum
Units
RPULLUP
Input Pullup Resistor
51
Kohm
RPULLDOWN
Input Pulldown Resistor
51
Kohm
pF
TABLE 3. FUNCTION TABLE
Inputs
CLK
Outputs
nCLK
Q0 thru Q15
nQ0 thru nQ15
Input to Output Mode
Polarity
0
1
LOW
HIGH
Differential to Differential
Non Inver ting
1
0
HIGH
LOW
Differential to Differential
Non Inver ting
0
Biased; NOTE 1
LOW
HIGH
Single Ended to Differential
Non Inver ting
1
Biased; NOTE 1
HIGH
LOW
Single Ended to Differential
Non Inver ting
Biased; NOTE 1
0
HIGH
LOW
Single Ended to Differential
Inver ting
Biased; NOTE 1
1
LOW
HIGH
Single Ended to Differential
Inver ting
NOTE 1: Single ended use requires that one of the differential inputs be biased. The voltage at the biased input sets the switch point for
the single ended input. For LVCMOS and LVTTL levels the recommended input bias network is a resistor to VCCI, a resistor of equal value
to ground and a 0.1µF capacitor from the input to ground. The resulting switch point is approximately VCCI/2 ± 300mV.
8530-01
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2
REV. A - OCTOBER 2, 2000
ICS8530-01
Integrated
Circuit
Systems, Inc.
LOW SKEW 1-TO-16
3.3V LVPECL FANOUT BUFFER
ABSOLUTE MAXIMUM RATINGS
Supply Voltage
Inputs
Outputs
Ambient Operating Temperature
Storage Temperature
4.6V
-0.5V to VCC+0.5 V
-0.5V to VCCO+0.5V
0°C to 70°C
-65°C to 150°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only and functional operation of the device at these or any conditions beyond those listed in the DC Electrical Characteristics or AC Electrical
Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
TABLE 4. DC ELECTRICAL CHARACTERISTICS, VCCI = VCCO = 3.3V±5%, TA = 0°C TO 70°C
Symbol
Parameter
Test Conditions
Minimum
Typical
Maximum
Units
VCCI
Input Power Supply Voltage
3.135
3.3
3.465
V
VCCO
Output Power Supply Voltage
3.135
3.3
3.465
V
ICCI
Input Power Supply Current
120
mA
VPP
Peak-to-Peak Input Voltage
0.15
1.3
V
VCMR
Common Mode Input Voltage; NOTE 1
0.7
2.5
V
IIH
Input High Current
CLK, nCLK
150
µA
IIL
Input Low Current
CLK, nCLK
-150
µA
VOH
Output High Voltage; NOTE 2, 3
1.9
2.3
V
VOL
Output Low Voltage; NOTE 2, 3
1.2
1.6
V
VSWING
Peak-to-Peak Output Voltage Swing
0.55
0.85
V
NOTE 1: Common mode voltage for LVPECL is defined as the minimum VIH.
NOTE 2: Noted output levels are for VCCI equal to 3.3V. Output levels vary 1:1 with VCCI.
NOTE 3: Outputs terminated with 50 ohms to VCCO-2V. The power dissipation of a terminated output is 73mW per output pair.
TABLE 5. AC ELECTRICAL CHARACTERISTICS, VCCI = VCCO = 3.3V±5%, TA = 0°C TO 70°C
Symbol
Parameter
Test Conditions
Minimum
Typical
Maximum
Units
fMAX
Maximum Input Frequency
500
MHZ
tpLH
Propagation Delay, Low-to-High; NOTE 2
1
2
ns
tpHL
Propagation Delay, High-to-Low; NOTE 2
1
2
ns
tsk(o)
Output Skew; NOTE 3
tsk(pp)
Par t-to-Par t Skew; NOTE 4
tR
Output Rise Time
30% to 70%
100
tF
Output Fall Time
30% to 70%
100
tDC
Output Duty Cycle
88
47
50
75
ps
250
ps
600
ps
600
ps
53
%
NOTE 1: All parameters measured at 250MHz unless noted otherwise.
NOTE 2: Measured from input differential crossing poitn to the output differential crossing point for differential i nput levels. Measured from
VCCI/2 to the output differential crossing point for single-ended input levels.
NOTE 3: Defined as skew across outputs at the same supply voltages and with equal load conditions. Measured from the input crossing
point to the output differential crossing point.
NOTE 4: Defined as skew at different outputs on different devices operating at the same supply voltages and with equal load conditions.
Measured using the same type of inputs on each device, from the input differential crossing point to the output differential crossing point.
8530-01
www.icst.com
3
REV. A - OCTOBER 2, 2000
Integrated
Circuit
Systems, Inc.
ICS8530-01
LOW SKEW 1-TO-16
3.3V LVPECL FANOUT BUFFER
FIGURE 1A, 1B, 1C - INPUT CLOCK WAVEFORMS
VCC
CLK
CROSS POINTS
VPP
VCMR
nCLK
GND
FIGURE 1A - LVDS, HSTL, SSTL DIFFERENTIAL INPUT LEVELS
VCC
CLK
CROSS POINTS
VPP
VCMR
nCLK
GND
FIGURE 1B - LVPECL DIFFERENTIAL INPUT LEVEL
VCC
CLK
or
nCLK
GND
FIGURE 1C- LVCMOS / LVTTL SINGLE ENDED INPUT LEVEL
8530-01
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4
REV. A - OCTOBER 2, 2000
ICS8530-01
Integrated
Circuit
Systems, Inc.
PACKAGE OUTLINE
AND
LOW SKEW 1-TO-16
3.3V LVPECL FANOUT BUFFER
DIMENSIONS - Y SUFFIX
e /2
NOT E 4
D
NOTE 5, 7
D1
D/2
NOTE 3
-D-
-A, B, OR -D-
D1/2
b
NOTE 3
-B-
NOTE 3
-A-
E1
-A, B, OR -D-
N
O
T
E
4
E/2
N/4 TIPS
0.20 C A-B D
4X
E
N
O
T
E
5,
7
e
E1/2
SEE DETAIL “A”
8 PLACES
11 / 13°
A
-H- NOTE 2 / / 0.10 C
ccc
-CSEE DETAIL “B”
NOTE 9
ddd M C A-B S D S
0.09 / 0.20
S
Y
M
B
O
L
WITH LEAD FINISH
b
NOTES:
1. ALL DIMENSIONS AND TOLERANCING CONFORM TO ANSI
Y14.5-1982
2. DATUM PLANE -H- LOCATED AT MOLD PARTING LINE AND
COINCIDENT WITH LEAD, WHERE LEAD EXITS PLASTIC BODY
AT BOTTOM OF PARTING LINE.
3. DATUMS A-B AND -D- TO BE DETERMINED AT CENTERLINE
BETWEEN LEADS WHERE LEADS EXIT PLASTIC AT DATUM
PLANE -H- .
4. TO BE DETERMINED AT SEATING PLACE -C- .
5. DIMENSIONS D1 AND E1 DO NOT INCLUDE MOLD
PROTRUSION.
6. “N” IS THE TOTAL NUMBER OF TERMINALS.
7. THESE DIMENSIONS TO BE DETEREMINED AT DATUM PLANE
-H-.
8. PACKAGE TOP DIMENSIONS ARE SMALLER THAN BOTTOM
DIMENSIONS AND TOP OF PACKAGE WILL NOT OVERHANG
BOTTOM OF PACKAGE.
9. DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSION.
ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08mm TOTAL
IN EXCESS OF THE b DIMENSION AT MAXIMUM MATERIAL
CONDITION.
10. CONTROLLING DIMENSION: MILLIMETER.
11. THIS OUTLINE CONFORMS TO JEDEC PUBLIBCATION 95
REGISTRATION MS-026, VARIATION BBC.
12. A1 IS DEFINED AS THE DISTANCE FROM T HE SEATING PLANE
TO T HE LOWEST POINT OF THE PACKAGE.
0.09 / 0.16
JEDEC VARIATION
ALL DIMENSIONS IN MILLIMETERS
BBC
MIN.
NOM.
A
b1
BASE METAL
0° MIN.
- 0.05 S
A2
0.08/0.20 R.
DATUM
PLANE
-H-
0.05
A2
1.35
0.08
R. MIN.
0.20 MIN.
L
1.00 REF.
8530-01
www.icst.com
5
1.40
12
1.45
D
9.00 BSC.
4
7.00 BSC.
7, 8
E
9.00 BSC.
4
E1
7.00 BSC.
7, 8
0.45
0.60
0.75
48
N
0° - 7 °
0.15
D1
e
A1
MAX.
1.60
A1
L
0.25
GAUGE PLANE
N
O
T
E
0.5 BSC.
b
0.17
0.22
0.27
b1
0.17
0.20
0.23
ccc
0.08
ddd
0.08
9
REV. A - OCTOBER 2, 2000
Integrated
Circuit
Systems, Inc.
ICS8530-01
LOW SKEW 1-TO-16
3.3V LVPECL FANOUT BUFFER
ORDERING INFORMATION
Part/Order Number
Marking
Package
Count
Temperature
ICS8530-01DY
ICS8530-01DY
48 Lead LQFP
250 per tray
0°C to 70°C
ICS8530-01DY T
ICS8530-01DY
48 Lead LQFP on Tape and Reel
2000
0°C to 70°C
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use
or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are
not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS
product for use in life support devices or critical medical instruments.
8530-01
www.icst.com
6
REV. A - OCTOBER 2, 2000