ICS8530 Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-16 DIFFERENTIAL-TO-2.5V LVPECL FANOUT BUFFER GENERAL DESCRIPTION FEATURES The ICS8530 is a low skew, 1-to-16 Differential,&6 to-2.5V LVPECL Fanout Buffer and a member of HiPerClockS™ the HiPerClockS™ family of High Performance Clock Solutions from ICS. The CLK, nCLK pair can accept most standard differential input levels. The high gain differential amplifier accepts peak-to-peak input voltages as small as 150mV, as long as the common mode voltage is within the specified minimum and maximum range. • 16 differential 2.5V LVPECL outputs Guaranteed output and part-to-part skew characteristics make the ICS8530 ideal for those clock distribution applications demanding well defined performance and repeatability. • Output skew: 50ps (maximum) • CLK, nCLK input pair • CLK, nCLK pair can accept the following differential input levels: LVDS, LVPECL, LVHSTL, SSTL, HCSL • Maximum output frequency up to 500MHz • Translates any single-ended input signal to 2.5V LVPECL levels with a resistor bias on nCLK input • Part-to-part skew: 250ps (maximum) • Propagation Delay: 2ns (maximum) • 3.3V core, 2.5V output operating supply • 0°C to 70°C ambient operating temperature • Industrial temperature information available upon request BLOCK DIAGRAM PIN ASSIGNMENT Q0 nQ0 Q15 nQ15 Q1 nQ1 Q14 nQ14 Q2 nQ2 Q13 nQ13 Q3 nQ3 Q12 nQ12 Q4 nQ4 Q11 nQ11 Q5 nQ5 Q10 nQ10 Q6 nQ6 Q9 nQ9 Q7 nQ7 Q8 nQ8 VCCO Q11 nQ11 Q10 nQ10 VEE Q9 nQ9 Q8 nQ8 VCCO VCC 48 47 46 45 44 43 42 41 40 39 38 37 1 36 2 35 3 34 4 33 5 32 6 31 7 30 8 29 9 28 10 27 11 26 12 25 13 14 15 16 17 18 19 20 21 22 23 24 ICS8530 CLK VCCO nQ0 Q0 nQ1 Q1 VEE nQ2 Q2 nQ3 Q3 VCCO VCCO nQ4 Q4 nQ5 Q5 VEE nQ6 Q6 nQ7 Q7 VCCO VCC ICS8530DY nCLK VCCO Q15 nQ15 Q14 nQ14 VEE Q13 nQ13 Q12 nQ12 VCCO CLK nCLK 48-Pin LQFP 7mm x 7mm x 1.4mm package body Y Package Top View www.icst.com/products/hiperclocks.html 1 REV. C AUGUST 7, 2001 ICS8530 Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-16 DIFFERENTIAL-TO-2.5V LVPECL FANOUT BUFFER TABLE 1. PIN DESCRIPTIONS Number 1, 11, 14, 24, 25, 35, 38, 48 2, 3 Name Type Description VCCO Power Output supply pins. Connect to 2.5V. Q11, nQ11 Output Differential output pair. LVPECL interface levels. 4, 5 Q10, nQ10 Output Differential output pair. LVPECL interface levels. 6, 19, 30, 43 VEE Power Negative supply pins. Connect to ground. Differential output pair. LVPECL interface levels. 7, 8 Q9, nQ9 Output 9, 10 Q8, nQ8 Output Differential output pair. LVPECL interface levels. 12, 13 VCC Power Positive supply pins. Connect to 3.3V. 15, 16 Q7, nQ7 Output Differential output pair. LVPECL interface levels. 17, 18 Q6, nQ6 Output Differential output pair. LVPECL interface levels. 20, 21 Q5, nQ5 Output Differential output pair. LVPECL interface levels.. 22, 23 Q4, nQ4 Output Differential output pair. LVPECL interface levels. 26, 27 28, 29 Q3, nQ3 Q2, nQ2 Output Output Differential output pair. LVPECL interface levels. Differential output pair. LVPECL interface levels. 36 37 39, 40 41, 42 44, 45 46, 47 NOTE: Pullup and CLK nCLK Q15, nQ15 Q14, nQ14 Q13, nQ13 Q12, nQ12 Pulldown refers Input Pulldown Non-inver ting differential clock input. Input Pullup Inver ting differential clock input. Output Differential output pair. LVPECL interface levels. Output Differential output pair. LVPECL interface levels. Output Differential output pair. LVPECL interface levels. Output Differential output pair. LVPECL interface levels. to internal input resistors. See Table 2, Pin Characteristics, for typical values. TABLE 2. PIN CHARACTERISTICS Symbol Parameter CIN Input Capacitance Test Conditions Minimum Typical CLK, nCLK Maximum Units 4 pF RPULLUP Input Pullup Resistor 51 KΩ RPULLDOWN Input Pulldown Resistor 51 KΩ TABLE 3. CLOCK INPUT FUNCTION TABLE Inputs CLK Outputs nCLK Q0 thru Q15 nQ0 thru nQ15 Input to Output Mode Polarity 0 1 LOW HIGH Differential to Differential Non Inver ting 1 0 HIGH LOW Differential to Differential Non Inver ting 0 Biased; NOTE 1 LOW HIGH Single Ended to Differential Non Inver ting 1 Biased; NOTE 1 HIGH LOW Single Ended to Differential Non Inver ting Biased; NOTE 1 0 HIGH LOW Single Ended to Differential Inver ting Biased; NOTE 1 1 LOW HIGH Single Ended to Differential Inver ting NOTE 1: Please refer to the Application Information section on page 7, Figure 8, which discusses wiring the differential input to accept single ended levels. ICS8530DY www.icst.com/products/hiperclocks.html 2 REV. C AUGUST 7, 2001 ICS8530 Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-16 DIFFERENTIAL-TO-2.5V LVPECL FANOUT BUFFER ABSOLUTE MAXIMUM RATINGS Supply Voltage, VCCx 4.6V Inputs, VI Outputs, VO Package Thermal Impedance, θJA Storage Temperature, TSTG -0.5V to VCC + 0.5V -0.5V to VCCO + 0.5V 47.9°C/W -65°C to 150°C Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VCC = 3.3V±5%, VCCO = 2.5V±5%, TA = 0°C TO 70°C Symbol Parameter Minimum Typical Maximum Units VCC Positive Supply Voltage Test Conditions 3.135 3.3 3.465 V VCCO Output Supply Voltage 2.375 2.5 2.625 V IEE Power Supply Current 115 mA Maximum Units TABLE 4B. DIFFERENTIAL DC CHARACTERISTICS, VCC = 3.3V±5%, VCCO = 2.5V±5%, TA = 0°C TO 70°C Symbol Parameter IIH Input High Current IIL Input Low Current Test Conditions Minimum Typical CLK VCC = VIN = 3.465V 150 µA nCLK VCC = VIN = 3.465V 5 µA CLK VCC = 3.465V, VIN = 0V -5 nCLK VCC = 3.465V, VIN = 0V -150 µA µA VPP Peak-to-Peak Input Voltage 0.15 Common Mode Input Voltage; VCMR 0.05 NOTE 1, 2 NOTE 1: For single ended applications, the maximum input voltage for CLK, nCLK is VCC + 0.3V. NOTE 2: Common mode voltage is defined as VIH. 1.3 V VCC - 0.85 V Maximum Units V TABLE 4C. LVPECL DC CHARACTERISTICS, VCC = 3.3V±5%, VCCO = 2.5V±5%, TA = 0°C TO 70°C Symbol Parameter Test Conditions Minimum Typical VOH Output High Voltage; NOTE 1 VCCO - 1.4 VCCO - 1.0 VOL Output Low Voltage; NOTE 1 VCCO - 2.0 VCCO - 1.7 V VSWING Peak-to-Peak Output Voltage Swing 0.55 0.93 V NOTE 1: Outputs terminated with 50Ω to VCCO-2V. ICS8530DY www.icst.com/products/hiperclocks.html 3 REV. C AUGUST 7, 2001 Integrated Circuit Systems, Inc. ICS8530 LOW SKEW, 1-TO-16 DIFFERENTIAL-TO-2.5V LVPECL FANOUT BUFFER TABLE 5. AC CHARACTERISTICS, VCC = 3.3V±5%, VCCO = 2.5V±5%, TA = 0°C TO 70°C Symbol Parameter fMAX Maximum Output Frequency tPD Propagation Delay; NOTE 1 tsk(o) Output Skew; NOTE 2, 4 tsk(pp) Par t-to-Par t Skew; NOTE 3, 4 Test Conditions Minimum ƒ≤ 500MHz Typical 1 26 Maximum Units 500 MHz 2 ns 50 ps 250 ps tR Output Rise Time 20% to 80% @ 50MHz 300 700 ps tF Output Fall Time 20% to 80% @ 50MHz 300 700 ps 53 % odc Output Duty Cycle 47 50 All parameters measured at 250MHz unless noted otherwise. NOTE 1: Measured from the differential input crossing point to the differential output crossing point. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential cross points. NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points. NOTE 4: This parameter is defined in accordance with JEDEC Standard 65. ICS8530DY www.icst.com/products/hiperclocks.html 4 REV. C AUGUST 7, 2001 ICS8530 Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-16 DIFFERENTIAL-TO-2.5V LVPECL FANOUT BUFFER PARAMETER MEASUREMENT INFORMATION VCCO VCC SCOPE Qx LVPECL VCC = 2.8V VCCO = 2V nQx VEE = -0.5V ± 0.135V FIGURE 1 - OUTPUT LOAD TEST CIRCUIT V CC CLK V Cross Points PP V CMR nCLK VEE FIGURE 2 - DIFFERENTIAL INPUT LEVEL Qx nQx Qy nQy tsk(o) FIGURE 3 - OUTPUT SKEW ICS8530DY www.icst.com/products/hiperclocks.html 5 REV. C AUGUST 7, 2001 ICS8530 Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-16 DIFFERENTIAL-TO-2.5V LVPECL FANOUT BUFFER Qx PART 1 nQx Qy PART 2 nQy tsk(pp) FIGURE 4 - PART-TO-PART SKEW 80% 80% V 20% SWING 20% Clock Inputs and Outputs t t R FIGURE 5 - INPUT AND OUTPUT RISE AND F FALL TIME CLK nCLK Q0 - Q15 nQ0 - nQ15 t PD FIGURE 6 - PROPAGATION DELAY CLK, Qx nCLK, nQx Pulse Width t t odc = t PERIOD PW PERIOD FIGURE 7 - odc & tPERIOD ICS8530DY www.icst.com/products/hiperclocks.html 6 REV. C AUGUST 7, 2001 ICS8530 Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-16 DIFFERENTIAL-TO-2.5V LVPECL FANOUT BUFFER APPLICATION INFORMATION WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS Figure 8 shows how the differential input can be wired to accept single ended levels. The reference voltage V_REF ~ VCC/2 is generated by the bias resistors R1, R2 and C1. This bias circuit should be located as close as possible to the input pin. The ratio of R1 and R2 might need to be adjusted to position the V_REF in the center of the input voltage swing. For example, if the input clock swing is only 2.5V and VCC = 3.3V, V_REF should be 1.25V and R2/R1 = 0.609. VCC R1 1K CLK_IN + V_REF C1 0.1uF R2 1K FIGURE 8 - SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT ICS8530DY www.icst.com/products/hiperclocks.html 7 REV. C AUGUST 7, 2001 ICS8530 Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-16 DIFFERENTIAL-TO-2.5V LVPECL FANOUT BUFFER POWER CONSIDERATIONS This section provides information on power dissipation and junction temperature for the ICS8530. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the ICS8530 is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VCC = 3.3V + 5% = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load. • • Power (core)MAX = VCC_MAX * IEE_MAX = 3.465V * 115mA = 398.5mW Power (outputs)MAX = 30.2mW/Loaded Output pair If all outputs are loaded, the total power is 16 * 30.2mW = 483.2mW Total Power_MAX (3.465V, with all outputs switching) = 398.5mW + 483.2mW = 881.7mW 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockSTM devices is 125°C. The equation for Tj is as follows: Tj = θJA * Pd_total + TA Tj = Junction Temperature θJA = junction-to-ambient thermal resistance Pd_total = Total device power dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used . Assuming a moderate air low of 200 linear feet per minute and a multi-layer board, the appropriate value is 42.1°C/W per Table 6 below. Therefore, Tj for an ambient temperature of 70°C with all outputs switching is: 70°C + 0.881W * 42.1°C/W = 107.1°C. This is well below the limit of 125°C This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow, and the type of board (single layer or multi-layer). Table 6. Thermal Resistance qJA for 48-pin LQFP, Forced Convection qJA by Velocity (Linear Feet per Minute) 0 Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 67.8°C/W 47.9°C/W 200 55.9°C/W 42.1°C/W 500 50.1°C/W 39.4°C/W NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs. ICS8530DY www.icst.com/products/hiperclocks.html 8 REV. C AUGUST 7, 2001 ICS8530 Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-16 DIFFERENTIAL-TO-2.5V LVPECL FANOUT BUFFER 3. Calculations and Equations. The purpose of this section is to derive the power dissipated into the load. LVPECL output driver circuit and termination are shown in Figure 9. VCCO Q1 VOUT RL 50 VCCO - 2V FIGURE 9 - LVPECL DRIVER CIRCUIT AND TERMINATION To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a termination voltage of V - 2V. CC Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low. Pd_H = [(V – (V OH_MAX Pd_L = [(V – (V OL_MAX • - 2V))/R ]*(V CC_MAX L - 2V))/R ]*(V CC_MAX L For logic high, V -V – 1.0V CC_MAX = 2.625, this results in V CC_MAX • ) OL_MAX =V OH_MAX = 1.625V OH_MAX For logic low, V OUT Using V =V OL_MAX =V – 1.7V CC_MAX = 2.625, this results in V CC_MAX ) OH_MAX CC_MAX =V OUT Using V -V CC_MAX = 0.925V OL_MAX Pd_H = [(1.625V - (2.625V - 2V))/50 Ω]*(1V) = 20mW Pd_L = [(0.925V - (2.625V - 2V))/50 Ω]*(1.7) = 10.2mW Total Power Dissipation per output pair = Pd_H + Pd_L = 30.2mW ICS8530DY www.icst.com/products/hiperclocks.html 9 REV. C AUGUST 7, 2001 ICS8530 Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-16 DIFFERENTIAL-TO-2.5V LVPECL FANOUT BUFFER RELIABILITY INFORMATION TABLE 7. θJAVS. AIR FLOW TABLE qJA by Velocity (Linear Feet per Minute) 0 Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 67.8°C/W 47.9°C/W 200 500 55.9°C/W 42.1°C/W 50.1°C/W 39.4°C/W NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs. TRANSISTOR COUNT The transistor count for ICS8530 is: 930 ICS8530DY www.icst.com/products/hiperclocks.html 10 REV. C AUGUST 7, 2001 ICS8530 Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-16 DIFFERENTIAL-TO-2.5V LVPECL FANOUT BUFFER PACKAGE OUTLINE - Y SUFFIX TABLE 8. PACKAGE DIMENSIONS JEDEC VARIATION ALL DIMENSIONS IN MILLIMETERS SYMBOL BBC MINIMUM NOMINAL MAXIMUM 48 N A -- -- 1.60 A1 0.05 -- 0.15 A2 1.35 1.40 1.45 b 0.17 0.22 0.27 c 0.09 -- 0.20 D 9.00 BASIC D1 7.00 BASIC D2 5.50 Ref. E 9.00 BASIC E1 7.00 BASIC E2 5.50 Ref. 0.50 BASIC e L 0.45 0.60 0.75 q 0° -- 7° ccc -- -- 0.08 Reference Document: JEDEC Publication 95, MS-026 ICS8530DY www.icst.com/products/hiperclocks.html 11 REV. C AUGUST 7, 2001 ICS8530 Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-16 DIFFERENTIAL-TO-2.5V LVPECL FANOUT BUFFER TABLE 9. ORDERING INFORMATION Part/Order Number ICS8530DY ICS8530DYT Marking ICS8530DY ICS8530DY Package 48 Lead LQFP 48 Lead LQFP on Tape and Reel Count 250 per tray 1000 Temperature 0°C to 70°C 0°C to 70°C While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. ICS8530DY www.icst.com/products/hiperclocks.html 12 REV. C AUGUST 7, 2001