ICS ICS8701-01Y

ICS8701-01
LOW SKEW ¸1, ¸2 CLOCK
GENERATOR W/POLARITY CONTROL
Integrated
Circuit
Systems, Inc.
GENERAL DESCRIPTION
FEATURES
The ICS8701-01 is a low skew, ÷1, ÷2 Clock
Generator and a member of the HiPerClockS™
HiPerClockS™ family of High Performance Clock Solutions
from ICS. The low impedance LVCMOS outputs
are designed to drive 50Ω series or parallel terminated transmission lines. The effective fanout can be increased from 20 to 40 by utilizing the ability of the outputs to
drive two series terminated lines.
• 20 LVCMOS outputs, 7Ω typical output impedance
,&6
• Output frequency up to 250 MHz
• 250ps bank skew, 300ps output skew, 350ps multiple
frequency skew, 700ps part-to-part skew
• Selectable inverting and non-inverting outputs
• LVCMOS / LVTTL clock input
The divide select inputs, DIV_SELx, control the output frequency of each bank. The outputs can be utilized in the ÷1,
÷2 or a combination of ÷1 and ÷2 modes. The master reset/
output enable input, nMR/OE, resets the internal dividers and
controls the active and high impedance states of all outputs.
The output polarity inputs, INV0:1, control the polarity (inverting or non-inverting) of the outputs of each bank. Outputs
QA0-QA4 are inverting for every combination of the INV0:1
input. The timing relationship between the inverting and noninverting outputs at different frequencies is shown in the Timing Diagrams.
• LVCMOS / LVTTL control inputs
• Bank enable logic allows unused banks to be disabled
in reduced fanout applications
• 3.3V or mixed 3.3V input, 2.5V output operating
supply modes
• 48 lead low-profile QFP (LQFP), 7mm x 7mm x 1.4mm
package body, 0.5mm package lead pitch
• 0°C to 70°C ambient operating temperature
• Other divide values available on request
The ICS8701-01 is characterized at 3.3V and mixed 3.3V input supply, and 2.5V output supply operating modes. Guaranteed bank, output and part-to-part skew characteristics
make the ICS8701-01 ideal for those clock distribution applications demanding well defined performance and repeatability.
BLOCK DIAGRAM
÷1
1
÷2
0
GND
QB2
GND
QB3
VDDOB
QB4
QC0
VDDOC
QC1
GND
QC2
GND
LVCMOS_CLK
PIN A SSIGNMENT
QAO - QA4
DIV_SELA
QC3
VDDOC
QC4
QD0
VDDOD
QD1
GND
QD2
GND
QD3
VDDOD
QD4
1
0
QB0 - QB4
DIV_SELB
1
0
QC0 - QC4
DIV_SELC
1
0
QD0 - QD4
nMR/OE
INV0
INV1
8701-01
ICS8701-01
QB1
VDDOB
QB0
QA4
VDDOA
QA3
GND
QA2
GND
QA1
VDDOA
QA0
DIV_SELA
DIV_SELB
LVCMOS_CLK
GND
VDDI
INV0
GND
INV1
VDDI
nMR/OE
DIV_SELC
DIV_SELD
DIV_SELD
48 47 46 45 44 43 42 41 40 39 38 37
1
36
2
35
3
34
4
33
5
32
6
31
7
30
8
29
9
28
10
27
11
26
12
25
13 14 15 16 17 18 19 20 21 22 23 24
Output
Polarity
Control
48-Pin LQFP
Y Package
Top View
www.icst.com
1
REV. A - AUGUST 28, 2000
ICS8701-01
LOW SKEW ¸1, ¸2 CLOCK
GENERATOR W/POLARITY CONTROL
Integrated
Circuit
Systems, Inc.
TABLE 1. PIN DESCRIPTIONS
Number
Name
Ty pe
Description
2, 44
VDDOC
Pow er
Output Bank C pow er supply. Connect to 3.3V or 2.5V.
5, 11
VDDOD
Pow er
Output Bank D pow er supply. Connect to 3.3V or 2.5V.
26, 32
VDDOA
Pow er
Output Bank C pow er supply. Connect to 3.3V or 2.5V.
35, 41
VDDOB
Pow er
Output Bank B pow er supply. Connect to 3.3V or 2.5V.
GND
Pow er
Ground. Connect to ground.
VDDI
QA0, QA1, QA2,
QA3, QA4
QB0, QB1, QB2,
QB3, QB4
QC0, QC1, QC2,
QC3, QC4
QD0, QD1, QD2,
QD3, QD4
LVCMOS_CLK
Pow er
Input pow er supply. Connect to 3.3V.
Output
Bank A outputs. LVCMOS interface levels. 7Ω typical output impedance.
Output
Bank B outputs. LVCMOS interface levels. 7Ω typical output impedance.
Output
Bank C outputs. LVCMOS interface levels. 7Ω typical output impedance.
Output
Bank D outputs. LVCMOS interface levels. 7Ω typical output impedance.
7, 9, 18,
21, 28, 30,
37, 39, 46,
48
16, 20
25, 27, 29,
31, 33
34, 36, 38,
40, 42
43, 45, 47,
1, 3
4, 6, 8,
10, 12
22
Input
Pullup
Clock input. LVCMOS interface levels.
13
DIV_SELD
Input
Pullup
Controls frequency division for bank D outputs. LVCMOS interface levels.
14
DIV_SELC
Input
Pullup
Controls frequency division for bank C outputs. LVCMOS interface levels.
23
DIV_SELB
Input
Pullup
Controls frequency division for bank B outputs. LVCMOS interface levels.
24
DIV_SELA
Input
Pullup
Controls frequency division for bank A outputs. LVCMOS interface levels.
17, 19
INV1, INV0
Input
Pullup
15
nMR/OE
Input
Pullup
Determines polarity of outputs by banks. LVCMOS interface levels.
Master reset and output enable. Resets non-inverting outputs to LOW. Sets
inverting outputs to HIGH. Enables and disables all outputs. LVCMOS interface
levels.
TABLE 2. PIN CHARACTERISTICS
Sy mbol
Parameter
Test Conditions
CIN
Input Capacitance
RPULLUP
Input Pullup Resistor
CPD
Pow er Dissipation Capacitance
(per output)
ROUT
Output Impedance
Minimum
Ty pical
Maximum
Units
pF
51
KΩ
VDDI, VDDOx = 3.465V
pF
VDDI = 3.465V, VDDOx = 2.625V
pF
Ω
7
TABLE 3. FUNCTION TABLE
Inputs
Outputs
nMR/OE
DIV_SELx
INV1
INV0
BANK A
BANK B
BANK C
BANK D
0
X
X
X
Hi Z
Hi Z
Hi Z
Hi Z
zero
1
0
0
0
Inverting
Non-inverting
Non-inverting
Non-inverting
fIN/2
8701-01
Qx frequency
1
0
0
1
Inverting
Inverting
Non-inverting
Non-inverting
fIN/2
1
0
1
0
Inverting
Inverting
Inverting
Non-inverting
fIN/2
1
0
1
1
Inverting
Inverting
Inverting
Inverting
fIN/2
1
1
0
0
Inverting
Non-inverting
Non-inverting
Non-inverting
fIN
1
1
0
1
Inverting
Inverting
Non-inverting
Non-inverting
fIN
1
1
1
0
Inverting
Inverting
Inverting
Non-inverting
fIN
1
1
1
1
Inverting
Inverting
Inverting
Inverting
fIN
www.icst.com
2
REV. A - AUGUST 28, 2000
ICS8701-01
LOW SKEW ¸1, ¸2 CLOCK
GENERATOR W/POLARITY CONTROL
Integrated
Circuit
Systems, Inc.
A BSOLUTE MAXIMUM RATINGS
Supply Voltage
4.6V
Inputs
Outputs
Ambient Operating Temperature
Storage Temperature
-0.5V to VDDI + 0.5V
-0.5V to VDDOx + 0.5V
0°C to 70°C
-65°C to 150°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress
specifications only and functional operation of product at these condition or any conditions beyond those listed in the DC Electrical
Characteristics or AC Electrical Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may
affect product reliability.
TABLE 4A. DC ELECTRICAL CHARACTERISTICS, VDDI = VDDOX = 3.3V±5%, TA = 0°C TO 70°C
Sy mbol
Parameter
VDDI
VDDOx
VIH
Input High Voltage
Test Conditions
Minimum
Ty pical
Maximum
Units
Input Pow er Supply Voltage
3.135
3.3
3.465
V
Output Pow er Supply Voltage
3.135
3.3
3.465
V
2
3.765
V
2
3.765
V
-0.3
0.8
V
-0.3
1.3
V
5
µA
70
mA
All except LVCMOS_CLK
VDDI = 3.465V
LVCMOS_CLK
All except LVCMOS_CLK
VIL
Input Low Voltage
VDDI = 3.135V
IIH
Input High Current
VDDI = VIN = 3.465V
VDDI = VIN = 0V
LVCMOS_CLK
IIL
Input Low Current
IDD
Quiescent Pow er Supply Current
VOH
Output High Voltage
VOL
Output Low Voltage
VDDOx = 3.135V
IOH = -36mA
VDDOx =3.135V
IOL = 36mA
-150
µA
2.6
TABLE 5A. AC ELECTRICAL CHARACTERISTICS, VDDI = VDDOX = 3.3V±5%, TA=0°C TO 70°C
Test Conditions
Minimum
0MHZ < f ≤ 200MHz
2.5
0MHZ < f ≤ 200MHz
2.5
V
Ty pical
0.5
V
Maximum
Units
250
MHz
3.5
ns
Sy mbol
Parameter
fMAX
Maximum Input Frequency
tpLH
Propagation Delay, Low -to-High
tpHL
Propagation Delay, High-to-Low
3.5
ns
tsk(b)
Bank Skew ; NOTE 2
Measured on falling edge at VDDOx/2
250
ps
tsk(o)
Output Skew ; NOTE 3
Measured on falling edge at VDDOx/2
300
ps
tsk(ω)
Multiple Frequency Skew ; NOTE 4
Measured on falling edge at VDDOx/2
350
ps
tsk(pp)
Part to Part Skew ; NOTE 5
Measured on falling edge at VDDOx/2
700
ps
tR
Output Rise Time; NOTE 6
150
700
ps
tF
Output Fall Time; NOTE 6
150
700
ps
tPW
Output Pulse Width
tEN
Output Enable Time; NOTE 6
0MHZ < f < 200MHz
f = 200MHz
tCY CLE/2
- 0.5
2
tCY CLE/2
2.5
tCY CLE/2
+ 0.5
3
ns
6
ns
ns
tDIS
Output Disable Time; NOTE 6
6
ns
NOTE 1: All parameters measured at 200MHz unless noted otherw ise. All outputs terminated w ith 50Ω to VDDOx/2.
NOTE 2: Defined as skew w ithin a bank of outputs at the same supply voltages and w ith equal load conditions.
NOTE 3: Defined as skew across banks of outputs sw itching in the same direction at the same supply voltages and w ith equal load
conditions.
NOTE 4: Defined as skew across banks of outputs sw itching in the same direction operating at different frequencies w ith the same supply
voltages and equal load conditions.
NOTE 5: Defined as the skew at different outputs sw itching in the same direction on different devices operating at the same supply voltages
and w ith equal load conditions.
NOTE 6: These parameters are guaranteed by characterization. Not tested in production.
8701-01
www.icst.com
3
REV. A - AUGUST 28, 2000
ICS8701-01
LOW SKEW ¸1, ¸2 CLOCK
GENERATOR W/POLARITY CONTROL
Integrated
Circuit
Systems, Inc.
TABLE 4B. DC ELECTRICAL CHARACTERISTICS, VDDI = 3.3V±5%, VDDOX = 2.5V±5%, TA = 0°C TO 70°C
Sy mbol
Parameter
Minimum
Ty pical
Maximum
Units
VDDI
Input Pow er Supply Voltage
Test Conditions
3.135
3.3
3.465
V
VDDOx
Output Pow er Supply Voltage
2.375
2.5
All except LVCMOS_CLK
VIH
Input High Voltage
VDDI = 3.465V
VIL
Input Low Voltage
IIH
Input High Current
VDDI = VIN = 3.465V
VDDI = VIN = 0V
LVCMOS_CLK
All except LVCMOS_CLK
VDDI = 3.135V
LVCMOS_CLK
IIL
Input Low Current
IDD
Quiescent Pow er Supply Current
VOH
Output High Voltage
VOL
Output Low Voltage
VDDI = 3.135V
VDDOx = 2.375V
IOH = -27mA
VDDI =3.135V
VDDOx = 2.375V
IOL = 27mA
2.625
V
2
3.765
V
2
3.765
V
-0.3
0.8
V
-0.3
1.3
V
5
µA
70
mA
-150
µA
1.8
V
0.5
V
Maximum
Units
TABLE 5B. AC ELECTRICAL CHARACTERISTICS, VD DI = 3.3V±5%, VDDO = 2.5V±5%, T A = 0°C TO 70°C
Sy mbol
Parameter
Test Conditions
Minimum
fMAX
Maximum Input Frequency
tpLH
Ty pical
250
MHz
Propagation Delay, Low -to-High
0MHZ < f ≤ 200MHz
2.5
3.5
ns
tpHL
Propagation Delay, High-to-Low
0MHZ < f ≤ 200MHz
2.5
3.5
ns
tsk(b)
Bank Skew ; NOTE 2
Measured on falling edge at VDDOx/2
300
ps
tsk(o)
Output Skew ; NOTE 3
Measured on falling edge at VDDOx/2
300
ps
tsk(ω)
Multiple Frequency Skew ; NOTE 4
Measured on falling edge at VDDOx/2
350
ps
tsk(pp)
Part to Part Skew ; NOTE 5
Measured on falling edge at VDDOx/2
700
ps
tR
Output Rise Time; NOTE 6
720
ps
tF
Output Fall Time; NOTE 6
150
720
ps
tCY CLE/2
- 0.5
2
tCY CLE/2
+ 0.5
3
tPW
Output Pulse Width
tEN
Output Enable Time; NOTE 6
150
0MHZ < f < 200MHz
f = 200MHz
tCY CLE/2
2.5
6
ns
ns
ns
tDIS
Output Disable Time; NOTE 6
6
ns
NOTE 1: All parameters measured at 200MHz unless noted otherw ise. All outputs terminated w ith 50Ω to VDDOx/2.
NOTE 2: Defined as skew w ithin a bank of outputs at the same supply voltages and w ith equal load conditions.
NOTE 3: Defined as skew across banks of outputs sw itching in the same direction at the same supply voltages and w ith equal load
conditions.
NOTE 4: Defined as skew across banks of outputs sw itching in the same direction operating at different frequency w ith the same supply
voltages and equal load conditions.
NOTE 5: Defined as the skew at different outputs sw itching in the same direction on different devices operating at the same supply voltages
and w ith equal load conditions.
NOTE 6: These parameters are guaranteed by characterization. Not tested in production.
8701-01
www.icst.com
4
REV. A - AUGUST 28, 2000
ICS8701-01
LOW SKEW ¸1, ¸2 CLOCK
GENERATOR W/POLARITY CONTROL
Integrated
Circuit
Systems, Inc.
FIGURE 1A, 1B - TIMING DIAGRAMS
LVCMOS_CLK
QA, ÷1, INV
QB, ÷2, INV
QC, ÷2, NINV
QD, ÷1, NINV
FIGURE 1A - ACTIVE, ÷1, ÷2, INVERTING AND NON-INVERTING
nMR/OE
LVCMOS_CLK
QA, ÷1, INV
QB, ÷2, INV
QC, ÷2, NINV
QD, ÷1, NINV
High Impedance
Active
FIGURE 1B - RESET TO ACTIVE, ÷ 1, ÷ 2, INVERTING AND NON-INVERTING
8701-01
www.icst.com
5
REV. A - AUGUST 28, 2000
ICS8701-01
LOW SKEW ¸1, ¸2 CLOCK
GENERATOR W/POLARITY CONTROL
Integrated
Circuit
Systems, Inc.
FIGURE 2A, 2B - TIMING WAVEFORMS
CLK
3.3V
VDDI/2
VDDI/2
0V
tPHL
tPLH
Q
VDDI/2
VDDI/2
FIGURE 2A - PROPAGATION DELAYS
fin = 200MHz, Vamp = 3.3V, tr = tf = 600ps
nMR/OE
3.3V
VDDI/2
VDDI/2
0V
tPHZ
Q
VOH
tPZH
VOH - 300mV
VDDO/2
tPLZ
tPZL
VDDO/2
Q
VOL
VOL + 300mV
FIGURE 2B - DISABLE AND ENABLE TIMES
fin = 10MHz, Vamp = 3.3V, tr = tf = 600ps
8701-01
www.icst.com
6
REV. A - AUGUST 28, 2000
ICS8701-01
LOW SKEW ¸1, ¸2 CLOCK
GENERATOR W/POLARITY CONTROL
Integrated
Circuit
Systems, Inc.
FIGURE 3A, 3B- SKEW DEFINITIONS & WAVEFORMS
Bank Skew - Skew within a bank of outputs at the same supply voltages and with equal load conditions.
CLK
VDDO/2
VDDO/2
tsk(b)
tsk(b)
VDDO/2
VDDO/2
○
○
○
○
○
○
○
○
Qx0
Qx4
FIGURE 3A - BANK SKEW
fin = 200MHz, Vamp = 3.3V, tr = tf = 200ps
Output Skew - Skew across banks of outputs switching in the same direction at the same supply voltages and with equal load
conditions.
CLK
VDDO/2
VDDO/2
QA0 - QA4
tsk(o)
tsk(o)
VDDO/2
VDDO/2
QB0 - QB4
QC0 - QC4
QD0 - QD4
8701-01
FIGURE 3B - INVERTING OUTPUT SKEW
fin = 200MHz, Vamp = 3.3V, tr = tf = 200ps
www.icst.com
7
REV. A - AUGUST 28, 2000
ICS8701-01
LOW SKEW ¸1, ¸2 CLOCK
GENERATOR W/POLARITY CONTROL
Integrated
Circuit
Systems, Inc.
FIGURE 3C, 3D- SKEW DEFINITIONS & WAVEFORMS
Multiple Frequency Skew - Skew across banks of outputs switching in the same direction operating at different frequencies with
the same supply voltages and equal load conditions.
CLK
QA0 - QA4,
QB0 - QB4,
QC0 - QC4,
or
QD0 - QD4
VDDO/2
in ÷1, inverting
tsk(w)
QA0 - QA4,
QB0 - QB4,
QC0 - QC4,
or
QD0 - QD4
in ÷2, inverting
VDDO/2
FIGURE 3C - MULTIPLE FREQUENCY SKEW
fin = 200MHz, Vamp = 3.3V, tr = tf = 200ps
Part to Part Skew - Skew at different outputs switching in the same direction on different devices operating at the same supply
voltages and with equal load conditions.
CLK
PART 1 QA0 - QA4
QB0 - QB4
QC0 - QC4
QD0 - QD4
inverting
VDDO/2
VDDO/2
tsk(p)
PART 2 QA0 - QA4
QB0 - QB4
QC0 - QC4
QD0 - QD4
inverting
tsk(p)
VDDO/2
VDDO/2
FIGURE 3B - OUTPUT SKEW
fin = 200MHz, Vamp = 3.3V, tr = tf = 200ps
8701-01
www.icst.com
8
REV. A - AUGUST 28, 2000
ICS8701-01
LOW SKEW ¸1, ¸2 CLOCK
GENERATOR W/POLARITY CONTROL
Integrated
Circuit
Systems, Inc.
PACKAGE OUTLINE AND DIMENSIONS - Y SUFFIX
e /2
NOTE 4
D
NOTE 5, 7
D1
D/2
NOTE 3
-D-
-A, B, OR -D-
D1/2
b
NOTE 3
-B-
NOTE 3
-A-
E1
-A, B, OR -D-
N
O
T
E
4
NOTES:
1. ALL DIMENSIONS AND TOLERANCING CONFORM TO ANSI
Y14.5-1982
2. DATUM PLANE -H- LOCATED AT MOLD PARTING LINE AND
COINCIDENT WITH LEAD, WHERE LEAD EXITS PLASTIC BODY
AT BOTTOM OF PARTING LINE.
3. DATUMS A-B AND -D- TO BE DETERMINED AT CENTERLINE
BETWEEN LEADS WHERE LEADS EXIT PLASTIC AT DATUM
PLANE -H- .
4. TO BE DETERMINED AT SEATING PLACE -C- .
5. DIMENSIONS D1 AND E1 DO NOT INCLUDE MOLD
PROTRUSION.
6. “N” IS THE TOTAL NUMBER OF TERMINALS.
7. THESE DIMENSIONS TO BE DETEREMINED AT DATUM PLANE
-H-.
8. PACKAGE TOP DIMENSIONS ARE SMALLER THAN BOTTOM
DIMENSIONS AND TOP OF PACKAGE WILL NOT OVERHANG
BOTTOM OF PACKAGE.
9. DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSION.
ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08mm TOTAL
IN EXCESS OF THE b DIMENSION AT MAXIMUM MATERIAL
CONDITION.
10. CONTROLLING DIMENSION: MILLIMETER.
11. THIS OUTLINE CONFORMS TO JEDEC PUBLIBCATION 95
REGISTRATION MS-026, VARIATION BBC.
12. A1 IS DEFINED AS THE DISTANCE FROM THE SEATING PLANE
TO THE LOWEST POINT OF THE PACKAGE.
E/2
N/4 T IPS
0.20 C A-B D
4X
E
N
O
T
E
5,
7
e
E1/2
SEE DETAIL “A”
8 PLACES
11 / 13°
A
-H- NOT E 2 / / 0.10 C
ccc
-CSEE DETAIL “B”
NOTE 9
ddd M C A-B S D S
0.09 / 0.20
S
Y
M
B
O
L
WIT H LEAD FINISH
b
0.09 / 0.16
JEDEC VARIATION
ALL DIMENSIONS IN MILLIMETERS
BBC
MIN.
NOM.
A
b1
BASE METAL
0° MIN.
- 0.05 S
A2
0.08/0.20 R.
DATUM
PLANE
-H-
0.05
A2
1.35
0.08
R. MIN.
0.20 MIN.
L
1.00 REF.
8701-01
www.icst.com
9
12
1.45
D
9.00 BSC.
4
7.00 BSC.
7, 8
E
9.00 BSC.
4
E1
7.00 BSC.
7, 8
0.45
0.60
0.75
48
N
0° - 7 °
0.15
1.40
D1
e
A1
MAX.
1.60
A1
L
0.25
GAUGE PLANE
N
O
T
E
0.5 BSC.
b
0.17
0.22
0.27
b1
0.17
0.20
0.23
ccc
0.08
ddd
0.08
9
REV. A - AUGUST 28, 2000
ICS8701-01
LOW SKEW ¸1, ¸2 CLOCK
GENERATOR W/POLARITY CONTROL
Integrated
Circuit
Systems, Inc.
ORDERING INFORMATION
Part/Order Number
Marking
Package
Count
Temperature
ICS8701-01Y
ICS8701-01
48 Lead LQFP
250 per tray
0°C to 70°C
ICS8701-01Y T
ICS8701-01
48 Lead LQFP on Tape and Reel
2000
0°C to 70°C
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or
for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal
commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use
in life support devices or critical medical instruments.
8701-01
www.icst.com
10
REV. A - AUGUST 28, 2000