IDT74ALVC32 3.3V CMOS QUADRUPLE 2-INPUT POSITIVE-OR GATE INDUSTRIAL TEMPERATURE RANGE IDT74ALVC32 3.3V CMOS QUADRUPLE 2-INPUT POSITIVE-OR GATE DESCRIPTION: FEATURES: – – – – – – – – This quadruple 2-input positive-OR gate is built using advanced dual metal CMOS technology. The ALVC32 performs the Boolean function Y = A • B or Y = A + B in positive logic. 0.5 MICRON CMOS Technology ESD > 2000V per MIL-STD-883, Method 3015; > 200V using machine model (C = 200pF, R = 0) VCC = 3.3V ± 0.3V, Normal Range VCC = 2.7V to 3.6V, Extended Range VCC = 2.5V ± 0.2V CMOS power levels (0.4µ W typ. static) Rail-to-Rail output swing for increased noise margin Available in SOIC, SSOP and TSSOP packages The ALVC32 has been designed with a ±24mA output driver. This driver is capable of driving a moderate to heavy load while maintaining speed performance. APPLICATIONS: Drive Features for ALVC32: – High Output Drivers: ±24mA – Suitable for heavy loads • 3.3V High Speed Systems • 3.3V and lower voltage computing systems FUNCTIONAL BLOCK DIAGRAM PIN CONFIGURATION A Y B 1A 1 14 V CC 1B 2 13 4B 1Y 3 4A 2A 4 12 SO14-1 SO14-2 11 SO14-3 2B 5 10 3B 2Y 6 9 3A GN D 7 8 3Y 4Y SOIC/ SSOP/ TSSOP TOP VIEW FUNCTION TABLE PIN DESCRIPTION Pin Names xA, xB xY (each gate) Inputs (1) Data Inputs xA xB Output xY Data Outputs H X H X H H L L L Description NOTE: 1. H = HIGH Voltage Level L = LOW Voltage Level X = Don't Care INDUSTRIAL TEMPERATURE RANGE SEPTEMBER 2000 1 c 1999 Integrated Device Technology, Inc. DSC-4638/- IDT74ALVC32 3.3V CMOS QUADRUPLE 2-INPUT POSITIVE-OR GATE INDUSTRIAL TEMPERATURE RANGE ABSOLUTE MAXIMUM RATINGS (1) Symbol CAPACITANCE (TA = +25°C, f = 1.0MHz) V Symbol CIN Parameter(1) Input Capacitance Conditions VIN = 0V V COUT Output Capacitance VOUT = 0V 7 9 pF CI/O I/O Port Capacitance VIN = 0V 7 9 pF Description Max. Unit VTERM(2) Terminal Voltage with Respect to GND – 0.5 to + 4.6 VTERM(3) Terminal Voltage with Respect to GND – 0.5 to VCC + 0.5 TSTG Storage Temperature – 65 to + 150 °C IOUT DC Output Current – 50 to + 50 mA IIK ± 50 mA IOK Continuous Clamp Current, VI < 0 or VI > VCC Continuous Clamp Current, VO < 0 – 50 mA ICC Continuous Current through each ±100 mA ISS VCC or GND Typ. 5 Max. 7 Unit pF ALVC QUAD Link NOTE: 1. As applicable to the device type. ALVC QUAD Link NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. VCC terminals. 3. All terminals except VCC. DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE Following Conditions Apply Unless Otherwise Specified: Operating Condition: TA = −40°C to +85°C Min. 1.7 Typ.(1) VCC = 2.7V to 3.6V 2 — — VCC = 2.3V to 2.7V — — 0.7 — — 0.8 Symbol VIH Parameter Input HIGH Voltage Level Test Conditions VCC = 2.3V to 2.7V VIL Input LOW Voltage Level VCC = 2.7V to 3.6V — Max. — Unit V V IIH Input HIGH Current VCC = 3.6V VI = VCC — — ±5 IIL Input LOW Current VCC = 3.6V VI = GND — — ±5 VIK Clamp Diode Voltage VCC = 2.3V, IIN = – 18mA — – 0.7 – 1.2 V VH Input Hysteresis VCC = 3.3V — 100 — mV ICCL ICCH ∆ICC Quiescent Power Supply Current VCC = 3.6V VIN = GND or VCC One input at VCC − 0.6V, other inputs at VCC or GND — 0.1 10 µA — — 750 µA Quiescent Power Supply Current Variation ALVC QUAD Link NOTE: 1. Typical values are at VCC = 3.3V, +25°C ambient. c µA 2 IDT74ALVC32 3.3V CMOS QUADRUPLE 2-INPUT POSITIVE-OR GATE INDUSTRIAL TEMPERATURE RANGE OUTPUT DRIVE CHARACTERISTICS Symbol VOH Parameter Output HIGH Voltage VCC Test Conditions(1) = 2.3V to 3.6V IOH = – 0.1mA IOH = – 6mA 2 — VCC = 2.3V IOH = – 12mA 1.7 — 2.2 — VCC = 3.0V Output LOW Voltage Max. — VCC = 2.3V VCC = 2.7V VOL Min. VCC – 0.2 2.4 — VCC = 3.0V IOH = – 24mA 2 — VCC = 2.3V to 3.6V IOL = 0.1mA — 0.2 VCC = 2.3V IOL = 6mA — 0.4 IOL = 12mA — 0.7 VCC = 2.7V IOL = 12mA — 0.4 VCC = 3.0V IOL = 24mA — 0.55 Unit V V ALVC QUAD Link NOTE: 1. VIH and VIL must be within the min. or max. range shown in the DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE table for the appropriate VCC range. TA = – 40°C to + 85°C. OPERATING CHARACTERISTICS, TA = 25oC Symbol CPD Parameter Power Dissipation Capacitance per gate SWITCHING CHARACTERISTICS VCC = 2.5V ± 0.2V VCC = 3.3V ± 0.3V Test Conditions Typical Typical Unit CL = 0pF, f = 10Mhz 24 26 pF (1) VCC = 2.5V ± 0.2V Symbol tPLH tPHL Parameter Propagation Delay xA or xB to xY Min. 1 Max. 3.1 NOTE: 1. See test circuits and waveforms. TA = – 40°C to + 85°C. 3 VCC = 2.7V Min. 1 Max. 3.4 VCC = 3.3V ± 0.3V Min. 1 Max. 3.3 Unit ns IDT74ALVC32 3.3V CMOS QUADRUPLE 2-INPUT POSITIVE-OR GATE INDUSTRIAL TEMPERATURE RANGE TEST CIRCUITS AND WAVEFORMS TEST CONDITIONS PROPAGATION DELAY Symbol VLOAD VCC(1)= 3.3V ± 0.3V VCC(1) = 2.7V 6 6 VIH 2.7 2.7 Vcc V SAME PHASE INPUT TRANSITION VT 1.5 1.5 Vcc / 2 V OUTPUT VLZ 300 300 150 mV VHZ 300 300 150 mV CL 50 VCC(2)= 2.5V ± 0.2V Unit 2 x Vcc V 50 30 tPLH tPHL tPLH tPHL V IH VT 0V V OH VT V OL V IH VT 0V OPPOSITE PHASE INPUT TRANSITION pF ALVC QUAD Link ALVC Link TEST CIRCUITS FOR ALL OUTPUTS ENABLE AND DISABLE TIMES V LOAD V CC 500 Ω (1, 2) V IN Pulse Generator CONTROL INPUT GND tPZL V OUT D.U.T. OUTPUT SW ITCH NORMALLY CLOSED LOW tPZH OUTPUT SW ITCH NORMALLY OPEN HIGH 500 Ω RT CL ALVC Link DEFINITIONS: CL= Load capacitance: includes jig and probe capacitance. RT = Termination resistance: should be equal to ZOUT of the Pulse Generator. NOTES: 1. Pulse Generator for All Pulses: Rate ≤ 10MHz; tF ≤ 2.5ns; tR ≤ 2.5ns. 2. Pulse Generator for All Pulses: Rate ≤ 10MHz; tF ≤ 2ns; tR ≤ 2ns. V OL + V LZ V OL tPHZ V OH V OH - V HZ VT 0V 0V t SU V IH VT 0V V IH VT 0V V IH VT 0V V IH VT 0V tH tREM ASYNCHRONOUS CONTROL GND SYNCHRONOUS CONTROL Open tSU tH ALVC Link OUTPUT SKEW - TSK (x) V IH VT 0V tPHL1 PULSE WIDTH V OH tSK (x) V LOAD/2 VT TIMING INPUT ALVC QUAD Link OUTPUT 1 V LOAD/2 SET-UP, HOLD, AND RELEASE TIMES Switch VLOAD tPLH1 0V NOTE: 1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH. DATA INPUT Test Open Drain Disable Low Enable Low Disable High Enable High All Other tests tPLZ V IH VT ALVC Link SWITCH POSITION INPUT DISABLE ENABLE Open tSK (x) LOW-HIGH-LOW PULSE VT V OL tW V OH VT V OL OUTPUT 2 VT HIGH-LOW -HIGH PULSE VT ALVC Link tPLH2 tPHL2 tSK (x) = tPLH2 - tP LH1 or tPHL2 - tPHL1 NOTES: ALVC Link 1. For tSK(o) OUTPUT1 and OUTPUT2 are any two outputs. 2. For tSK(b) OUTPUT1 and OUTPUT2 are in the same bank. 4 IDT74ALVC32 3.3V CMOS QUADRUPLE 2-INPUT POSITIVE-OR GATE INDUSTRIAL TEMPERATURE RANGE ORDERING INFORMATION IDT XX Tem p. R ange ALVC XXX XX Device Type Package DC PY PG Sm all Outline IC (SO 14-1) Shrink Sm all Outline Package (SO14-2) Thin Shrink Sm all Outline Package (SO14-3) 32 Quadruple 2-Input Positive-OR Gate, ±24mA 74 – 40°C to +85°C CORPORATE HEADQUARTERS 2975 Stender Way Santa Clara, CA 95054 for SALES: 800-345-7015 or 408-727-6116 fax: 408-492-8674 www.idt.com* *To search for sales office near you, please click the sales button found on our home page or dial the 800# above and press 2. The IDT logo is a registered trademark of Integrated Device Technology, Inc. 5