IDT74ALVCH374 3.3V CMOS OCTAL POSITIVE EDGE-TRIGGERED D-TYPE INDUSTRIAL TEMPERATURE RANGE IDT74ALVCH374 3.3V CMOS OCTAL POSITIVE EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH 3-STATE OUTPUTS AND BUS-HOLD DESCRIPTION: FEATURES: – – – – – – – – – 0.5 MICRON CMOS Technology Typical tSK(o) (Output Skew) < 250ps ESD > 2000V per MIL-STD-883, Method 3015; > 200V using machine model (C = 200pF, R = 0) VCC = 3.3V ±0.3V, Normal Range VCC = 2.7V to 3.6V, Extended Range VCC = 2.5V ±0.2V CMOS power levels (0.4µ W typ. static) Rail-to-Rail output swing for increased noise margin Available in SOIC, SSOP, QSOP, and TSSOP packages This octal postive edge-triggered D-type flip-flop is built using advanced dual metal CMOS technology. The ALVCH374 device is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. On the positive transition of the clock (CLK) input, the Q outputs are set to the logic levels at the data (D) inputs. A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without interface or pullup components. OE does not affect internal operations of the latch. Old data can be retained or new data can be entered while the outputs are in the high-impedance state. Drive Features for ALVCH374: – High Output Drivers: ±24mA – Suitable for heavy loads The ALVCH374 has been designed with a ±24mA output driver. This driver is capable of driving a moderate to heavy load while maintaining speed performance. APPLICATIONS: • 3.3V High Speed Systems • 3.3V and lower voltage computing systems The ALVCH374 has a “bus-hold” which retains the inputs’ last state whenever the input bus goes to a high impedance. This prevents floating inputs and eliminates the need for pull-up/down resistors. FUNCTIONAL BLOCK DIAGRAM OE CLK 1 11 C1 2 3 1D 1Q 1D TO SEVEN OTHER CHANNELS INDUSTRIAL TEMPERATURE RANGE MARCH 1999 1 c 1999 Integrated Device Technology, Inc. DSC-4473/- IDT74ALVCH374 3.3V CMOS OCTAL POSITIVE EDGE-TRIGGERED D-TYPE INDUSTRIAL TEMPERATURE RANGE ABSOLUTE MAXIMUM RATINGS(1) PIN CONFIGURATION OE 1 20 V CC 1Q 2 19 8Q 1D 3 2D 4 2Q 3Q 5 6 SO20-2 SO20-7 SO20-8 SO20-9 18 8D 17 7D 16 7Q 15 6Q 3D 7 14 6D 4D 8 13 5D 4Q 9 12 5Q 10 11 CLK GND Symbol VTERM(2) Description Terminal Voltage with Respect to GND Max. – 0.5 to +4.6 Unit V VTERM(3) IOUT Terminal Voltage with Respect to GND –0.5 to VCC +0.5 V – 50 to +50 mA IIK ±50 mA IOK Continuous Clamp Current, VI < 0 or VI > VCC Continuous Clamp Current, VO < 0 –50 mA ICC ISS TSTG Continuous Current through each VCC or GND Storage Temperature ±100 mA DC Output Current – 65 to +150 °C ALVC Link NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. VCC terminals. 3. All terminals except VCC. SSOP/ TVSOP/ TSSOP/ QSOP TOP VIEW CAPACITANCE (TA = +25°C, f = 1.0MHz) Symbol CIN Parameter(1) Input Capacitance Conditions VIN = 0V Typ. 5 Max. 7 Unit pF COUT Output Capacitance VOUT = 0V 7 9 pF CI/O I/O Port Capacitance VIN = 0V 7 9 pF ALVC Link NOTE: 1. As applicable to the device type. PIN DESCRIPTION Pin Names OE Description 3-State Output Enable Input (Active LOW) CLK Clock Input xD Data Inputs(1) xQ 3-State Outputs NOTE: 1. These pins have “Bus-hold”. All other pins are standard inputs, outputs, or I/Os. FUNCTION TABLE (each flip=flop) Inputs (1) Output OE L CLK ↑ xD H xQ H L ↑ L L H or L X L Q0 H X X Z NOTE: 1. H = HIGH Voltage Level L = LOW Voltage Level X = Don’t Care Z = High-Impedance ↑ = LOW-to-HIGH Transition Q0 = Level of Q before the indicated steady-state input conditions were established. c 1998 Integrated Device Technology, Inc. 2 DSC-123456 IDT74ALVCH374 3.3V CMOS OCTAL POSITIVE EDGE-TRIGGERED D-TYPE INDUSTRIAL TEMPERATURE RANGE DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE Following Conditions Apply Unless Otherwise Specified: Operating Condition: TA = –40°C to +85°C Symbol VIH VIL Parameter Input HIGH Voltage Level Input LOW Voltage Level VCC = 2.3V to 2.7V Min. 1.7 Typ.(1) — Max. — VCC = 2.7V to 3.6V 2 — — Test Conditions VCC = 2.3V to 2.7 V — — 0.7 VCC = 2.7V to 3.6V — — 0.8 ±5 Unit V V IIH Input HIGH Current VCC = 3.6V VI = VCC — — µA IIL Input LOW Current VCC = 3.6V VI = GND — — ±5 IOZH High Impedance Output Current VCC = 3.6V VO = VCC — — ± 10 µA IOZL (3-State Output pins) VO = GND — — ± 10 µA VIK Clamp Diode Voltage VCC = 2.3V, IIN = –18mA — – 0.7 – 1.2 V VH Input Hysteresis VCC = 3.3V — 100 — mV ICCL ICCH ICCZ ∆ICC Quiescent Power Supply Current VCC = 3.6V VIN = GND or VCC — 0.1 10 µA Quiescent Power Supply Current Variation One input at VCC – 0.6V, other inputs at VCC or GND — — 750 µA ALVC Link NOTE: 1. Typical values are at VCC = 3.3V, +25°C ambient. BUS-HOLD CHARACTERISTICS Symbol IBHH Parameter(1) Bus-Hold Input Sustain Current VCC = 3.0V Bus-Hold Input Sustain Current VCC = 2.3V Test Conditions VI = 2.0V IBHL IBHH IBHL IBHHO Bus-Hold Input Overdrive Current VCC = 3.6V Min. – 75 Typ.(2) — Max. — VI = 0.8V 75 — — VI = 1.7V – 45 — — VI = 0.7V 45 — — VI = 0 to 3.6V — — ± 500 Unit µA µA µA IBHLO ALVC Link NOTES: 1. Pins with Bus-hold are identified in the pin description. 2. Typical values are at VCC = 3.3V, +25°C ambient. 3 IDT74ALVCH374 3.3V CMOS OCTAL POSITIVE EDGE-TRIGGERED D-TYPE INDUSTRIAL TEMPERATURE RANGE OUTPUT DRIVE CHARACTERISTICS Symbol VOH Parameter Output HIGH Voltage VCC Test Conditions(1) = 2.3V to 3.6V IOH = – 0.1mA IOH = – 6mA 2 — VCC = 2.3V IOH = – 12mA 1.7 — 2.2 — VCC = 3.0V Output LOW Voltage Max. — VCC = 2.3V VCC = 2.7V VOL Min. VCC – 0.2 2.4 — VCC = 3.0V IOH = – 24mA 2 — VCC = 2.3V to 3.6V IOL = 0.1mA — 0.2 VCC = 2.3V IOL = 6mA — 0.4 IOL = 12mA — 0.7 VCC = 2.7V IOL = 12mA — 0.4 VCC = 3.0V IOL = 24mA — 0.55 Unit V V ALVC Link NOTE: 1. VIH and VIL must be within the min. or max. range shown in the DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE table for the appropriate VCC range. TA = – 40°C to + 85°C. OPERATING CHARACTERISTICS, TA = 25oC Symbol CPD CPD Parameter Power Dissipation Capacitance Outputs enabled Power Dissipation Capacitance Outputs disabled VCC = 2.5V ± 0.2V VCC = 3.3V ± 0.3V Typical Typical Test Conditions CL = 0pF, f = 10Mhz Unit pF pF SWITCHING CHARACTERISTICS (1) VCC = 2.5V ± 0.2V Symbol tPLH tPHL tPZH tPZL tPHZ tPLZ VCC = 2.7V VCC = 3.3V ± 0.3V Parameter Propagation Delay CLK to xQ Output Enable Time OE to xQ Output Disable Time OE to xQ Min. — Max. 8 Min. — Max. 7 Min. 2.2 Max. 6 Unit ns — 8.5 — 7.5 1.5 6.5 ns — 9.5 — 6.5 1.5 5.5 ns tW Pulse Duration, CLK HIGH or LOW 3.3 — 3.3 — 3.3 — ns tSU Setup Time, data before CLK↑ 2 — 2 — 2 — ns tH Hold Time, data after CLK↑ 1.5 — 1.5 — 1.5 — ns Output Skew(2) — — — — — 500 ps tSK(o) NOTES: 1. See test circuits and waveforms. TA = – 40°C to + 85°C. 2. Skew between any two outputs of the same package and switching in the same direction. 4 IDT74ALVCH374 3.3V CMOS OCTAL POSITIVE EDGE-TRIGGERED D-TYPE INDUSTRIAL TEMPERATURE RANGE TEST CIRCUITS AND WAVEFORMS TEST CONDITIONS PROPAGATION DELAY Symbol VLOAD VCC(1)= 3.3V ±0.3V VCC(1) = 2.7V VCC(2)= 2.5V ±0.2V Unit 2 x Vcc V 6 6 VIH 2.7 2.7 Vcc V VT 1.5 1.5 VCC / 2 V VLZ 300 300 150 mV VHZ 300 300 150 mV CL 50 50 30 V IH VT 0V SAME PHASE INPUT TRANSITION tPLH tPHL tPLH tPHL V OH VT V OL OUTPUT V IH VT 0V OPPOSITE PHASE INPUT TRANSITION pF ALVC Link ALVC Link TEST CIRCUITS FOR ALL OUTPUTS ENABLE AND DISABLE TIMES V LOAD V CC Open 500 Ω V IN (1, 2) Pulse Generator CONTROL INPUT GND V OUT tPZL D.U.T. OUTPUT SW ITCH NORMALLY CLO SED LOW tPZH OUTPUT SW ITCH NORMALLY OP EN HIGH 500 Ω RT CL ALVC Link DEFINITIONS: CL = Load capacitance: includes jig and probe capacitance. RT = Termination resistance: should be equal to ZOUT of the Pulse Generator. NOTES: 1. Pulse Generator for All Pulses: Rate ≤ 10MHz; tF ≤ 2.5ns; tR ≤ 2.5ns. 2. Pulse Generator for All Pulses: Rate ≤ 10MHz; tF ≤ 2ns; tR ≤ 2ns. Test Open Drain Disable Low Enable Low Disable High Enable High All Other tests DATA INPUT tPLH1 GND Open SYNCHRONOUS CONTROL 0V 0V tS U V IH VT 0V V IH VT 0V V IH VT 0V V IH VT 0V tH tREM tSU tH PULSE WIDTH VT 0V LOW -HIGH-LOW PULSE VT V OL tSK (x) HIGH-LOW -HIGH PULSE VT V OL OUTPUT 2 VT tW V OH tPLH2 V OH V HZ VT ALVC Link tPHL1 tSK (x) V LZ V OL tPHZ V IH V OH OUTPUT 1 V LOAD/2 TIMING INPUT ALVC Link INPUT V LOAD/2 VT SET-UP, HOLD, AND RELEASE TIMES ASYNCHRONOUS CONTROL (x) 0V NOTE: 1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH. Switch VLOAD TSK tPLZ V IH VT ALVC Link SWITCH POSITION OUTPUT SKEW - DISABLE ENABLE VT A LV C Link tPHL2 tSK (x) = tPLH2 - tPLH1 or t PHL2 - tPHL1 ALVC Link NOTES: 1. For tSK(o) OUTPUT1 and OUTPUT2 are any two outputs. 2. For tSK(b) OUTPUT1 and OUTPUT2 are in the same bank. 5 IDT74ALVCH374 3.3V CMOS OCTAL POSITIVE EDGE-TRIGGERED D-TYPE INDUSTRIAL TEMPERATURE RANGE ORDERING INFORMATION IDT XX X XXX XX Bus-Hold Device Type Package ALVC Tem p. Range SO PY Q PG Small Outline IC (SO 20-2) Shrink S m all Outline Package (SO20-7) Quarter-size Sm all Outline Package (SO20-8) Thin Shrink Small Outline Package (SO20-9) 374 Octal Positive Edge-Triggered D-Type Flip-Flop with 3-State Outputs, ±24mA H Bus-Hold 74 –40°C to +85°C CORPORATE HEADQUARTERS 2975 Stender Way Santa Clara, CA 95054 for SALES: 800-345-7015 or 408-727-6116 fax: 408-492-8674 www.idt.com* *To search for sales office near you, please click the sales button found on our home page or dial the 800# above and press 2. The IDT logo is a registered trademark of Integrated Device Technology, Inc. 6