User’s Manual IE-703204-G1-EM1 Emulation Board Target Devices V850ES/SA2 V850ES/SA3 Document No. U16622EJ1V0UM00 (1st edition) Date Published September 2003 N CP(K) 2003 Printed in Japan [MEMO] 2 User’s Manual U16622EJ1V0UM Windows is either a trademark or a registered trademark of Microsoft Corporation in the United States and/or other countries. PC/AT is a trademark of International Business Machines Corporation. • The information in this document is current as of March, 2003. The information is subject to change without notice. For actual design-in, refer to the latest publications of NEC Electronics data sheets or data books, etc., for the most up-to-date specifications of NEC Electronics products. Not all products and/or types are available in every country. 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Before using any NEC Electronics product in your application, pIease contact the NEC Electronics office in your country to obtain a list of authorized representatives and distributors. They will verify: • Device availability • Ordering information • Product release schedule • Availability of related technical literature • Development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, AC supply voltages, and so forth) • Network requirements In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country. [GLOBAL SUPPORT] http://www.necel.com/en/support/support.html NEC Electronics America, Inc. (U.S.) NEC Electronics (Europe) GmbH NEC Electronics Hong Kong Ltd. Santa Clara, California Tel: 408-588-6000 800-366-9782 Duesseldorf, Germany Tel: 0211-65 03 01 Hong Kong Tel: 2886-9318 • Sucursal en España Madrid, Spain Tel: 091-504 27 87 • Succursale Française Vélizy-Villacoublay, France Tel: 01-30-67 58 00 • Filiale Italiana Milano, Italy Tel: 02-66 75 41 • Branch The Netherlands Eindhoven, The Netherlands Tel: 040-244 58 45 • Tyskland Filial Taeby, Sweden Tel: 08-63 80 820 NEC Electronics Hong Kong Ltd. Seoul Branch Seoul, Korea Tel: 02-558-3737 NEC Electronics Shanghai, Ltd. Shanghai, P.R. China Tel: 021-6841-1138 NEC Electronics Taiwan Ltd. Taipei, Taiwan Tel: 02-2719-2377 NEC Electronics Singapore Pte. Ltd. Novena Square, Singapore Tel: 6253-8311 • United Kingdom Branch Milton Keynes, UK Tel: 01908-691-133 J03.4 4 User’s Manual U16622EJ1V0UM INTRODUCTION Target Readers This manual is intended for users who design and develop application systems using the V850ES/SA2 and V850ES/SA3 microcontrollers. Purpose The purpose of this manual is to describe the basic specifications of the IE703204-G1-EM1 and its proper operation. Organization This manual is broadly divided into the following parts. • Outline • Cautions • Part names and functions • Restrictions • Setup procedure How to Read This Manual It is assumed that the reader of this manual has general knowledge in the fields of electrical engineering, logic circuits, and microcontrollers. Use the IE-703204-G1-EM1 connected to the in-circuit emulator (IE-V850ES-G1). This manual describes the basic setup procedures and switch settings of the IE-703204-G1-EM1 and IE-V850ES-G1. For the part names, functions, and configuration parts of the IE-V850ES-G1, refer to the IE-V850ES-G1 User’s Manual (U16313E) provided separately. To learn about the basic specifications and operation →Read this manual in the order listed in CONTENTS. To learn software settings such as the operation methods, command functions, etc., of the IE-V850ES-G1 or IE-703204-G1-EM1 →Read the user’s manual of the debugger (sold separately) that is used. Conventions Note: Footnote for item marked with Note in the text Caution: Information requiring particular attention Remark: Supplementary information Binary … ×××× or ××××B Numeral representation: Decimal ... ×××× Hexadecimal ... ××××H Prefix representing a power of 2 (address space, memory capacity): K (kilo): 210 = 1024 M (mega): 220 = 10242 Terminology Target device Target system The meanings of terms used in this manual are listed below. This is the device to be emulated. The system (user-built system) to be debugged. This includes the target program and hardware configured by the user. Emulation CPU The CPU that executes the program created by the user in the emulator. User’s Manual U16622EJ1V0UM 5 /, B 4 ' 5 6 ( '?4 3 ' /, +,'& * > ; > ; ( )*!"#*-5)*0 !"#6 && )*+&,*-*5 <!"#$#%4!"#$#%&6 !"#$#%4!"#$#%&? "C" 0%!"''"0013 / "& 0D ", %( D 11 '"' , ""C )>!"''")>( /B( + #!"''"# # /B( ! #!"''D# # 91/ )# ,!+& 2E!"'&'&D52*/#6 < &,& ) &, &,& < &++& ) &++, &++ 2E!"1'&'&52*/#6 2>!"'&'3>( &+&+ 2>!"1'&'3>( &C %F!"'&'# 1% G ,, 1-*71,7 1 " /, 0+ 01// /2 3 +4 //,2 ( CONTENTS CHAPTER 1 OUTLINE ........................................................................................................................10 1.1 Product Configuration ...........................................................................................................11 1.2 Features (When Connected to IE-V850ES-G1) ....................................................................12 1.3 Function Specifications (When Connected to IE-V850ES-G1) ..........................................13 1.4 System Configuration............................................................................................................14 1.5 Contents in Carton.................................................................................................................16 CHAPTER 2 PART NAMES AND FUNCTIONS..................................................................................17 2.1 Part Names and Functions of IE-703204-G1-EM1 ...............................................................17 2.2 LEDs Controlled by IE-703204-G1-EM1................................................................................19 CHAPTER 3 SETUP PROCEDURE ....................................................................................................20 3.1 Connecting IE-V850ES-G1 and IE-703204-G1-EM1 with Probe .........................................20 3.2 Replacing Resonator .............................................................................................................23 CHAPTER 4 CAUTIONS .....................................................................................................................24 4.1 Connection with Target System ...........................................................................................24 4.2 Characteristics of Target Interface.......................................................................................24 CHAPTER 5 RESTRICTIONS .............................................................................................................34 5.1 Clock Generator .....................................................................................................................34 5.2 Timing of Setting/Releasing Standby Mode ........................................................................34 5.3 DMA .........................................................................................................................................34 5.4 Operation During Break.........................................................................................................34 APPENDIX A PACKAGE DRAWINGS................................................................................................35 User’s Manual U16622EJ1V0UM 7 LIST OF FIGURES Figure No. Title Page 1-1 System Configuration ...................................................................................................................................14 1-2 Contents in Carton .......................................................................................................................................16 2-1 Part Names of IE-703204-G1-EM1 ..............................................................................................................17 2-2 LEDs Controlled by IE-703204-G1-EM1 ......................................................................................................19 4-1 Equivalent Circuit A ......................................................................................................................................24 4-2 Equivalent Circuit B ......................................................................................................................................24 4-3 Equivalent Circuit C......................................................................................................................................25 4-4 Equivalent Circuit D......................................................................................................................................25 4-5 Equivalent Circuit E ......................................................................................................................................25 4-6 Equivalent Circuit F ......................................................................................................................................25 4-7 Equivalent Circuit G......................................................................................................................................26 4-8 Equivalent Circuit H......................................................................................................................................26 4-9 Equivalent Circuit I .......................................................................................................................................26 4-10 Equivalent Circuit J.......................................................................................................................................26 4-11 Equivalent Circuit K ......................................................................................................................................27 4-12 Equivalent Circuit L ......................................................................................................................................27 8 User’s Manual U16622EJ1V0UM LIST OF TABLES Figure No. Title Page 4-1 Pin Correspondence List (V850ES/SA2 Pin Names) ...................................................................................28 4-2 Pin Correspondence List (V850ES/SA3 Pin Names) ...................................................................................31 User’s Manual U16622EJ1V0UM 9 CHAPTER 1 OUTLINE The IE-703204-G1-EM1 is an emulation board for the IE-V850ES-G1 in-circuit emulator. Connected to the IE-V850ES-G1, the IE-703204-G1-EM1 can be used for efficient hardware and software debugging during system development using the V850ES/SA2 and V850ES/SA3. This manual describes the basic setup procedure and the switch settings of the IE-V850ES-G1 when connected to the IE-703204-G1-EM1. For the part names and functions of the IE-V850ES-G1, refer to the separate IE-V850ES-G1 User’s Manual (U16313E). 10 User’s Manual U16622EJ1V0UM CHAPTER 1 OUTLINE 1.1 Product Configuration Separately-sold products In-circuit emulator (IE-V850ES-G1) Emulation board (IE-703204-G1-EM1) The IE-V850ES-G1 can be used as an in-circuit emulator for the V850ES/SA2 and V850ES/SA3 by installing the IE-703204-G1-EM1 board. Separately-sold products Sockets SWEX-100SD-1 SWEX-120SE-1 PC interface board IE-70000-PCI-IF(-A) IE-70000-CD-IF-A General-purpose probes made by TOKYO ELETECH CORPORATION This is a board for connecting the IE-V850ES-G1 to a PC. , More than one such board can be installed using the PC s expansion slots. IE-70000-PCI-IF(-A): For PCI bus IE-70000-CD-IF-A: For PCMCIA socket User’s Manual U16622EJ1V0UM 11 CHAPTER 1 OUTLINE 1.2 Features (When Connected to IE-V850ES-G1) • Maximum operating frequency: 20 MHz (2.2 V to 2.7 V) • The following pins can be masked. NMI, WAIT, RESET, HLDRQ • The external dimensions of the IE-703204-G1-EM1 are listed below Item External dimensions 12 Value Height 35 mm Width 205 mm Depth 140 mm User’s Manual U16622EJ1V0UM CHAPTER 1 OUTLINE 1.3 Function Specifications (When Connected to IE-V850ES-G1) Item Specification Emulation memory capacity Internal ROM 1 MB For user memory 4 MB Internal ROM 256 KB External memory 1 MB Memory access detection coverage memory capacity External memory 1 MB Branch destination entry count calculation coverage memory capacity Internal ROM 256 KB External memory 1 MB Execution/pass detection coverage memory capacity Trace memory capacity 168 bits × 32 K frames Time measurement function Internal timers × 3 External logic probe 8-bit external trace possible Trace/break event setting possible Break function Event break Step execution break Forced break Fail-safe break • Illegal access to peripheral I/O • Access to guard area • Write to ROM area Caution Some functions may not be supported depending on the debugger that is used. User’s Manual U16622EJ1V0UM 13 CHAPTER 1 OUTLINE 1.4 System Configuration The system configuration when using the IE-703204-G1-EM1 connected to the IE-V850ES-G1, which itself is connected to a PC (PC-9800 series or PC/ATTM compatible) is shown below. Figure 1-1. System Configuration <7> <14> Target system <9> <10> <15> <11> <8> <6> <1> Target connector connection example (enlarged view) <2> Target system <14> <12> <4> <3> Remarks <5> <13> <1>: PC (PC-9800 series or PC/AT compatible) <2>: Debugger (sold separately), device file (obtained separately)Note 1 <3>: PC interface board (IE-70000-PCI-IF(-A), IE-70000-CD-IF-A: Sold separately) <4>: PC interface cable (supplied with IE-V850ES-G1: Sold separately) <5>: IE-V850ES-G1 (sold separately) <6>: Emulation board (this product) <7>: ProbeNote 2 (SWEX-120SE-1: Sold separately) <8>: ProbeNote 2 (SWEX-100SD-1: Sold separately) <9>: CSICE121A1312N03Note 2 (sold separately) <10>: LSPACK121A1312N01Note 2 (sold separately) <11>: CSSOCKET121A1312N01Note 2 (sold separately) or CSSOCKET121A1312N01NNote 2 (sold separately) (CSSOCKET121A1312N01S1Note 2 (sold separately) can be used for stacking.) CSSOCKET121A1312N01N is a type with no guide pins. <12>: YQPACK100SDNote 2 (supplied with this product) 14 User’s Manual U16622EJ1V0UM CHAPTER 1 OUTLINE <13>: NQPACK100SDNote 2 (supplied with this product) <14>: YQGUIDENote 2 (supplied with this product) <15>: Power supply cable (supplied with IE-V850-G1: Sold separately) Notes 1. 2. The device file can be downloaded from the NEC Electronics website. (URL: http://www.necel.com/micro) These are products of TOKYO ELETECH CORPORATION. For further information, contact Daimaru Kogyo Co., Ltd. Tokyo Electronics Department (TEL: +81-3-3820-7112) Osaka Electronics Department (TEL: +81-6-6244-6672) User’s Manual U16622EJ1V0UM 15 CHAPTER 1 OUTLINE 1.5 Contents in Carton The IE-703204-G1-EM1 package contains the IE-703204-G1-EM1 emulation board, a guarantee card, a packing list, this manual, and an accessory bag. Check whether the accessory bag contains the items listed below. If you find any missing or damaged items, contact an NEC Electronics sales representative or distributor. Figure 1-2. Contents in Carton <1> IE-703204-G1-EM1 <4> Packing list <3> Guaranteed card <2> Accessory bag <1> IE-703204-G1-EM1 × 1 <2> Accessory bag × 1 <3> Guarantee card × 1 <4> Packing list × 1 Check whether the accessory bag contains the following items in addition to this manual and the packing list (× 1). (a) 7-pin header (for resonator replacement): × 1 (b) NQPACK100SD (for mounting board): ×1 YQPACK100SD (for mounting probe): ×1 HQPACK100SD (for mounting IC): ×1 YQ-GUIDE (guide pin): ×4 (c) Screws/washers: 16 6 sets (6 screws + 6 washers are included) User’s Manual U16622EJ1V0UM CHAPTER 2 PART NAMES AND FUNCTIONS This chapter describes the part names and functions of the IE-703204-G1-EM1. For the part names and functions of the IE-V850ES-G1, refer to the IE-V850ES-G1 User’s Manual (U16313E). 2.1 Part Names and Functions of IE-703204-G1-EM1 Figure 2-1. Part Names of IE-703204-G1-EM1 (3) OSC1 (main clock) (4) OSC2 (subclock) 1 1 (2) Socket for connecting SWEX-120SE-1 (1) Socket for connecting SWEX-100SD-1 User’s Manual U16622EJ1V0UM 17 CHAPTER 2 PART NAMES AND FUNCTIONS (1) Socket for connecting SWEX-100SD-1 Connect the SWEX-100SD-1 when using the IE-703204-G1-EM1 as the emulator of the V850ES/SA2. (2) Socket for connecting SWEX-120SE-1 Connect the SWEX-120SE-1 when using the IE-703204-G1-EM1 as the emulator of the V850ES/SA3. (3) OSC1 (main clock) This is the socket in which the resonator that generates the main clock is mounted. Use this socket when replacing the resonator for the main clock. For details, refer to 3.2 Resonator Replacement. (4) OSC2 (subclock) This is the socket in which the resonator that generates the subclock is mounted. The frequency of the subclock is fixed to 32.768 kHz, so the resonator for subclock cannot be replaced. 18 User’s Manual U16622EJ1V0UM CHAPTER 2 PART NAMES AND FUNCTIONS 2.2 LEDs Controlled by IE-703204-G1-EM1 Some of the LEDs mounted in the IE-V850ES-G1 are controlled by the IE-703204-G1-EM1. For the LEDs that are controlled by the IE-V850ES-G1, refer to the IE-V850ES-G1 User’s Manual (U16313E). Figure 2-2. LEDs Controlled by IE-703204-G1-EM1 Reset LED Target VDD supply voltage <1> Target VDD supply voltage <2> TARGET POWER (1) Reset LED The status of the RESET signal connected to the target system is indicated as follows. Lit (ON): The target system is connected and the RESET signal is active (GND level). Unlit (OFF): Either the target system is not connected, or the RESET signal is inactive (VDD level). (2) Target VDD supply voltage <1> The status of the VDD signal connected to the target system is indicated as follows. (This LED indicates the status of pin 11 during V850ES/SA2 emulation, and the status of the F3 pin during V850ES/SA3 emulation.) Lit (ON): The target system is connected, and voltage is being applied to the VDD pin. Unlit (OFF): Either the target system is not connected, or voltage is not being applied to the VDD pin. (3) Target VDD supply voltage <2> The status of the VDD signal connected to the target system is indicated as follows. (This LED indicates the status of pin 19 during V850ES/SA2 emulation, and the status of the H2 pin during V850ES/SA3 emulation.) Lit (ON): The target system is connected and voltage is being applied to the VDD pin. Unlit (OFF): Either the target system is not connected, or voltage is not being applied to the VDD pin. User’s Manual U16622EJ1V0UM 19 CHAPTER 3 SETUP PROCEDURE This chapter describes how to connect the IE-703204-G1-EM1 to related products and how to replace the resonator. 3.1 Connecting IE-V850ES-G1 and IE-703204-G1-EM1 with Probe The following shows the procedure to connect the IE-V850ES-G1 and IE-703204-G1-EM1 with the probe. <1> Pull off the front cover of the IE-V850ES-G1. <2> Raise the frame of the IE-V850ES-G1 as shown. 20 User’s Manual U16622EJ1V0UM CHAPTER 3 SETUP PROCEDURE <3> With the main board and the IE-703204-G1-EM1 aligned as shown, insert three connectors on each side. At this time align the board so that the socket (YQSOCKET) to connect the prove faces towards the probe exit side. Insert the probe (SWEX-100SD-1 or SWEX-120SE-1) in the socket corresponding to the target device (refer to the following figure). Socket to connect SWEX-120SE-1 (for V850ES/SA3) Socket to connect SWEX-100SD-1 (for V850ES/SA2) User’s Manual U16622EJ1V0UM 21 CHAPTER 3 SETUP PROCEDURE <4> Slowly lower the frame of the IE-V850ES-G1. <5> Replace the front cover of the IE-V850ES-G1. 22 User’s Manual U16622EJ1V0UM CHAPTER 3 SETUP PROCEDURE 3.2 Replacing Resonator The IE-703204-G1-EM1 does not support clock oscillation by the resonator on the target system. Therefore, to change the main clock frequency, replace the resonator mounted in OSC1 (main clock) on the IE-703204-G1-EM1 with a resonator with the desired frequency. After shipment, the following oscillators are mounted as oscillators for generating each clock. Item Setting OSC1 (main clock) 20 MHz oscillator OSC2 (subclock) 32.768 kHz oscillator To change the main clock frequency, mount the resonator and capacitor on the included 7-pin header as shown and substitute it for the 7-pin header already mounted on OSC1 (main clock). Open 1 2 3 4 5 6 7 6 7 7-pin header 1 2 3 4 5 OSC1 (main clock) 7-pin socket Open X1 X2 µPD70F3204Y (Emulation CPU) The frequency of the subclock is fixed to 32.768 kHz, so the resonator for the subclock cannot be replaced. The IE-703204-G1-EM1 does not support clock oscillation by the resonator on the target system. Therefore, operation between the resonator on the target system and the oscillator in the target device cannot be emulated using the IE703204-G1-EM1. User’s Manual U16622EJ1V0UM 23 CHAPTER 4 CAUTIONS The following must be observed when using the IE-703204-G1-EM1. 4.1 Connection with Target System Turn off power to the IE-V850ES-G1 before connecting the IE-703204-G1-EM1 to the target system. 4.2 Characteristics of Target Interface The target interface (signals connecting the in-circuit emulator and the target system) functionally operates as if an actual device is connected, however, the characteristics may be different than those of the actual device. The target interface of the IE-703204-G1-EM1 is one of those shown in Figures 4-1 to 4-12. The target interface processing of each target device is shown in Tables 4-1 and 4-2. Figure 4-1. Equivalent Circuit A Target system side IE system side Port pin µPD70F3204Y Emulation CPU Figure 4-2. Equivalent Circuit B Target system side Same potential as VDD VCCA IE system side 3.6 V VCCB P174AVC16245 A B (Voltage level shifter) 24 User’s Manual U16622EJ1V0UM EP1K100FC484 (FPGA) CHAPTER 4 CAUTIONS Figure 4-3. Equivalent Circuit C Target system side IE system side Port pin Same potential as VDD µ PD70F3204Y Emulation CPU 3.6 V VCCA VCCB P174AVC16245 A B (Voltage level shifter) EP1K100FC484 (FPGA) Figure 4-4. Equivalent Circuit D Same potential as VDD Same potential as VDD 3.6 V Target system side IE system side 10 kΩ VCCA A VCCB P174AVC16245 B (Voltage level shifter) µPC393G2 (Comparator) User reset pin Figure 4-5. Equivalent Circuit E Same potential as VDD Target system side VCCA G6H-2F (Relay)Note IE system side 3.6 V VCCB P174AVC16245 A B (Voltage level shifter) AVREF0 µ PD70F3204Y AVREF1 Emulation CPU Note Conducts only when the target system is connected. Figure 4-6. Equivalent Circuit F Target system side IE system side II100 Ω µ PC393G2 (Comparator) 1 MΩ User’s Manual U16622EJ1V0UM 25 CHAPTER 4 CAUTIONS Figure 4-7. Equivalent Circuit G Same potential as VDD Target system side VCCA G6H-2F (Relay)Note IE system side 3.6 V VCCB P174AVC16245 A B (Voltage level shifter) AVREF0 µ PD70F3204Y AVREF1 Emulation CPU Note Conducts only when the target system is connected. Figure 4-8. Equivalent Circuit H Target system side Same potential as VDD 3.6 V VCCA VCCB IE system side P174AVC16245 A B (Voltage level shifter) 1 MΩ II- EP1K100FC484 (FPGA) Figure 4-9. Equivalent Circuit I Target system side Same potential as VDD IE system side µ PD70F3204Y Emulation CPU AVDD Open AVDD EVDD Open EVDD Open N.C. Figure 4-10. Equivalent Circuit J IE system side Target system side µ PD70F3204Y Emulation CPU N.C. 26 Open Open User’s Manual U16622EJ1V0UM N.C. CHAPTER 4 CAUTIONS Figure 4-11. Equivalent Circuit K Target system side IE system side µ PD70F3204Y Emulation CPU AVSS AVSS VSS VSS EVSS EVSS Figure 4-12. Equivalent Circuit L IE system side Target system side µPD70F3204 Emulation CPU 1 X1 Open X2 Open 7 X1 X2 XT1 Open XT2 Open 27 pF 32.768 kHz 27 pF 1 7 XT1 XT2 1 MΩ User’s Manual U16622EJ1V0UM 27 CHAPTER 4 CAUTIONS Table 4-1. Pin Correspondence List (V850ES/SA2 Pin Names) (1/3) V850ES/SA2 Pin No. 28 Target Interface Name (V850ES/SA2 Pin Names) Processing in In-Circuit Emulator 1 AVREF0 Emulation circuit E 2 AVDD Emulation circuit I 3 AVSS Emulation circuit K 4 P80/ANO0 Emulation circuit A 5 P81/ANO1 Emulation circuit A 6 AVREF1 Emulation circuit E 7 P00/NMI Emulation circuit A 8 P30/SI1/RXD0 Emulation circuit A 9 P31/SO1/TXD0 Emulation circuit A 10 P32/SCK1 Emulation circuit A 11 VDD Emulation circuit A 12 VSS Emulation circuit K 13 X1 Emulation circuit L 14 X2 Emulation circuit L 15 RESET Emulation circuit D 16 XT1 Emulation circuit L 17 XT2 Emulation circuit L 18 VDD Emulation circuit G 19 VSS Emulation circuit K 20 P90/A0 Emulation circuit C 21 P91/A1 Emulation circuit C 22 P92/A2/INTP5 Emulation circuit C 23 P93/A3/INTP6 Emulation circuit C 24 P94/A4/TO2 Emulation circuit C 25 P95/A5/TO3 Emulation circuit C 26 P96/A6/TO4 Emulation circuit C 27 P97/A7/TO5 Emulation circuit C 28 P98/A8/RXD1 Emulation circuit C 29 P99/A9/TXD1 Emulation circuit C 30 P910/A10/SI2 Emulation circuit C 31 P911/A11/SO2 Emulation circuit C 32 P912/A12/SCK2 Emulation circuit C 33 P913/A13/SI3 Emulation circuit C 34 P914/A14/SO3 Emulation circuit C 35 P915/A15/SCK3 Emulation circuit C 36 EVSS Emulation circuit K 37 EVDD Emulation circuit I 38 PCS0/CS0 Emulation circuit B 39 PCS1/CS1 Emulation circuit B 40 PCS2/CS2 Emulation circuit B User’s Manual U16622EJ1V0UM CHAPTER 4 CAUTIONS Table 4-1. Pin Correspondence List (V850ES/SA2 Pin Names) (2/3) V850ES/SA2 Pin No. Target Interface Name (V850ES/SA2 Pin Names) Processing in In-Circuit Emulator 41 PCS3/CS3 Emulation circuit B 42 PCM0/WAIT Emulation circuit B 43 PCM1/CLKOUT Emulation circuit B 44 PCM2/HLDAK Emulation circuit B 45 PCM3/HLDRQ Emulation circuit B 46 PCT0/WR0 Emulation circuit B 47 PCT1/WR1 Emulation circuit B 48 PCT4/RD Emulation circuit B 49 PCT5 Emulation circuit B 50 PCT6/ASTB Emulation circuit B 51 PCT7 Emulation circuit B 52 PDL0/AD0 Emulation circuit B 53 PDL1/AD1 Emulation circuit B 54 PDL2/AD2 Emulation circuit B 55 PDL3/AD3 Emulation circuit B 56 PDL4/AD4 Emulation circuit B 57 PDL5/AD5/FLMD1 Emulation circuit B 58 PDL6/AD6 Emulation circuit B 59 PDL7/AD7 Emulation circuit B 60 PDL8/AD8 Emulation circuit B 61 PDL9/AD9 Emulation circuit B 62 IC/FLMD0 Emulation circuit B 63 EVSS Emulation circuit K 64 EVDD Emulation circuit I 65 PDL10/AD10 Emulation circuit B 66 PDL11/AD11 Emulation circuit B 67 PDL12/AD12 Emulation circuit B 68 PDL13/AD13 Emulation circuit B 69 PDL14/AD14 Emulation circuit B 70 PDL15/AD15 Emulation circuit B 71 PDH0/A16 Emulation circuit B 72 PDH1/A17 Emulation circuit B 73 PDH2/A18 Emulation circuit B 74 PDH3/A19 Emulation circuit B 75 PDH4/A20 Emulation circuit B 76 PDH5/A21 Emulation circuit B 77 P40/SI0 Emulation circuit A 78 P41/SO0/SDA Emulation circuit A 79 P42/SCK0/SCL Emulation circuit A 80 P43/INTP00/TI0/TCLR0 Emulation circuit A User’s Manual U16622EJ1V0UM 29 CHAPTER 4 CAUTIONS Table 4-1. Pin Correspondence List (V850ES/SA2 Pin Names) (3/3) V850ES/SA2 Pin No. 30 Target Interface Name (V850ES/SA2 Pin Names) Processing in In-Circuit Emulator 81 P44/INTP01/TO0 Emulation circuit A 82 P45/INTP10/TI1/TCLR1 Emulation circuit A 83 P46/INTP11/TO1 Emulation circuit A 84 P01/INTP0/TI2 Emulation circuit A 85 P02/INTP1/TI3 Emulation circuit A 86 P03/INTP2/TI4 Emulation circuit A 87 P04/INTP3/TI5 Emulation circuit A 88 P05/INTP4 Emulation circuit A 89 P711/ANI11 Emulation circuit A 90 P710/ANI10 Emulation circuit A 91 P79/ANI9 Emulation circuit A 92 P78/ANI8 Emulation circuit A 93 P77/ANI7 Emulation circuit A 94 P76/ANI6 Emulation circuit A 95 P75/ANI5 Emulation circuit A 96 P74/ANI4 Emulation circuit A 97 P73/ANI3 Emulation circuit A 98 P72/ANI2 Emulation circuit A 99 P71/ANI1 Emulation circuit A 100 P70/ANI0 Emulation circuit A User’s Manual U16622EJ1V0UM CHAPTER 4 CAUTIONS Table 4-2. Pin Correspondence List (V850ES/SA3 Pin Names) (1/3) V850ES/SA3 Pin No. Target Interface Name (V850ES/SA3 Pin Names) Processing in In-Circuit Emulator A1 P70/ANI0 Emulation circuit A A2 P71/ANI1 Emulation circuit A A3 P73/ANI3 Emulation circuit A A4 P713/ANI13 Emulation circuit A A5 P76/ANI6 Emulation circuit A A6 P78/ANI8 Emulation circuit A A7 P711/ANI11 Emulation circuit A A8 P04/INTP3/TI5 Emulation circuit A A9 PCD2 Emulation circuit B A10 P45/INTP10/TI1/TCLR1 Emulation circuit A A11 P43/INTP00/TI0/TCLR0 Emulation circuit A A12 P41/SO0/SDA Emulation circuit A A13 PDH5/A21 Emulation circuit B B1 AVDD Emulation circuit I B2 AVREF0 Emulation circuit E B3 P72/ANI2 Emulation circuit A B4 P712/ANI12 Emulation circuit A B5 P75/ANI5 Emulation circuit A B6 P77/ANI7 Emulation circuit A B7 P710/ANI10 Emulation circuit A B8 PCD3 Emulation circuit B B9 P02/INTP1/TI3 Emulation circuit A B10 P46/INTP11/TO1 Emulation circuit A B11 P42/SCK0/SCL Emulation circuit A B12 P40/SI0 Emulation circuit A B13 PDH4/A20 Emulation circuit B C1 P80/ANO0 Emulation circuit A C2 AVSS Emulation circuit K C3 P74/ANI4 Emulation circuit A C4 P714/ANI14 Emulation circuit A C5 P715/ANI15 Emulation circuit A C6 P79/ANI9 Emulation circuit A C7 P05/INTP4[/ADTRG] Emulation circuit A C8 P03/INTP2/TI4 Emulation circuit A C9 PCD1 Emulation circuit B C10 P01/INTP0/TI2 Emulation circuit A C11 P44/INTP01/TO0 Emulation circuit A C12 PDH3/A19 Emulation circuit B C13 PDH7/A23 Emulation circuit H D1 P81/ANO1 Emulation circuit A D2 AVREF1 Emulation circuit E User’s Manual U16622EJ1V0UM 31 CHAPTER 4 CAUTIONS Table 4-2. Pin Correspondence List (V850ES/SA3 Pin Names) (2/3) V850ES/SA3 Pin No. 32 Target Interface Name (V850ES/SA3 Pin Names) Processing in In-Circuit Emulator D3 P00/NMI Emulation circuit A D4 N.C. Emulation circuit J D11 PDH0/A16 Emulation circuit B D12 PDH2/A18 Emulation circuit B D13 PDH1/A17 Emulation circuit B E1 P30/SI1/RXD0 Emulation circuit A E2 P31/SO1/TXD0 Emulation circuit A E3 P32/SCK1 Emulation circuit A E11 PDL14/AD14 Emulation circuit B E12 PDH6/A22 Emulation circuit H E13 PDL15/AD15 Emulation circuit B F1 VSS Emulation circuit K F2 X1 Emulation circuit L F3 VDD Emulation circuit F F11 PDL11/AD11 Emulation circuit B F12 PDL13/AD13 Emulation circuit B F13 PDL12/AD12 Emulation circuit B G1 RESET Emulation circuit D G2 XT1 Emulation circuit L G3 X2 Emulation circuit L G11 EVSS Emulation circuit K G12 PDL10/AD10 Emulation circuit B G13 EVDD Emulation circuit I H1 VSS Emulation circuit K H2 VDD Emulation circuit G H3 XT2 Emulation circuit L H11 PDL8/AD8 Emulation circuit B H12 MODE/FLMD0 Emulation circuit B H13 PDL9/AD9 Emulation circuit B J1 P20/SI4 Emulation circuit A J2 P91/A1 Emulation circuit C J3 P90/A0 Emulation circuit C J11 PDL5/AD5/FLMD1 Emulation circuit B J12 PDL7/AD7 Emulation circuit B J13 PDL6/AD6 Emulation circuit B K1 P22/SCK4 Emulation circuit A K2 P92/A2/INTP5 Emulation circuit C K3 P21/SO4 Emulation circuit A K11 PCM1/CLKOUT Emulation circuit B K12 PDL4/AD4 Emulation circuit B User’s Manual U16622EJ1V0UM CHAPTER 4 CAUTIONS Table 4-2. Pin Correspondence List (V850ES/SA3 Pin Names) (3/3) V850ES/SA3 Pin No. Target Interface Name (V850ES/SA3 Pin Names) Processing in In-Circuit Emulator K13 PDL3/AD3 Emulation circuit B L1 P93/A3/INTP6 Emulation circuit C L2 P94/A4/TO2 Emulation circuit C L3 P911/A11/SO2 Emulation circuit C L4 P914/A14/SO3 Emulation circuit C L5 P915/A15/SCK3 Emulation circuit C L6 EVDD Emulation circuit I L7 PCS0/CS0 Emulation circuit B L8 PCS2/CS2 Emulation circuit B L9 PCM4 Emulation circuit H L10 PCT2 Emulation circuit H L11 PCT0/WR0 Emulation circuit B L12 PDL1/AD1 Emulation circuit B L13 PDL2/AD2 Emulation circuit B M1 P95/A5/TO3 Emulation circuit C M2 P97/A7/TO5 Emulation circuit C M3 P99/A9/TXD1 Emulation circuit C M4 P913/A13/SI3 Emulation circuit C M5 EVSS Emulation circuit K M6 PCS5 Emulation circuit H M7 PCS4 Emulation circuit H M8 PCM0/WAIT Emulation circuit B M9 PCM2/HLDAK Emulation circuit B M10 PCT3 Emulation circuit H M11 PCT4/RD Emulation circuit B M12 PCT7 Emulation circuit B M13 PDL0/AD0 Emulation circuit B N1 P96/A6/TO4 Emulation circuit C N2 P98/A8/RXD1 Emulation circuit C N3 P910/A10/SI2 Emulation circuit C N4 P912/A12/SCK2 Emulation circuit C N5 PCS7 Emulation circuit H N6 PCS6 Emulation circuit H N7 PCS1/CS1 Emulation circuit B N8 PCS3/CS3 Emulation circuit B N9 PCM5 Emulation circuit H N10 PCM3/HLDRQ Emulation circuit B N11 PCT1/WR1 Emulation circuit B N12 PCT5 Emulation circuit B N13 PCT6/ASTB Emulation circuit B User’s Manual U16622EJ1V0UM 33 CHAPTER 5 RESTRICTIONS The IE-703204-G1-EM1 has the following restrictions. 5.1 Clock Generator (1) Resonator to be connected Oscillation by the resonator on the target system is not supported. Therefore, clock oscillation operation on the target system cannot be emulated with the in-circuit emulator. (2) Emulation of oscillation stabilization time after reset has been released In the target device for emulation, oscillation stabilization time is inserted after reset has been released; however, it is not inserted in the in-circuit emulator. (3) Operation clock after reset In the target device for emulation, the operation clock after reset is fXX/8; however, there may be a period in which the clock is not initialized to fXX/8 with the in-circuit emulator (depending on the timing of reset release). 5.2 Timing of Setting/Releasing Standby Mode The timing of setting/releasing the standby mode is different between the target device and the in-circuit emulator. The difference is within 1 clock when standby mode is set, and 2 or 3 clocks when it is released. 5.3 DMA The status of the DCHC0 to DCHC3 registers of the DMA function vary when read; however, these registers cannot be displayed by the I/O register browser of the debugger. 5.4 Operation During Break In the in-circuit emulator, peripheral functions operate during a break, so there may be a difference between the operations of the in-circuit emulator and target device. (However, while the in-circuit emulator is in the break status, the counter of the watchdog timer stops.) 34 User’s Manual U16622EJ1V0UM APPENDIX A PACKAGE DRAWINGS (1) NQPACK100SD (unit: mm) TOP VIEW R – 3 C 1.5 2. 2 21.0 0.5 X 24 = 12.0 5.8 0.3 0.5 5.8 13.0 20.2 16.6 Slit width 3 – φ 1.0 2.5 + 0.1 14.0 – 0 2.5 1.85 0.18 0.5 15.0 0.5 0.2 9.45 1.85 3.7 1.2 5.1 5.5 3.9 SIDE VIEW BOTTOM VIEW 14.0 0.2 Slit width 16.0 15.0 17.0 9.0 4 – φ 2.0 Projection height 1.8 Remark NQPACK100SD is a product of TOKYO ELETECH CORPORATION. User’s Manual U16622EJ1V0UM 35 APPENDIX A PACKAGE DRAWINGS (2) YQPACK100SD (unit: mm) TOP VIEW 4 16.6 0.5 X 24 = 12.0 0.5 5.8 φ2 – 5.8 13.4 21.0 23.0 .2 3. 2 3 –φ 1.0 R – – R 4 4 10.9 13.3 15.7 18.1 2 2. SIDE VIEW 2.3 1.2 3.1 7.4 2.5 0.25 X 0.3 3.9 2.2 9.0 3.1 3.7 0.3 0.25 0.4 BOTTOM VIEW 0.2 14.1 17.3 16.1 15.3 C 1.5 13.4 Remark 36 YQPACK100SD is a product of TOKYO ELETECH CORPORATION. User’s Manual U16622EJ1V0UM APPENDIX A PACKAGE DRAWINGS (3) HQPACK100SD (unit: mm) TOP VIEW 4 5.8 13.4 21.0 23.0 .2 φ2 – 16.6 0.5 X 24 = 12.0 0.5 5.8 3. 2 3 – φ 1.0 R R 2 2. 3.9 2.15 1.6 2.3 3.1 7.4 1.2 SIDE VIEW 0.23 0.58 BOTTOM VIEW 17.3 C 1.5 14.1 17.1 15.12 0.2 13.4 Remark HQPACK100SD is a product of TOKYO ELETECH CORPORATION. User’s Manual U16622EJ1V0UM 37 APPENDIX A PACKAGE DRAWINGS (4) CSICE121A1312N03 (unit: mm) TOP VIEW 23 16.6 0.4X29=11.6 0.4 0.4X29=11.6 0.4 C2 Pin 1 side φ 3.3 4- φ 2.2 Part hole 12.1 14.7 17.3 19.9 SIDE VIEW φ1.03 2.4 (8.1) (4) 0.8 3.9 φ 0.32 BOTTOM VIEW 0.8X12=9.6 0.8 CSICE121A1312N03 0.8 121-land diameter φ : 0.5 Resist diameter φ : 0.5 N 0.8X12=9.6 A 1 13 CSI-PWB-121A1312N01 MADE IN JAPAN TET 4.3 Remark 38 CSICE121A1312N03 is a product of TOKYO ELETECH CORPORATION. User’s Manual U16622EJ1V0UM APPENDIX A PACKAGE DRAWINGS (5) LSPACK121A1312N01 (unit: mm) TOP VIEW 29 22.65 0.8X12 = 9.6 0.8 0.8X12 = 9.6 0.8 LSPACK121A TET MADE IN JAPAN SIDE VIEW 1 6.7 1.65 BOTTOM VIEW Remark LSPACK121A1312N01 is a product of TOKYO ELETECH CORPORATION. User’s Manual U16622EJ1V0UM 39 APPENDIX A PACKAGE DRAWINGS (6) CSSOCKET121A1312N01 (unit: mm) TOP VIEW 12 9.6 0.8X12=9.6 4 4 C1 Pin 1 side 0.8 0.8X12=9.6 0.8 2.5 3 4.2 8.1 1.2 SIDE VIEW φ 0.25 φ 0.65 Remark 40 φ 0.7 CSSOCKET121A1312N01 is a product of TOKYO ELETECH CORPORATION. User’s Manual U16622EJ1V0UM APPENDIX A PACKAGE DRAWINGS (7) CSSOCKET121A1312N01N (unit: mm) TOP VIEW 12 4 4 9.6 0.8X12=9.6 C1 Pin 1 side 0.8 0.8X12=9.6 0.8 4.2 1.2 3 SIDE VIEW φ 0.25 φ 0.65 Remark CSSOCKET121A1312N01N is a product of TOKYO ELETECH CORPORATION. User’s Manual U16622EJ1V0UM 41 APPENDIX A PACKAGE DRAWINGS (8) CSSOCKET121A1312N01S1 (unit: mm) TOP VIEW 12 4 4 9.6 0.8X12=9.6 C1 Pin 1 side 0.8 0.8X12=9.6 0.8 4.2 1.2 3 SIDE VIEW φ 0.25 φ 0.65 Remark 42 CSSOCKET121A1312N01S1 is a product of TOKYO ELETECH CORPORATION. User’s Manual U16622EJ1V0UM APPENDIX A PACKAGE DRAWINGS (9) CSSOCKET121A1312N01 (foot pattern) (unit: mm) External dimensions of LSPACK 23 External dimensions of CSSOCKET 12 0.8X12=9.6 0.8 4 121-pad diameter: φ 4 0.8X12=9.6 4 0.8 C1 Pin 1 side 3- φ 0.8±0.05 Through hole: Finished diameter Remarks 1. After CSSOCKET has been fixed on the board by soldering, it is recommended to solder the guide pin of the connector from the lower side of the board or to fix the portion around the connector with resin for reinforcement. 2. The soldering reflow conditions are the same as for the CSPACK. Remark CSSOCKET121A1312N01 is a product of TOKYO ELETECH CORPORATION. User’s Manual U16622EJ1V0UM 43 APPENDIX A PACKAGE DRAWINGS (10) SWEX-100SD-1 (unit: mm) TOP VIEW (48) SG FG TET ( f 6) CN1 Target TET SWEX-100SD-E2 (38.5) SWEX-100SD1 CN4 100 IC1 1 75 25 51 26 FG SG JAPAN SG FG 76 (38.5) (295±8) CN3 (48) 50 MADE IN JAPAN FG SG CN2 (20) Red Black (5) (45) Ground Wire Remark 44 SWEX-100SD-1 is a product of TOKYO ELETECH CORPORATION. User’s Manual U16622EJ1V0UM (19.5) (13.1) 6.4 (13.1) (19.5) (20) APPENDIX A PACKAGE DRAWINGS (11) SWEX-120SE-1 (unit: mm) TOP VIEW (55.5) (295±8) TET ( f 7) JAPAN FG SG SG FG 109 1 108 73 36 37 CN2 72 MADE IN JAPAN FG (24) (12.5) 6.4 (12.5) (19.5) SIDE VIEW CN4 144 (47.5) CN1 Target TET SWEX-144SD-E2 (47.5) FG CN3 SWEX-144SD-1 (19.5) (55.5) (24) Red Black (5) (45) Ground Wire Remark SWEX-120SE-1 is a product of TOKYO ELETECH CORPORATION. User’s Manual U16622EJ1V0UM 45