CY7C1480V33 CY7C1482V33 CY7C1486V33 PRELIMINARY 72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined Sync SRAM Functional Description[1] Features • Supports bus operation up to 250 MHz • Available speed grades are 250, 200,167 MHz • Registered inputs and outputs for pipelined operation • 3.3V core power supply • 2.5V / 3.3V I/O operation • Fast clock-to-output times — 3.0 ns (for 250-MHz device) — 3.0 ns (for 200-MHz device) — 3.4 ns (for 167-MHz device) • Provide high-performance 3-1-1-1 access rate • User-selectable burst counter supporting Intel® Pentium® interleaved or linear burst sequences • Separate processor and controller address strobes • Synchronous self-timed writes • Asynchronous output enable • Single Cycle Chip Deselect • CY7C1480V33 and CY7C1482V33 offered in JEDEC-standard lead-free 100-pin TQFP, 165-Ball fBGA packages. CY7C1486V33 available in 209-Ball BGA packages • IEEE 1149.1 JTAG-Compatible Boundary Scan • “ZZ” Sleep Mode Option The CY7C1480V33/CY7C1482V33/CY7C1486V33 SRAM integrates 2,097,152 x 36/4,194,304 x 18,1,048,576 × 72 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input (CLK). The synchronous inputs include all addresses, all data inputs, address-pipelining Chip Enable (CE1), depth-expansion Chip Enables (CE2 and CE3), Burst Control inputs (ADSC, ADSP, and ADV), Write Enables (BWX, and BWE), and Global Write (GW). Asynchronous inputs include the Output Enable (OE) and the ZZ pin. Addresses and chip enables are registered at rising edge of clock when either Address Strobe Processor (ADSP) or Address Strobe Controller (ADSC) are active. Subsequent burst addresses can be internally generated as controlled by the Advance pin (ADV). Address, data inputs, and write controls are registered on-chip to initiate a self-timed Write cycle.This part supports Byte Write operations (see Pin Descriptions and Truth Table for further details). Write cycles can be one to two or four bytes wide as controlled by the byte write control inputs. GW when active LOW causes all bytes to be written. The CY7C1480V33/CY7C1482V33/CY7C1486V33 operates from a +3.3V core power supply while all outputs may operate with either a +2.5 or +3.3V supply. All inputs and outputs are JEDEC-standard JESD8-5-compatible. Selection Guide 250 MHz 200 MHz 167 MHz Unit Maximum Access Time 3.0 3.0 3.4 ns Maximum Operating Current 500 500 450 mA Maximum CMOS Standby Current 120 120 120 mA Shaded areas contain advance information. Please contact your local Cypress sales representative for availability of these parts. Note: 1. For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com. Cypress Semiconductor Corporation Document #: 38-05283 Rev. *C • 3901 North First Street • San Jose, CA 95134 • 408-943-2600 Revised December 3, 2004 CY7C1480V33 CY7C1482V33 CY7C1486V33 PRELIMINARY 1 Logic Block Diagram – CY7C1480V33 (2M x 36) A0, A1, A ADDRESS REGISTER 2 A[1:0] MODE ADV CLK Q1 BURST COUNTER CLR AND Q0 LOGIC ADSC ADSP BWD DQD ,DQPD BYTE WRITE REGISTER DQD ,DQPD BYTE WRITE DRIVER BWC DQC ,DQPC BYTE WRITE REGISTER DQC ,DQPC BYTE WRITE DRIVER DQB ,DQPB BYTE WRITE REGISTER DQB ,DQPB BYTE WRITE DRIVER BWB BWA BWE GW CE1 CE2 CE3 OE ZZ SENSE AMPS OUTPUT REGISTERS OUTPUT BUFFERS E DQs DQPA DQPB DQPC DQPD DQA ,DQPA BYTE WRITE DRIVER DQA ,DQPA BYTE WRITE REGISTER ENABLE REGISTER MEMORY ARRAY INPUT REGISTERS PIPELINED ENABLE SLEEP CONTROL 2 Logic Block Diagram – CY7C1482V33 (4M x 18) A0, A1, A ADDRESS REGISTER 2 A[1:0] MODE BURST Q1 COUNTER AND LOGIC CLR Q0 ADV CLK ADSC ADSP BWB DQB,DQPB WRITE DRIVER DQB,DQPB WRITE REGISTER MEMORY ARRAY BWA DQA,DQPA WRITE DRIVER DQA,DQPA WRITE REGISTER SENSE AMPS OUTPUT REGISTERS OUTPUT BUFFERS DQs DQPA DQPB E BWE GW CE1 CE2 CE3 ENABLE REGISTER PIPELINED ENABLE INPUT REGISTERS OE ZZ SLEEP CONTROL Document #: 38-05283 Rev. *C Page 2 of 30 CY7C1480V33 CY7C1482V33 CY7C1486V33 PRELIMINARY Logic Block Diagram – CY7C1486V33 (1M x 72) ADDRESS REGISTER A0, A1,A A[1:0] MODE Q1 BINARY COUNTER CLR Q0 ADV CLK ADSC ADSP BWH DQH, DQPH WRITE DRIVER DQH, DQPH WRITE DRIVER BWG DQF, DQPF WRITE DRIVER DQG, DQPG WRITE DRIVER BWF DQF, DQPF WRITE DRIVER DQF, DQPF WRITE DRIVER BWE DQE, DQPE WRITE DRIVER DQ E, DQP BYTE “a”E WRITE DRIVER BWD DQD, DQPD WRITE DRIVER DQD, DQPD WRITE DRIVER BWC DQC, DQPC WRITE DRIVER DQC, DQPC WRITE DRIVER MEMORY ARRAY SENSE AMPS BWB BWA BWE ENABLE REGISTER OUTPUT BUFFERS E DQA, DQPA WRITE DRIVER DQA, DQPA WRITE DRIVER GW CE1 CE2 CE3 OE ZZ DQB, DQPB WRITE DRIVER DQB, DQPB WRITE DRIVER OUTPUT REGISTERS PIPELINED ENABLE INPUT REGISTERS DQs DQPA DQPB DQPC DQPD DQPE DQPF DQPG DQPH SLEEP CONTROL Document #: 38-05283 Rev. *C Page 3 of 30 CY7C1480V33 CY7C1482V33 CY7C1486V33 PRELIMINARY Pin Configurations NC NC NC VDDQ VSSQ NC NC DQB DQB VSSQ VDDQ DQB DQB NC VDD NC VSS DQB DQB VDDQ VSSQ DQB DQB DQPB NC VSSQ VDDQ NC NC NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 CY7C1482V33 (4M x 18) 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 Document #: 38-05283 Rev. *C A NC NC VDDQ VSSQ NC DQPA DQA DQA VSSQ VDDQ DQA DQA VSS NC VDD ZZ DQA DQA VDDQ VSSQ DQA DQA NC NC VSSQ VDDQ NC NC NC A A A A A A A A A A A A A A A A A A 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 DQPB DQB DQB VDDQ VSSQ DQB DQB DQB DQB VSSQ VDDQ DQB DQB VSS NC VDD ZZ DQA DQA VDDQ VSSQ DQA DQA DQA DQA VSSQ VDDQ DQA DQA DQPA MODE A A A A A1 A0 A A VSS VDD CY7C1480V33 (2M x 36) 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 MODE A A A A A1 A0 A A VSS VDD DQPC DQC DQc VDDQ VSSQ DQC DQC DQC DQC VSSQ VDDQ DQC DQC NC VDD NC VSS DQD DQD VDDQ VSSQ DQD DQD DQD DQD VSSQ VDDQ DQD DQD DQPD 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 A A CE1 CE2 NC NC BWB BWA CE3 VDD VSS CLK GW BWE OE ADSC ADSP ADV A A A A CE1 CE2 BWD BWC BWB BWA CE3 VDD VSS CLK GW BWE OE ADSC ADSP ADV A A 100-pin TQFP Pinout Page 4 of 30 CY7C1480V33 CY7C1482V33 CY7C1486V33 PRELIMINARY Pin Configurations (continued) 165-ball fBGA CY7C1480V33 (2M x 36) 1 A B C D E F G H J K L M N P NC / 288M R 2 A 3 4 5 6 7 8 9 10 11 CE1 BWC BWB CE3 BWE ADSC ADV A NC NC A CE2 BWD BWA CLK GW A NC / 144M NC DQC VDDQ VSS VSS VSS VSS VSS VSS VDDQ VDDQ VSS VDD OE VSS VDD ADSP DQPC DQC VDDQ NC DQB DQPB DQB DQC DQC VDDQ VDD VSS VSS VSS VDD VDDQ DQB DQB DQC DQC NC DQD DQC VDDQ VDD VSS VSS VSS VDD DQB DQB DQC NC DQD VDDQ NC VDDQ VDD VDD VDD VSS VSS VSS VSS VSS VSS VSS VSS VSS VDD VDD VDD VDDQ VDDQ NC VDDQ DQB NC DQA DQB ZZ DQA DQD DQD VDDQ VDD VSS VSS VSS VDD VDDQ DQA DQA DQD DQD VDDQ VDD VSS VSS VSS VDD VDDQ DQA DQA DQD DQPD DQD NC VDDQ VDDQ VDD VSS VSS NC VSS A VSS NC VDD VSS VDDQ VDDQ DQA NC DQA DQPA NC A A A TDI A1 TDO A A A A MODE A A A TMS TCK A A A A 7 8 9 10 11 A A0 CY7C1482V33 (4M x 18) 1 2 A B C D E F G H J K L M N P NC / 288M A 3 4 5 6 CE1 CE2 BWB NC CE3 NC A NC BWA NC NC NC DQB VDDQ VSS VDD VSS R VDDQ CLK BWE GW ADSC OE ADV ADSP A VSS VSS VSS VSS VSS VDD VDDQ VSS VDDQ NC NC A NC / 144M DQPA DQA NC DQB VDDQ VDD VSS VSS VSS VDD VDDQ NC DQA NC DQB VDDQ VDD VSS VSS VSS VDD VDDQ NC DQA NC NC DQB DQB NC NC VDDQ NC VDDQ VDD VDD VDD VSS VSS VSS VSS VSS VSS VSS VSS VSS VDD VDD VDD VDDQ NC VDDQ NC NC DQA DQA ZZ NC DQB NC VDDQ VDD VSS VSS VSS VDD VDDQ DQA NC DQB NC VDDQ VDD VSS VSS VSS VDD VDDQ DQA NC DQB DQPB NC NC VDDQ VDDQ VDD VSS VSS NC VSS A VSS NC VDD VSS VDDQ VDDQ DQA NC NC NC NC A A A TDI A1 TDO A A A A MODE A A A TMS A0 TCK A A A A Document #: 38-05283 Rev. *C Page 5 of 30 CY7C1480V33 CY7C1482V33 CY7C1486V33 PRELIMINARY Pin Configurations (continued) 209-ball BGA CY7C1486V33 (1M × 72) 1 2 3 A DQG DQG B DQG DQG BWSC C DQG DQG D DQG E 4 6 7 8 9 10 11 CE3 A DQB DQB ADSP ADSC ADV BWSG NC BWE A BWSB BWSF DQB DQB BWSH BWSD NC CE1 NC BWSE BWSA DQB DQB DQG VSS NC NC OE GW NC VSS DQB DQB DQPG DQPC VDDQ VDDQ VDD VDD VDD VDDQ VDDQ DQPF DQPB F DQC DQC VSS VSS VSS NC VSS VSS VSS DQF DQF G DQC DQC VDDQ VDDQ VDD NC VDD VDDQ VDDQ DQF DQF H DQC DQC VSS VSS VSS NC VSS VSS VSSQ DQF DQF J DQC DQC VDDQ VDDQ VDD NC VDD VDDQ VDDQ DQF DQF K NC NC CLK NC VSS VSS VSS NC NC NC NC L DQH DQH VDDQ VDDQ VDD NC VDD VDDQ VDDQ DQA DQA M DQH DQH VSS VSS VSS NC VSS VSS VSS DQA DQA N DQH DQH VDDQ VDDQ VDD NC VDD VDDQ VDDQ DQA DQA P DQH DQH VSS VSS VSS ZZ VSS VSS VSS DQA DQA R DQPD VDDQ VDD VDD VDD VDDQ VDDQ T DQD DQD VSS NC NC MODE NC NC VSS DQE DQE U DQD DQD A A A A A A A DQE DQE V DQD DQD A A A A1 A A A DQE DQE W DQD DQD TMS TDI A A0 A TCK DQE DQE A DQPH VDDQ Document #: 38-05283 Rev. *C CE2 5 TDO DQPA DQPE Page 6 of 30 CY7C1480V33 CY7C1482V33 CY7C1486V33 PRELIMINARY Pin Definitions Pin Name I/O Description A0, A1, A InputSynchronous Address Inputs used to select one of the address locations. Sampled at the rising edge of the CLK if ADSP or ADSC is active LOW, and CE1, CE2, and CE3 are sampled active. A1: A0 are fed to the two-bit counter. BWA,BWB,BWC,BWD, BWE,BWF,BWG,BWH InputSynchronous Byte Write Select Inputs, active LOW. Qualified with BWE to conduct byte writes to the SRAM. Sampled on the rising edge of CLK. GW InputSynchronous Global Write Enable Input, active LOW. When asserted LOW on the rising edge of CLK, a global write is conducted (ALL bytes are written, regardless of the values on BWX and BWE). BWE InputSynchronous Byte Write Enable Input, active LOW. Sampled on the rising edge of CLK. This signal must be asserted LOW to conduct a byte write. CLK InputClock CE1 InputSynchronous Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE2 and CE3 to select/deselect the device. ADSP is ignored if CE1 is HIGH. CE2 InputSynchronous Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction with CE1 and CE3 to select/deselect the device. CE3 InputSynchronous Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE1 and CE2 to select/deselect the device. OE InputOutput Enable, asynchronous input, active LOW. Controls the direction of the I/O Asynchronous pins. When LOW, the I/O pins behave as outputs. When deasserted HIGH, I/O pins are tri-stated, and act as input data pins. OE is masked during the first clock of a read cycle when emerging from a deselected state. ADV InputSynchronous Advance Input signal, sampled on the rising edge of CLK, active LOW. When asserted, it automatically increments the address in a burst cycle. ADSP InputSynchronous Address Strobe from Processor, sampled on the rising edge of CLK, active LOW. When asserted LOW, addresses presented to the device are captured in the address registers. A1: A0 are also loaded into the burst counter. When ADSP and ADSC are both asserted, only ADSP is recognized. ASDP is ignored when CE1 is deasserted HIGH. ADSC InputSynchronous Address Strobe from Controller, sampled on the rising edge of CLK, active LOW. When asserted LOW, addresses presented to the device are captured in the address registers. A1: A0 are also loaded into the burst counter. When ADSP and ADSC are both asserted, only ADSP is recognized. ZZ InputZZ “sleep” Input, active HIGH. When asserted HIGH places the device in a Asynchronous non-time-critical “sleep” condition with data integrity preserved. For normal operation, this pin has to be LOW or left floating. ZZ pin has an internal pull-down. DQs, DQPs I/OSynchronous VDD Power Supply Power supply inputs to the core of the device. VSS Ground Clock Input. Used to capture all synchronous inputs to the device. Also used to increment the burst counter when ADV is asserted LOW, during a burst operation. Bidirectional Data I/O lines. As inputs, they feed into an on-chip data register that is triggered by the rising edge of CLK. As outputs, they deliver the data contained in the memory location specified by the addresses presented during the previous clock rise of the read cycle. The direction of the pins is controlled by OE. When OE is asserted LOW, the pins behave as outputs. When HIGH, DQs and DQPX are placed in a tri-state condition. Ground for the core of the device. VSSQ I/O Ground Ground for the I/O circuitry. VDDQ I/O Power Supply Power supply for the I/O circuitry. MODE Input Static Selects Burst Order. When tied to GND selects linear burst sequence. When tied to VDD or left floating selects interleaved burst sequence. This is a strap pin and should remain static during device operation. Mode Pin has an internal pull-up. Document #: 38-05283 Rev. *C Page 7 of 30 CY7C1480V33 CY7C1482V33 CY7C1486V33 PRELIMINARY Pin Definitions (continued) Pin Name I/O Description TDO JTAG Serial Output Synchronous Serial data-out to the JTAG circuit. Delivers data on the negative edge of TCK. If the JTAG feature is not being utilized, this pin should be disconnected. This pin is not available on TQFP packages. TDI JTAG Serial Input Synchronous Serial data-In to the JTAG circuit. Sampled on the rising edge of TCK. If the JTAG feature is not being utilized, this pin can be disconnected or connected to VDD. This pin is not available on TQFP packages. TMS JTAG Serial Input Synchronous Serial data-In to the JTAG circuit. Sampled on the rising edge of TCK. If the JTAG feature is not being utilized, this pin can be disconnected or connected to VDD. This pin is not available on TQFP packages. TCK JTAG Clock Clock input to the JTAG circuitry. If the JTAG feature is not being utilized, this pin must be connected to VSS. This pin is not available on TQFP packages. NC - No Connects. Not internally connected to the die Functional Overview All synchronous inputs pass through input registers controlled by the rising edge of the clock. All data outputs pass through output registers controlled by the rising edge of the clock. Maximum access delay from the clock rise (tCO) is 3.0 ns (250-MHz device). The CY7C1480V33/CY7C1482V33/CY7C1486V33 supports secondary cache in systems utilizing either a linear or interleaved burst sequence. The interleaved burst order supports Pentium and i486™ processors. The linear burst sequence is suited for processors that utilize a linear burst sequence. The burst order is user selectable, and is determined by sampling the MODE input. Accesses can be initiated with either the Processor Address Strobe (ADSP) or the Controller Address Strobe (ADSC). Address advancement through the burst sequence is controlled by the ADV input. A two-bit on-chip wraparound burst counter captures the first address in a burst sequence and automatically increments the address for the rest of the burst access. Byte Write operations are qualified with the Byte Write Enable (BWE) and Byte Write Select (BWX) inputs. A Global Write Enable (GW) overrides all Byte Write inputs and writes data to all four bytes. All writes are simplified with on-chip synchronous self-timed Write circuitry. Three synchronous Chip Selects (CE1, CE2, CE3) and an asynchronous Output Enable (OE) provide for easy bank selection and output tri-state control. ADSP is ignored if CE1 is HIGH. Single Read Accesses This access is initiated when the following conditions are satisfied at clock rise: (1) ADSP or ADSC is asserted LOW, (2) CE1, CE2, CE3 are all asserted active, and (3) the Write signals (GW, BWE) are all deasserted HIGH. ADSP is ignored if CE1 is HIGH. The address presented to the address inputs (A) is stored into the address advancement logic and the Address Register while being presented to the memory array. The corresponding data is allowed to propagate to the input of the Output Registers. At the rising edge of the next clock the data is allowed to propagate through the output register and onto the data bus within 3.0 ns (250-MHz device) if OE is active LOW. The only exception occurs when the SRAM is emerging from a deselected state to a selected state, its outputs are always tri-stated during the first cycle of the Document #: 38-05283 Rev. *C access. After the first cycle of the access, the outputs are controlled by the OE signal. Consecutive single Read cycles are supported. Once the SRAM is deselected at clock rise by the chip select and either ADSP or ADSC signals, its output will tri-state immediately. Single Write Accesses Initiated by ADSP This access is initiated when both of the following conditions are satisfied at clock rise: (1) ADSP is asserted LOW, and (2) CE1, CE2, CE3 are all asserted active. The address presented to A is loaded into the address register and the address advancement logic while being delivered to the memory array. The Write signals (GW, BWE, and BWX) and ADV inputs are ignored during this first cycle. ADSP-triggered Write accesses require two clock cycles to complete. If GW is asserted LOW on the second clock rise, the data presented to the DQs inputs is written into the corresponding address location in the memory array. If GW is HIGH, then the Write operation is controlled by BWE and BWX signals. The CY7C1480V33/CY7C1482V33/CY7C1486V33 provides Byte Write capability that is described in the Write Cycle Descriptions table. Asserting the Byte Write Enable input (BWE) with the selected Byte Write (BWX) input, will selectively write to only the desired bytes. Bytes not selected during a Byte Write operation will remain unaltered. A synchronous self-timed Write mechanism has been provided to simplify the Write operations. Because CY7C1480V33/CY7C1482V33/CY7C1486V33 is a common I/O device, the Output Enable (OE) must be deasserted HIGH before presenting data to the DQs inputs. Doing so will tri-state the output drivers. As a safety precaution, DQs are automatically tri-stated whenever a Write cycle is detected, regardless of the state of OE. Single Write Accesses Initiated by ADSC ADSC Write accesses are initiated when the following conditions are satisfied: (1) ADSC is asserted LOW, (2) ADSP is deasserted HIGH, (3) CE1, CE2, CE3 are all asserted active, and (4) the appropriate combination of the Write inputs (GW, BWE, and BWX) are asserted active to conduct a Write to the desired byte(s). ADSC-triggered Write accesses require a single clock cycle to complete. The address presented to A is loaded into the address register and the address advancement logic while being delivered to the memory array. Page 8 of 30 CY7C1480V33 CY7C1482V33 CY7C1486V33 PRELIMINARY The ADV input is ignored during this cycle. If a global Write is conducted, the data presented to the DQs is written into the corresponding address location in the memory core. If a Byte Write is conducted, only the selected bytes are written. Bytes not selected during a Byte Write operation will remain unaltered. A synchronous self-timed Write mechanism has been provided to simplify the Write operations. Because CY7C1480V33/CY7C1482V33/CY7C1486V33 is a common I/O device, the Output Enable (OE) must be deasserted HIGH before presenting data to the DQs inputs. Doing so will tri-state the output drivers. As a safety precaution, DQs are automatically tri-stated whenever a Write cycle is detected, regardless of the state of OE. Accesses pending when entering the “sleep” mode are not considered valid nor is the completion of the operation guaranteed. The device must be deselected prior to entering the “sleep” mode. CE1, CE2, CE3, ADSP, and ADSC must remain inactive for the duration of tZZREC after the ZZ input returns LOW. Interleaved Burst Address Table (MODE = Floating or VDD) First Address A1: A0 Second Address A1: A0 Third Address A1: A0 Fourth Address A1: A0 00 01 10 11 Burst Sequences 01 00 11 10 The CY7C1480V33/CY7C1482V33/CY7C1486V33 provides a two-bit wraparound counter, fed by A1: A0, that implements either an interleaved or linear burst sequence. The interleaved burst sequence is designed specifically to support Intel Pentium applications. The linear burst sequence is designed to support processors that follow a linear burst sequence. The burst sequence is user selectable through the MODE input. 10 11 00 01 11 10 01 00 Asserting ADV LOW at clock rise will automatically increment the burst counter to the next address in the burst sequence. Both Read and Write burst operations are supported. Linear Burst Address Table (MODE = GND) First Address A1: A0 Second Address A1: A0 Third Address A1: A0 Fourth Address A1: A0 10 11 00 01 Sleep Mode 01 10 11 00 The ZZ input pin is an asynchronous input. Asserting ZZ places the SRAM in a power conservation “sleep” mode. Two clock cycles are required to enter into or exit from this “sleep” mode. While in this mode, data integrity is guaranteed. 10 11 00 01 11 00 01 10 ZZ Mode Electrical Characteristics Parameter Description IDDZZ Sleep mode standby current Test Conditions tZZS Device operation to ZZ ZZ > VDD – 0.2V tZZREC ZZ recovery time ZZ < 0.2V tZZI ZZ Active to Sleep current This parameter is sampled tRZZI ZZ Inactive to exit Sleep current This parameter is sampled Document #: 38-05283 Rev. *C Min. ZZ > VDD – 0.2V Max. Unit 120 mA 2tCYC ns 2tCYC ns 2tCYC 0 ns ns Page 9 of 30 CY7C1480V33 CY7C1482V33 CY7C1486V33 PRELIMINARY Truth Table[ 2, 3, 4, 4, 5, 6] Add. Used CE1 CE2 CE3 ZZ ADSP ADSC ADV Deselect Cycle, Power Down Operation None H X X L X L X WRITE OE CLK X X L-H Tri-State DQ Deselect Cycle, Power Down None L L X L L X X X X L-H Tri-State Deselect Cycle, Power Down None L X H L L X X X X L-H Tri-State Deselect Cycle, Power Down None L L X L H L X X X L-H Tri-State Deselect Cycle, Power Down None L X H L H L X X X L-H Tri-State Sleep Mode, Power Down None X X X H X X X X X X Tri-State READ Cycle, Begin Burst External L H L L L X X X L L-H Q READ Cycle, Begin Burst External L H L L L X X X H L-H Tri-State WRITE Cycle, Begin Burst External L H L L H L X L X L-H D READ Cycle, Begin Burst External L H L L H L X H L L-H Q READ Cycle, Begin Burst External L H L L H L X H H L-H Tri-State READ Cycle, Continue Burst Next X X X L H H L H L L-H READ Cycle, Continue Burst Next X X X L H H L H H L-H Tri-State Q READ Cycle, Continue Burst Next H X X L X H L H L L-H READ Cycle, Continue Burst Next H X X L X H L H H L-H Tri-State WRITE Cycle, Continue Burst Next X X X L H H L L X L-H D WRITE Cycle, Continue Burst Next H X X L X H L L X L-H D READ Cycle, Suspend Burst Current X X X L H H H H L L-H Q READ Cycle, Suspend Burst Current X X X L H H H H H L-H Tri-State READ Cycle, Suspend Burst Current H X X L X H H H L L-H READ Cycle, Suspend Burst Current H X X L X H H H H L-H Tri-State WRITE Cycle,Suspend Burst Current X X X L H H H L X L-H D WRITE Cycle,Suspend Burst Current H X X L X H H L X L-H D Q Q Notes: 2. X = “Don't Care.” H = Logic HIGH, L = Logic LOW. 3. WRITE = L when any one or more Byte Write enable signals and BWE = L or GW = L. WRITE = H when all Byte write enable signals, BWE, GW = H. 4. The DQ pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock. 5. The SRAM always initiates a read cycle when ADSP is asserted, regardless of the state of GW, BWE, or BWX. Writes may occur only on subsequent clocks after the ADSP or with the assertion of ADSC. As a result, OE must be driven HIGH prior to the start of the write cycle to allow the outputs to tri-state. OE is a don't care for the remainder of the write cycle 6. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle all data bits are Tri-State when OE is inactive or when the device is deselected, and all data bits behave as output when OE is active (LOW). 7. BWx represents any byte write signal.To enable any byte write BWx, a Logic LOW signal should be applied at clock rise. Any number of byte writes can be enabled at the same time for any given write. Document #: 38-05283 Rev. *C Page 10 of 30 CY7C1480V33 CY7C1482V33 CY7C1486V33 PRELIMINARY Truth Table for Read/Write[4] GW BWE BWD BWC BWB BWA Read Function (CY7C1480V33) H H X X X X Read H L H H H H Write Byte A – (DQA and DQPA) Write Byte B – (DQB and DQPB) H L H H H L H L H H L H Write Bytes B, A H L H H L L Write Byte C – (DQC and DQPC) H L H L H H Write Bytes C, A H L H L H L Write Bytes C, B H L H L L H Write Bytes C, B, A H L H L L L Write Byte D – (DQD and DQPD) H L L H H H Write Bytes D, A H L L H H L Write Bytes D, B H L L H L H Write Bytes D, B, A H L L H L L Write Bytes D, C H L L L H H Write Bytes D, C, A H L L L H L Write Bytes D, C, B H L L L L H Write All Bytes H L L L L L Write All Bytes L X X X X X Truth Table for Read/Write[4] Function (CY7C1482V33) GW BWE BWB BWA Read H H X X Read H L H H Write Byte A – (DQA and DQPA) Write Byte B – (DQB and DQPB) H L H L H L L H Write Bytes B, A H L L L Write All Bytes H L L L Write All Bytes L X X X Document #: 38-05283 Rev. *C Page 11 of 30 CY7C1480V33 CY7C1482V33 CY7C1486V33 PRELIMINARY IEEE 1149.1 Serial Boundary Scan (JTAG) Test MODE SELECT (TMS) The CY7C1480V33/CY7C1482V33 incorporates a serial boundary scan test access port (TAP). This port operates in accordance with IEEE Standard 1149.1-1990 but does not have the set of functions required for full 1149.1 compliance. These functions from the IEEE specification are excluded because their inclusion places an added delay in the critical speed path of the SRAM. Note that the TAP controller functions in a manner that does not conflict with the operation of other devices using 1149.1 fully compliant TAPs. The TAP operates using JEDEC-standard 3.3V or 2.5V I/O logic levels. The CY7C1480V33/CY7C1482V33 contains a TAP controller, instruction register, boundary scan register, bypass register, and ID register. Disabling the JTAG Feature It is possible to operate the SRAM without using the JTAG feature. To disable the TAP controller, TCK must be tied LOW (VSS) to prevent clocking of the device. TDI and TMS are internally pulled up and may be unconnected. They may alternately be connected to VDD through a pull-up resistor. TDO should be left unconnected. Upon power-up, the device will come up in a reset state which will not interfere with the operation of the device. The TMS input is used to give commands to the TAP controller and is sampled on the rising edge of TCK. It is allowable to leave this ball unconnected if the TAP is not used. The ball is pulled up internally, resulting in a logic HIGH level. Test Data-In (TDI) The TDI ball is used to serially input information into the registers and can be connected to the input of any of the registers. The register between TDI and TDO is chosen by the instruction that is loaded into the TAP instruction register. For information on loading the instruction register, see the TAP Controller State Diagram. TDI is internally pulled up and can be unconnected if the TAP is unused in an application. TDI is connected to the most significant bit (MSB) of any register. (See Tap Controller Block Diagram.) Test Data-Out (TDO) The TDO output ball is used to serially clock data-out from the registers. The output is active depending upon the current state of the TAP state machine. The output changes on the falling edge of TCK. TDO is connected to the least significant bit (LSB) of any register. (See Tap Controller State Diagram.) TAP Controller Block Diagram TAP Controller State Diagram 1 0 Bypass Register TEST-LOGIC RESET 2 1 0 0 0 RUN-TEST/ IDLE 1 SELECT DR-SCAN 1 SELECT IR-SCAN 0 1 1 CAPTURE-DR 0 TDO x . . . . . 2 1 0 SHIFT-IR 0 Boundary Scan Register 1 EXIT1-DR 1 EXIT1-IR 0 1 TCK 0 PAUSE-DR 0 PAUSE-IR 1 0 TMS TAP CONTROLLER 1 EXIT2-DR 0 EXIT2-IR 1 Performing a TAP Reset 1 UPDATE-DR 0 UPDATE-IR 1 0 The 0/1 next to each state represents the value of TMS at the rising edge of TCK. Test Access Port (TAP) Test Clock (TCK) The test clock is used only with the TAP controller. All inputs are captured on the rising edge of TCK. All outputs are driven from the falling edge of TCK. Document #: 38-05283 Rev. *C Selection Circuitry Identification Register CAPTURE-IR 1 Instruction Register 31 30 29 . . . 2 1 0 0 SHIFT-DR 1 TDI Selection Circuitry 0 0 0 1 A RESET is performed by forcing TMS HIGH (VDD) for five rising edges of TCK. This RESET does not affect the operation of the SRAM and may be performed while the SRAM is operating. At power-up, the TAP is reset internally to ensure that TDO comes up in a High-Z state. TAP Registers Registers are connected between the TDI and TDO balls and allow data to be scanned into and out of the SRAM test circuitry. Only one register can be selected at a time through the instruction register. Data is serially loaded into the TDI ball on the rising edge of TCK. Data is output on the TDO ball on the falling edge of TCK. Page 12 of 30 PRELIMINARY Instruction Register Three-bit instructions can be serially loaded into the instruction register. This register is loaded when it is placed between the TDI and TDO balls as shown in the Tap Controller Block Diagram. Upon power-up, the instruction register is loaded with the IDCODE instruction. It is also loaded with the IDCODE instruction if the controller is placed in a reset state as described in the previous section. When the TAP controller is in the Capture-IR state, the two least significant bits are loaded with a binary “01” pattern to allow for fault isolation of the board-level serial test data path. Bypass Register CY7C1480V33 CY7C1482V33 CY7C1486V33 Instructions are loaded into the TAP controller during the Shift-IR state when the instruction register is placed between TDI and TDO. During this state, instructions are shifted through the instruction register through the TDI and TDO balls. To execute the instruction once it is shifted in, the TAP controller needs to be moved into the Update-IR state. EXTEST EXTEST is a mandatory 1149.1 instruction which is to be executed whenever the instruction register is loaded with all 0s. EXTEST is not implemented in this SRAM TAP controller, and therefore this device is not compliant to 1149.1. The TAP controller does recognize an all-0 instruction. To save time when serially shifting data through registers, it is sometimes advantageous to skip certain chips. The bypass register is a single-bit register that can be placed between the TDI and TDO balls. This allows data to be shifted through the SRAM with minimal delay. The bypass register is set LOW (VSS) when the BYPASS instruction is executed. When an EXTEST instruction is loaded into the instruction register, the SRAM responds as if a SAMPLE/PRELOAD instruction has been loaded. There is one difference between the two instructions. Unlike the SAMPLE/PRELOAD instruction, EXTEST places the SRAM outputs in a High-Z state. Boundary Scan Register IDCODE The boundary scan register is connected to all the input and bidirectional balls on the SRAM. The x36 configuration has a 73-bit-long register, and the x18 configuration has a 54-bit-long register. The IDCODE instruction causes a vendor-specific, 32-bit code to be loaded into the instruction register. It also places the instruction register between the TDI and TDO balls and allows the IDCODE to be shifted out of the device when the TAP controller enters the Shift-DR state. The boundary scan register is loaded with the contents of the RAM I/O ring when the TAP controller is in the Capture-DR state and is then placed between the TDI and TDO balls when the controller is moved to the Shift-DR state. The EXTEST, SAMPLE/PRELOAD and SAMPLE Z instructions can be used to capture the contents of the I/O ring. The Boundary Scan Order tables show the order in which the bits are connected. Each bit corresponds to one of the bumps on the SRAM package. The MSB of the register is connected to TDI and the LSB is connected to TDO. Identification (ID) Register The ID register is loaded with a vendor-specific, 32-bit code during the Capture-DR state when the IDCODE command is loaded in the instruction register. The IDCODE is hardwired into the SRAM and can be shifted out when the TAP controller is in the Shift-DR state. The ID register has a vendor code and other information described in the Identification Register Definitions table. TAP Instruction Set Overview Eight different instructions are possible with the three-bit instruction register. All combinations are listed in the Instruction Codes table. Three of these instructions are listed as RESERVED and should not be used. The other five instructions are described in detail below. The TAP controller used in this SRAM is not fully compliant to the 1149.1 convention because some of the mandatory 1149.1 instructions are not fully implemented. The TAP controller cannot be used to load address data or control signals into the SRAM and cannot preload the I/O buffers. The SRAM does not implement the 1149.1 commands EXTEST or INTEST or the PRELOAD portion of SAMPLE/PRELOAD; rather, it performs a capture of the I/O ring when these instructions are executed. Document #: 38-05283 Rev. *C The IDCODE instruction is loaded into the instruction register upon power-up or whenever the TAP controller is given a test logic reset state. SAMPLE Z The SAMPLE Z instruction causes the boundary scan register to be connected between the TDI and TDO balls when the TAP controller is in a Shift-DR state. It also places all SRAM outputs into a High-Z state. SAMPLE/PRELOAD SAMPLE/PRELOAD is a 1149.1 mandatory instruction. The PRELOAD portion of this instruction is not implemented, so the device TAP controller is not fully 1149.1 compliant. When the SAMPLE/PRELOAD instruction is loaded into the instruction register and the TAP controller is in the Capture-DR state, a snapshot of data on the inputs and bidirectional balls is captured in the boundary scan register. The user must be aware that the TAP controller clock can only operate at a frequency up to 10 MHz, while the SRAM clock operates more than an order of magnitude faster. Because there is a large difference in the clock frequencies, it is possible that during the Capture-DR state, an input or output will undergo a transition. The TAP may then try to capture a signal while in transition (metastable state). This will not harm the device, but there is no guarantee as to the value that will be captured. Repeatable results may not be possible. To guarantee that the boundary scan register will capture the correct value of a signal, the SRAM signal must be stabilized long enough to meet the TAP controller’s capture set-up plus hold time (tCS plus tCH). The SRAM clock input might not be captured correctly if there is no way in a design to stop (or slow) the clock during a SAMPLE/PRELOAD instruction. If this is an issue, it is still Page 13 of 30 CY7C1480V33 CY7C1482V33 CY7C1486V33 PRELIMINARY BYPASS possible to capture all other signals and simply ignore the value of the CLK captured in the boundary scan register. When the BYPASS instruction is loaded in the instruction register and the TAP is placed in a Shift-DR state, the bypass register is placed between the TDI and TDO balls. The advantage of the BYPASS instruction is that it shortens the boundary scan path when multiple devices are connected together on a board. Once the data is captured, it is possible to shift out the data by putting the TAP into the Shift-DR state. This places the boundary scan register between the TDI and TDO balls. Note that since the PRELOAD part of the command is not implemented, putting the TAP to the Update-DR state while performing a SAMPLE/PRELOAD instruction will have the same effect as the Pause-DR command. Reserved These instructions are not implemented but are reserved for future use. Do not use these instructions. TAP Timing 1 2 Test Clock (TCK) 3 t TH t TMSS t TMSH t TDIS t TDIH t TL 4 5 6 t CYC Test Mode Select (TMS) Test Data-In (TDI) t TDOV t TDOX Test Data-Out (TDO) DON’T CARE UNDEFINED TAP AC Switching Characteristics Over the Operating Range[8, 9] Parameter Description Min. Max. Unit Clock tTCYC TCK Clock Cycle Time tTF TCK Clock Frequency tTH TCK Clock HIGH time 25 ns tTL TCK Clock LOW time 25 ns 50 ns 20 MHz Output Times tTDOV TCK Clock LOW to TDO Valid tTDOX TCK Clock LOW to TDO Invalid 5 ns 0 ns Set-up Times tTMSS TMS Set-up to TCK Clock Rise 5 ns tTDIS TDI Set-up to TCK Clock Rise 5 ns tCS Capture Set-up to TCK Rise 5 ns tTMSH TMS Hold after TCK Clock Rise 5 ns tTDIH TDI Hold after Clock Rise 5 ns tCH Capture Hold after Clock Rise 5 ns Hold Times Notes: 8. tCS and tCH refer to the set-up and hold time requirements of latching data from the boundary scan register. 9. Test conditions are specified using the load in TAP AC Test Conditions. tR/tF = 1 ns. Document #: 38-05283 Rev. *C Page 14 of 30 CY7C1480V33 CY7C1482V33 CY7C1486V33 PRELIMINARY 3.3V TAP AC Test Conditions 2.5V TAP AC Test Conditions Input pulse levels ............................................... .VSS to 3.3V Input pulse levels................................................. VSS to 2.5V Input rise and fall times ................................................... 1 ns Input rise and fall time .....................................................1 ns Input timing reference levels ...........................................1.5V Input timing reference levels......................................... 1.25V Output reference levels...................................................1.5V Output reference levels ................................................ 1.25V Test load termination supply voltage...............................1.5V Test load termination supply voltage ............................ 1.25V 3.3V TAP AC Output Load Equivalent 2.5V TAP AC Output Load Equivalent 1.25V 1.5V 50Ω 50Ω TDO TDO Z O= 50Ω Z O= 50Ω 20pF 20pF TAP DC Electrical Characteristics And Operating Conditions (0°C < TA < +70°C; VDD = 3.135 to 3.6V unless otherwise noted)[10] Parameter VOH1 VOH2 VOL1 VOL2 VIH VIL IX Description Test Conditions Min. Max. Unit Output HIGH Voltage IOH = –4.0 mA, VDDQ = 3.3V 2.4 V IOH = –1.0 mA, VDDQ = 2.5V 2.0 V VDDQ = 3.3V 2.9 V VDDQ = 2.5V 2.1 V Output HIGH Voltage IOH = –100 µA Output LOW Voltage Output LOW Voltage IOL = 8.0 mA VDDQ = 3.3V 0.4 V IOL = 1.0 mA VDDQ = 2.5V 0.4 V VDDQ = 3.3V 0.2 V VDDQ = 2.5V 0.2 V IOL = 100 µA Input HIGH Voltage Input LOW Voltage Input Load Current VDDQ = 3.3V 2.0 VDD + 0.3 V VDDQ = 2.5V 1.7 VDD + 0.3 V VDDQ = 3.3V –0.3 0.8 V VDDQ = 2.5V –0.3 0.7 V –5 5 µA GND < VIN < VDDQ Identification Register Definitions Instruction Field Revision Number (31:29) Device Depth (28:24) Architecture/Memory Type(23:18) Bus Width/Density(17:12) Cypress JEDEC ID Code (11:1) ID Register Presence Indicator (0) CY7C1480V33 CY7C1482V33 CY7C1486V33 (2M x36) (4M x 18) (1M x72) 000 000 000 Description Describes the version number 01011 01011 01011 000000 000000 000000 Defines memory type and architecture 110100 Defines width and density 100100 010100 00000110100 00000110100 1 1 Reserved for internal use 00000110100 Allows unique identification of SRAM vendor 1 Indicates the presence of an ID register Notes: 10. All voltages referenced to VSS (GND). 11. Bit #24 is “1” in the ID Register Definitions for both 2.5V and 3.3V versions of this device. Document #: 38-05283 Rev. *C Page 15 of 30 CY7C1480V33 CY7C1482V33 CY7C1486V33 PRELIMINARY Scan Register Sizes Register Name Bit Size (x36) Bit Size (x18) Bit Size (x72) Instruction 3 3 3 Bypass 1 1 1 ID 32 32 32 Boundary Scan Order-165FBGA 73 54 - - - 112 Boundary Scan Order-209BGA Identification Codes Instruction Code Description EXTEST 000 Captures the I/O ring contents. IDCODE 001 Loads the ID register with the vendor ID code and places the register between TDI and TDO. This operation does not affect SRAM operations. SAMPLE Z 010 Captures I/O ring contents. Places the boundary scan register between TDI and TDO. Forces all SRAM output drivers to a High-Z state. RESERVED 011 Do Not Use: This instruction is reserved for future use. SAMPLE/PRELOAD 100 Captures I/O ring contents. Places the boundary scan register between TDI and TDO. Does not affect SRAM operation. RESERVED 101 Do Not Use: This instruction is reserved for future use. RESERVED 110 Do Not Use: This instruction is reserved for future use. BYPASS 111 Places the bypass register between TDI and TDO. This operation does not affect SRAM operations. Boundary Scan Order (x36) Bit # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 165-Ball ID C1 D1 E1 D2 E2 F1 G1 F2 G2 J1 K1 L1 J2 M1 N1 K2 L2 M2 R1 R2 R3 P2 R4 P6 R6 Document #: 38-05283 Rev. *C Boundary Scan Order (x36) (continued) Bit # 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 165-Ball ID N6 P11 R8 P3 P4 P8 P9 P10 R9 R10 R11 N11 M11 L11 M10 L10 K11 J11 K10 J10 H11 G11 F11 E11 D10 Page 16 of 30 CY7C1480V33 CY7C1482V33 CY7C1486V33 PRELIMINARY Boundary Scan Order (x36) (continued) Bit # 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 165-Ball ID D11 C11 G10 F10 E10 A10 B10 A9 B9 A8 B8 A7 B7 B6 A6 B5 A5 A4 B4 B3 A3 A2 B2 Boundary Scan Order (x18) Bit # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 165-Ball ID D2 E2 F2 G2 J1 K1 L1 M1 N1 R1 R2 R3 P2 R4 P6 R6 N6 P11 R8 P3 P4 P8 P9 P10 Document #: 38-05283 Rev. *C Boundary Scan Order (x18) (continued) Bit # 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 165-Ball ID R9 R10 R11 M10 L10 K10 J10 H11 G11 F11 E11 D11 C11 A11 A10 B10 A9 B9 A8 B8 A7 B7 B6 A6 B5 A4 B3 A3 A2 B2 Boundary Scan Exit Order (x72) Bit # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 209-Ball ID A1 A2 B1 B2 C1 C2 D1 D2 E1 E2 F1 F2 G1 G2 H1 H2 J1 Page 17 of 30 CY7C1480V33 CY7C1482V33 CY7C1486V33 PRELIMINARY Boundary Scan Exit Order (x72) (continued) Bit # 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 209-Ball ID J2 L1 L2 M1 M2 N1 N2 P1 P2 R2 R1 T1 T2 U1 U2 V1 V2 W1 W2 T6 V3 V4 U4 W5 V6 W6 U3 U9 V5 U5 U6 W7 V7 U7 V8 V9 W11 W10 V11 V10 U11 U10 T11 T10 R11 R10 P11 P10 N11 N10 Document #: 38-05283 Rev. *C Boundary Scan Exit Order (x72) (continued) Bit # 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 209-Ball ID M11 M10 L11 L10 P6 J11 J10 H11 H10 G11 G10 F11 F10 E10 E11 D11 D10 C11 C10 B11 B10 A11 A10 A9 U8 A7 A5 A6 D6 B6 D7 K3 A8 B4 B3 C3 C4 C8 C9 B9 B8 A4 C6 B7 A3 Page 18 of 30 CY7C1480V33 CY7C1482V33 CY7C1486V33 PRELIMINARY Maximum Ratings Current into Outputs (LOW)......................................... 20 mA (Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ................................. –65°C to +150°C Static Discharge Voltage........................................... >2001V (per MIL-STD-883, Method 3015) Latch-up Current..................................................... >200 mA Ambient Temperature with Power Applied............................................. –55°C to +125°C Operating Range Supply Voltage on VDD Relative to GND........ –0.3V to +4.6V Range Commercial DC Voltage Applied to Outputs in Tri-State........................................... –0.5V to VDDQ + 0.5V Ambient Temperature 0°C to +70°C VDD VDDQ 3.3V – 5%/+10% 2.5V – 5% to VDD DC Input Voltage....................................–0.5V to VDD + 0.5V Electrical Characteristics Over the Operating Range[12, 13] Parameter Description Test Conditions VDD Power Supply Voltage VDDQ I/O Supply Voltage VOH Output HIGH Voltage VOL Output LOW Voltage VIH Input HIGH Voltage[12] VIL Input LOW Voltage[12] IX Input Load Current except ZZ and MODE GND ≤ VI ≤ VDDQ Min. 3.135 3.6 V 3.135 VDD V VDDQ = 2.5V 2.375 2.625 VDDQ = 3.3V, VDD = Min., IOH = –4.0 mA 2.4 VDDQ = 2.5V, VDD = Min., IOH = –1.0 mA 2.0 VDDQ = 3.3V, VDD = Min., IOL = 8.0 mA V V V 0.4 V 0.4 V 2.0 VDD + 0.3V V VDDQ = 2.5V 1.7 VDD + 0.3V V VDDQ = 3.3V –0.3 0.8 V VDDQ = 2.5V –0.3 0.7 V –5 5 µA VDDQ = 3.3V Input = VDD 30 Input = VSS Output Leakage Current GND ≤ VI ≤ VDDQ, Output Disabled IDD VDD Operating Supply Current VDD = Max., IOUT = 0 mA, f = fMAX = 1/tCYC Automatic CE Power-down Current—TTL Inputs VDD = Max, Device Deselected, VIN ≥ VIH or VIN ≤ VIL f = fMAX = 1/tCYC µA µA –30 5 µA 5 µA 4.0-ns cycle, 250 MHz 500 mA 5.0-ns cycle, 200 MHz 500 mA 6.0-ns cycle, 167 MHz 450 mA 4.0-ns cycle, 250 MHz 245 mA 5.0-ns cycle, 200 MHz 245 mA 6.0-ns cycle, 167 MHz 245 mA All speeds 120 mA Input = VDD IOZ µA –5 Input Current of MODE Input = VSS ISB1 Unit VDDQ = 3.3V VDDQ = 2.5V, VDD = Min., IOL = 1.0 mA Input Current of ZZ Max. –5 ISB2 Automatic CE VDD = Max, Device Deselected, Power-down VIN ≤ 0.3V or VIN > VDDQ – 0.3V, Current—CMOS Inputs f = 0 ISB3 VDD = Max, Device Deselected, or 4.0-ns cycle, 250 MHz Automatic CE Power-down VIN ≤ 0.3V or VIN > VDDQ – 0.3V 5.0-ns cycle, 200 MHz Current—CMOS Inputs f = fMAX = 1/tCYC 6.0-ns cycle, 167 MHz 245 mA 245 mA 245 mA Automatic CE Power-down Current—TTL Inputs 135 mA ISB4 VDD = Max, Device Deselected, VIN ≥ VIH or VIN ≤ VIL, f = 0 All speeds Shaded areas contain advance information. Notes: 12. Overshoot: VIH(AC) < VDD +1.5V (Pulse width less than tCYC/2), undershoot: VIL(AC) > –2V (Pulse width less than tCYC/2). 13. Power-up: Assumes a linear ramp from 0V to VDD(min.) within 200 ms. During this time VIH < VDD and VDDQ < VDD\ Document #: 38-05283 Rev. *C Page 19 of 30 CY7C1480V33 CY7C1482V33 CY7C1486V33 PRELIMINARY Thermal Resistance[14] Parameter Description ΘJA Thermal Resistance (Junction to Ambient) ΘJC Thermal Resistance (Junction to Case) Test Conditions Test conditions follow standard test methods and procedures for measuring thermal impedance, per EIA / JESD51. TQFP Package 209-BGA Package fBGA Package Unit 24.63 15.2 16.3 °C/W 2.28 1.7 2.1 °C/W Capacitance[14] Parameter CADDRESS Description Test Conditions TQFP Max. 209-BGA Max. 165-fBGA Max. Unit 6 6 6 pF CCTRL Address Input Capacitance TA = 25°C, f = 1 MHz, VDD = 3.3V Data Input Capacitance VDDQ = 2.5V Control Input Capacitance CCLK Clock Input Capacitance 6 6 6 pF CI/O Input/Output Capacitance 5 5 5 pF CDATA 5 5 5 pF 8 8 8 pF AC Test Loads and Waveforms 3.3V I/O Test Load R = 317Ω 3.3V OUTPUT ALL INPUT PULSES VDDQ OUTPUT RL = 50Ω Z0 = 50Ω 10% 90% 10% 90% GND 5 pF R = 351Ω ≤ 1ns ≤ 1ns VL = 1.5V INCLUDING JIG AND SCOPE (a) (c) (b) 2.5V I/O Test Load R = 1667Ω 2.5V OUTPUT Z0 = 50Ω 10% R =1538Ω VL = 1.25V INCLUDING JIG AND SCOPE 90% 10% 90% GND 5 pF (a) ALL INPUT PULSES VDDQ OUTPUT RL = 50Ω (b) ≤ 1ns ≤ 1ns (c) Note: 14. Tested initially and after any design or process change that may affect these parameters. Document #: 38-05283 Rev. *C Page 20 of 30 CY7C1480V33 CY7C1482V33 CY7C1486V33 PRELIMINARY Switching Characteristics Over the Operating Range[19, 20] 250 MHz Parameter tPOWER Description Min. [15] VDD(Typical) to the first access Max. 200 MHz Min. Max. 167 MHz Min. Max. Unit 1 1 1 ms Clock tCYC Clock Cycle Time 4.0 5.0 6.0 ns tCH Clock HIGH 2.0 2.0 2.4 ns tCL Clock LOW 2.0 2.0 2.4 ns Output Times tCO Data Output Valid After CLK Rise tDOH Data Output Hold After CLK Rise 1.3 1.3 1.5 ns tCLZ Clock to Low-Z[16, 17, 18] 1.3 1.3 1.5 ns tCHZ Clock to High-Z[16, 17, 18] tOEV OE LOW to Output Valid tOELZ OE LOW to Output Low-Z[16, 17, 18] tOEHZ OE HIGH to Output 3.0 3.0 3.0 3.0 3.0 0 High-Z[16, 17, 18] 3.4 3.0 0 3.0 3.4 ns 3.4 ns 0 3.0 ns ns 3.4 ns Set-up Times tAS Address Set-up Before CLK Rise 1.4 1.4 1.5 ns tADS ADSC, ADSP Set-up Before CLK Rise 1.4 1.4 1.5 ns tADVS ADV Set-up Before CLK Rise 1.4 1.4 1.5 ns tWES GW, BWE, BWX Set-up Before CLK Rise 1.4 1.4 1.5 ns tDS Data Input Set-up Before CLK Rise 1.4 1.4 1.5 ns tCES Chip Enable Set-Up Before CLK Rise 1.4 1.4 1.5 ns tAH Address Hold After CLK Rise 0.4 0.4 0.5 ns tADH ADSP, ADSC Hold After CLK Rise 0.4 0.4 0.5 ns tADVH ADV Hold After CLK Rise 0.4 0.4 0.5 ns tWEH GW, BWE, BWX Hold After CLK Rise 0.4 0.4 0.5 ns tDH Data Input Hold After CLK Rise 0.4 0.4 0.5 ns tCEH Chip Enable Hold After CLK Rise 0.4 0.4 0.5 ns Hold Times Shaded areas contain advance information. Notes: 15. This part has a voltage regulator internally; tPOWER is the time that the power needs to be supplied above VDD(minimum) initially before a read or write operation can be initiated. 16. tCHZ, tCLZ,tOELZ, and tOEHZ are specified with AC test conditions shown in part (b) of AC Test Loads. Transition is measured ± 200 mV from steady-state voltage. 17. At any given voltage and temperature, tOEHZ is less than tOELZ and tCHZ is less than tCLZ to eliminate bus contention between SRAMs when sharing the same data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed to achieve High-Z prior to Low-Z under the same system conditions 18. This parameter is sampled and not 100% tested. 19. Timing reference level is 1.5V when VDDQ = 3.3V and is 1.25V when VDDQ = 2.5V. 20. Test conditions shown in (a) of AC Test Loads unless otherwise noted. Document #: 38-05283 Rev. *C Page 21 of 30 CY7C1480V33 CY7C1482V33 CY7C1486V33 PRELIMINARY Switching Waveforms Read Cycle Timing[21] t CYC CLK t CH t ADS t CL t ADH ADSP tADS tADH ADSC tAS tAH A1 ADDRESS A2 tWES A3 Burst continued with new base address tWEH GW, BWE, BWx tCES Deselect cycle tCEH CE tADVS tADVH ADV ADV suspends burst. OE t OEHZ t CLZ Data Out (Q) Q(A1) High-Z tOEV tCO t OELZ tDOH Q(A2) t CHZ Q(A2 + 1) Q(A2 + 2) Q(A2 + 3) Q(A2) Q(A2 + 1) t CO Burst wraps around to its initial state Single READ BURST READ DON’T CARE UNDEFINED Note: 21. On this diagram, when CE is LOW: CE1 is LOW, CE2 is HIGH and CE3 is LOW. When CE is HIGH: CE1 is HIGH or CE2 is LOW or CE3 is HIGH. Document #: 38-05283 Rev. *C Page 22 of 30 CY7C1480V33 CY7C1482V33 CY7C1486V33 PRELIMINARY Switching Waveforms (continued) Write Cycle Timing[21, 22] t CYC CLK tCH tADS tCL tADH ADSP tADS ADSC extends burst tADH tADS tADH ADSC tAS tAH A1 ADDRESS A2 A3 Byte write signals are ignored for first cycle when ADSP initiates burst tWES tWEH BWE, BWX tWES tWEH GW tCES tCEH CE t t ADVS ADVH ADV ADV suspends burst OE tDS Data In (D) High-Z t OEHZ tDH D(A1) D(A2) D(A2 + 1) D(A2 + 1) D(A2 + 2) D(A2 + 3) D(A3) D(A3 + 1) D(A3 + 2) Data Out (Q) BURST READ Single WRITE BURST WRITE DON’T CARE Extended BURST WRITE UNDEFINED Note: 22. Full width write can be initiated by either GW LOW; or by GW HIGH, BWE LOW and BWX LOW. Document #: 38-05283 Rev. *C Page 23 of 30 CY7C1480V33 CY7C1482V33 CY7C1486V33 PRELIMINARY Switching Waveforms (continued) Read/Write Cycle Timing[21, 23, 24] tCYC CLK tCL tCH tADS tADH tAS tAH ADSP ADSC ADDRESS A1 A2 A3 A4 A5 A6 D(A5) D(A6) tWES tWEH BWE, BWX tCES tCEH CE ADV OE tDS tCO tDH tOELZ Data In (D) High-Z tCLZ Data Out (Q) High-Z Q(A1) Back-to-Back READs tOEHZ D(A3) Q(A2) Q(A4) Single WRITE Q(A4+1) Q(A4+2) BURST READ DON’T CARE Q(A4+3) Back-to-Back WRITEs UNDEFINED Notes: 23. The data bus (Q) remains in high-Z following a WRITE cycle, unless a new read access is initiated by ADSP or ADSC. 24. GW is HIGH. Document #: 38-05283 Rev. *C Page 24 of 30 CY7C1480V33 CY7C1482V33 CY7C1486V33 PRELIMINARY Switching Waveforms (continued) ZZ Mode Timing[27, 28] CLK t ZZ ZZ I t ZZREC t ZZI SUPPLY I DDZZ t RZZI ALL INPUTS (except ZZ) Outputs (Q) DESELECT or READ Only High-Z DON’T CARE Notes: 25. Device must be deselected when entering ZZ mode. See Cycle Descriptions table for all possible signal conditions to deselect the device. 26. DQs are in high-Z when exiting ZZ sleep mode. Document #: 38-05283 Rev. *C Page 25 of 30 PRELIMINARY CY7C1480V33 CY7C1482V33 CY7C1486V33 Ordering Information Speed (MHz) 250 200 167 Ordering Code CY7C1480V33-250AXC CY7C1482V33-250AXC Package Name A101 Part and Package Type Lead-Free 100-lead 14 × 20 × 1.4 mm Thin Quad Flat Pack CY7C1486V33-250BGC BB209A 209-ball BGA (14 × 22 × 1.76 mm) CY7C1480V33-250BZC CY7C1482V33-250BZC BB165C 165 fBGA(15 x 17 x1.4 mm) CY7C1486V33-250BGXC BB209A Lead-Free 209-ball BGA (14 × 22 × 1.76 mm) CY7C1480V33-250BZXC CY7C1482V33-250BZXC BB165C Lead-Free 165 fBGA(15 x 17 x1.4 mm) CY7C1480V33-200AXC CY7C1482V33-200AXC A101 BB209A 209-ball BGA (14 × 22 × 1.76 mm) CY7C1480V33-200BZC CY7C1482V33-200BZC BB165C 165 fBGA(15 x 17 x1.4 mm) CY7C1486V33-200BGXC BB209A Lead-Free 209-ball BGA (14 × 22 × 1.76 mm) CY7C1480V33-200BZXC CY7C1482V33-200BZXC BB165C Lead-Free 165 fBGA(15 x 17 x1.4 mm) A101 Commercial Lead-Free 100-lead 14 × 20 × 1.4 mm Thin Quad Flat Pack CY7C1486V33-200BGC CY7C1480V33-167AXC CY7C1482V33-167AXC Operating Range Lead-Free 100-lead 14 × 20 × 1.4 mm Thin Quad Flat Pack CY7C1486V33-167BGC BB209A 209-ball BGA (14 × 22 × 1.76 mm) CY7C1480V33-167BZC CY7C1482V33-167BZC BB165C 165 fBGA(15 x 17x1.4 mm) CY7C1486V33-167BGXC BB209A Lead-Free 209-ball BGA (14 × 22 × 1.76 mm) CY7C1480V33-167BZXC CY7C1482V33-167BZXC BB165C Lead-Free 165 fBGA(15 x 17x1.4 mm) Shaded areas contain advance information. Please contact your local sales representative for availability of these parts. Lead-free BG packages (Ordering Code: BGX) will be available in 2005. Notes: 27. Device must be deselected when entering ZZ mode. See Cycle Descriptions table for all possible signal conditions to deselect the device. 28. DQs are in high-Z when exiting ZZ sleep mode Document #: 38-05283 Rev. *C Page 26 of 30 CY7C1480V33 CY7C1482V33 CY7C1486V33 PRELIMINARY Package Diagrams 100-Pin Thin Plastic Quad Flatpack (14 x 20 x 1.4 mm) A101 DIMENSIONS ARE IN MILLIMETERS. 16.00±0.20 1.40±0.05 14.00±0.10 100 81 80 1 20.00±0.10 22.00±0.20 0.30±0.08 0.65 TYP. 30 12°±1° (8X) SEE DETAIL A 51 31 50 0.20 MAX. 1.60 MAX. 0° MIN. STAND-OFF 0.05 MIN. 0.15 MAX. 0.25 0.10 R 0.08 MIN. 0.20 MAX. SEATING PLANE GAUGE PLANE 0°-7° R 0.08 MIN. 0.20 MAX. 0.60±0.15 0.20 MIN. 1.00 REF. DETAIL Document #: 38-05283 Rev. *C A 51-85050-*A Page 27 of 30 PRELIMINARY CY7C1480V33 CY7C1482V33 CY7C1486V33 Package Diagrams (continued) 209-Ball FBGA (14 x 22 x 1.76 mm) BB209A 51-85167-** Document #: 38-05283 Rev. *C Page 28 of 30 CY7C1480V33 CY7C1482V33 CY7C1486V33 PRELIMINARY Package Diagrams (continued) 165-Ball FBGA (15 x 17 x 1.40 mm) BB165C PIN 1 CORNER BOTTOM VIEW TOP VIEW Ø0.05 M C PIN 1 CORNER Ø0.25 M C A B Ø0.45±0.05(165X) 1 2 3 4 5 6 7 8 9 10 11 11 10 9 8 7 6 5 4 3 2 1 A B B C C 1.00 A D D F F G G H J 14.00 E 17.00±0.10 E H J K L L 7.00 K M M N N P P R R A 1.00 5.00 0.35 0.15 C +0.05 -0.10 0.53±0.05 0.25 C 10.00 B 15.00±0.10 0.15(4X) SEATING PLANE 1.40 MAX. 0.36 C 51-85165-*A i486 is a trademark, and Intel and Pentium are registered trademarks of Intel Corporation. PowerPC is a trademark of IBM Corporation. All product and company names mentioned in this document are the trademarks of their respective holders. Document #: 38-05283 Rev. *C Page 29 of 30 © Cypress Semiconductor Corporation, 2004. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. CY7C1480V33 CY7C1482V33 CY7C1486V33 PRELIMINARY Document History Page Document Title: CY7C1480V33/CY7C1482V33/CY7C1486V3372-Mbit (2M x 36/4M x 18/1M x 72) Pipelined Sync SRAM Document Number: 38-05283 REV. ECN NO. Issue Date Orig. of Change Description of Change ** 114670 08/06/02 PKS New Data Sheet *A 118281 01/21/03 HGK Changed tCO from 2.4 to 2.6 ns for 250 MHz Updated features on page 1 for package offering Removed 30-MHz offering Updated Ordering Information Changed Advanced Information to Preliminary *B 233368 See ECN NJY Changed timing diagrams Changed logic block diagrams Modified Functional Description Modified “Functional Overview” section Added boundary scan order for all packages Included thermal numbers and capacitance values for all packages Included IDD and ISB values Removed 250-MHz speed grade offering and included 225-MHz speed bin Changed package outline for 165FBGA package and 209-ball BGA package Removed 119-BGA package offering *C 299452 See ECN SYT Removed 225-MHz offering and included 250-MHz speed bin Changed tCYC from 4.4 ns to 4.0 ns for 250-MHz Speed Bin Changed ΘJA from 16.8 to 24.63 °C/W and ΘJC from 3.3 to 2.28 °C/W for 100 TQFP Package on Page # 20 Added lead-free information for 100-Pin TQFP, 165 FBGA and 209 BGA Packages. Added comment of ‘Lead-free BG packages availability’ below the Ordering Information Document #: 38-05283 Rev. *C Page 30 of 30