CYPRESS CY7C1020BN-15ZC

CY7C1020BN
32K x 16 Static RAM
Features
Functional Description
• High speed
The CY7C1020BN is a high-performance CMOS static RAM
organized as 32,768 words by 16 bits. This device has an
automatic power-down feature that significantly reduces
power consumption when deselected.
— tAA = 12, 15 ns
• CMOS for optimum speed/power
• Low active power
— 825 mW (max.)
• Low CMOS standby power (L version only)
— 2.75 mW (max.)
• Automatic power-down when deselected
• Independent control of upper and lower bits
• Available in 44-pin TSOP II and 400-mil SOJ
Writing to the device is accomplished by taking Chip Enable
(CE) and Write Enable (WE) inputs LOW. If Byte Low Enable
(BLE) is LOW, then data from I/O pins (I/O1 through I/O8), is
written into the location specified on the address pins (A0
through A15). If Byte High Enable (BHE) is LOW, then data
from I/O pins (I/O9 through I/O16) is written into the location
specified on the address pins (A0 through A15).
Reading from the device is accomplished by taking Chip
Enable (CE) and Output Enable (OE) LOW while forcing the
Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW,
then data from the memory location specified by the address
pins will appear on I/O1 to I/O8. If Byte High Enable (BHE) is
LOW, then data from memory will appear on I/O9 to I/O16. See
the truth table at the back of this data sheet for a complete
description of read and write modes.
The input/output pins (I/O1 through I/O16) are placed in a
high-impedance state when the device is deselected (CE
HIGH), the outputs are disabled (OE HIGH), the BHE and BLE
are disabled (BHE, BLE HIGH), or during a write operation (CE
LOW, and WE LOW).
The CY7C1020BN is available in standard 44-pin TSOP Type
II and 400-mil-wide SOJ packages.
Logic Block Diagram
Pin Configuration
SOJ / TSOP II
Top View
SENSE AMPS
A7
A6
A5
A4
A3
A2
A1
A0
ROW DECODER
DATA IN DRIVERS
32K x 16
RAM Array
I/O1–I/O8
I/O9–I/O16
COLUMN DECODER
A8
A9
A10
A11
A12
A13
A14
BHE
WE
CE
OE
BLE
Cypress Semiconductor Corporation
Document #: 001-06443 Rev. **
•
198 Champion Court
•
NC
A3
A2
A1
A0
CE
I/O1
I/O2
I/O3
I/O4
VCC
VSS
I/O5
I/O6
I/O7
I/O8
WE
A15
A14
A13
A12
NC
1
44
2
3
43
42
4
41
40
39
38
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A5
A6
A7
OE
BHE
BLE
I/O16
I/O15
I/O14
I/O13
VSS
VCC
I/O12
I/O11
I/O10
I/O9
NC
A8
A9
A10
A11
NC
San Jose, CA 95134-1709
•
408-943-2600
Revised February 1, 2006
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CY7C1020BN
Selection Guide
7C1020BN-12
7C1020BN-15
Maximum Access Time (ns)
12
15
Maximum Operating Current (mA)
140
130
Maximum CMOS Standby Current (mA)
L
Maximum Ratings
3
3
0.5
0.5
Current into Outputs (LOW)......................................... 20 mA
(Above which the useful life may be impaired. For user guidelines, not tested.)
Storage Temperature ................................. –65°C to +150°C
Ambient Temperature with
Power Applied............................................. –55°C to +125°C
Static Discharge Voltage............................................ >2001V
(per MIL-STD-883, Method 3015)
Latch-Up Current ..................................................... >200 mA
Operating Range
Supply Voltage on VCC to Relative GND[1] .... –0.5V to +7.0V
DC Voltage Applied to Outputs
in High Z State[1] ......................................–0.5V to VCC+0.5V
DC Input Voltage[1] ...................................–0.5V to VCC+0.5V
Range
Commercial
Industrial
Ambient
Temperature[2]
VCC
0×C to +70×C
5V ± 10%
–40×C to +85×C
5V ± 10%
Electrical Characteristics Over the Operating Range
Parameter
7C1020BN-12
Test
Conditions
Description
Min.
Max.
VOH
Output HIGH Voltage
VCC = Min., IOH = –4.0 mA
VOL
Output LOW Voltage
VCC = Min., IOL = 8.0 mA
VIH
Input HIGH Voltage
2.2
6.0
VIL
Input LOW Voltage[1]
–0.5
0.8
IIX
Input Load Current
GND < VI < VCC
–1
+1
IOZ
Output Leakage Current
GND < VI < VCC, Output Disabled
–1
+1
Current[3]
2.4
7C1020BN-15
Min.
2.4
0.4
VCC = Max., VOUT = GND
Max.
Unit
V
0.4
V
2.2
6.0
V
–0.5
0.8
V
–1
+1
µA
–1
+1
µA
IOS
Output Short Circuit
–300
–300
mA
ICC
VCC Operating Supply Current VCC = Max., IOUT = 0 mA, f = fMAX = 1/tRC
140
130
mA
ISB1
Automatic CE Power-Down
Current—TTL Inputs
Max. VCC, CE > VIH
VIN > VIH or VIN < VIL, f = fMAX
20
20
mA
ISB2
Automatic CE Power-Down
Current—CMOS Inputs
Max. VCC, CE > VCC – 0.3V,
VIN > VCC – 0.3V, or VIN < 0.3V,
f=0
3
3
mA
0.5
0.5
mA
L
Capacitance[4]
Parameter
Description
CIN
Input Capacitance
COUT
Output Capacitance
Test Conditions
TA = 25°C, f = 1 MHz,
VCC = 5.0V
Max.
Unit
8
pF
8
pF
Notes:
1. VIL (min.) = –2.0V for pulse durations of less than 20 ns.
2. TA is the case temperature.
3. Not more than one output should be shorted at one time. Duration of the short circuit should not exceed 30 seconds.
4. Tested initially and after any design or process changes that may affect these parameters.
Document #: 001-06443 Rev. **
Page 2 of 8
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CY7C1020BN
AC Test Loads and Waveforms
R 481Ω
R 481Ω
5V
5V
OUTPUT
ALL INPUT PULSES
3.0V
90%
OUTPUT
30 pF
R2
255Ω
R2
255Ω
5 pF
INCLUDING
JIG AND
SCOPE
(a)
INCLUDING
JIG AND
SCOPE
(b)
167
90%
10%
10%
GND
Rise Time: 1 V/ns
Fall Time: 1 V/ns
1.73V
OUTPUT
Equivalent to: THÉVENIN
EQUIVALENT
30 pF
Switching Characteristics[5] Over the Operating Range
7C1020BN-12
Parameter
Description
Min.
Max.
7C1020BN-15
Min.
Max.
Unit
Read Cycle
tRC
Read Cycle Time
12
tAA
Address to Data Valid
tOHA
Data Hold from Address Change
tACE
CE LOW to Data Valid
12
15
ns
tDOE
OE LOW to Data Valid
6
7
ns
Z[6]
tLZOE
OE LOW to Low
tHZOE
OE HIGH to High Z[6, 7]
tLZCE
CE LOW to Low
Z[6]
CE HIGH to High
tPU
CE LOW to Power-Up
tPD
CE HIGH to Power-Down
tDBE
Byte Enable to Data Valid
tLZBE
Byte Enable to Low Z
tHZBE
Write
12
3
15
3
ns
7
3
6
0
7
6
0
ns
ns
15
ns
7
ns
0
6
ns
ns
0
12
ns
ns
0
6
Byte Disable to High Z
ns
3
0
Z[6, 7]
tHZCE
15
ns
7
ns
Cycle[8]
tWC
Write Cycle Time
12
15
ns
tSCE
CE LOW to Write End
9
10
ns
tAW
Address Set-Up to Write End
8
10
ns
tHA
Address Hold from Write End
0
0
ns
tSA
Address Set-Up to Write Start
0
0
ns
tPWE
WE Pulse Width
8
10
ns
tSD
Data Set-Up to Write End
6
8
ns
tHD
Data Hold from Write End
0
0
ns
3
3
ns
tLZWE
[6]
WE HIGH to Low Z
[6, 7]
tHZWE
WE LOW to High Z
tBW
Byte Enable to End of Write
6
8
7
9
ns
ns
Notes:
5. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
IOL/IOH and 30-pF load capacitance.
6. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device.
7. tHZOE, tHZBE, tHZCE, and tHZWE are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured ±500 mV from steady-state
voltage.
8. The internal write time of the memory is defined by the overlap of CE LOW, WE LOW and BHE / BLE LOW. CE, WE and BHE / BLE must be LOW to initiate
a write, and the transition of these signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal
that terminates the write.
Document #: 001-06443 Rev. **
Page 3 of 8
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CY7C1020BN
Switching Waveforms
Read Cycle No. 1[9, 10]
tRC
ADDRESS
tAA
tOHA
DATA OUT
PREVIOUS DATA VALID
DATA VALID
Read Cycle No. 2 (OE Controlled)[10, 11]
ADDRESS
tRC
CE
tACE
OE
tHZOE
tDOE
BHE, BLE
tLZOE
tHZCE
tDBE
tLZBE
DATA OUT
HIGH IMPEDANCE
tLZCE
VCC
SUPPLY
CURRENT
tHZBE
HIGH
IMPEDANCE
DATA VALID
tPD
tPU
50%
IICC
CC
50%
IISB
SB
Notes:
9. Device is continuously selected. OE, CE, BHE and/or BHE = VIL.
10. WE is HIGH for read cycle.
11. Address valid prior to or coincident with CE transition LOW.
Document #: 001-06443 Rev. **
Page 4 of 8
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CY7C1020BN
Switching Waveforms (continued)
Write Cycle No. 1 (CE Controlled)[12, 13]
tWC
ADDRESS
CE
tSA
tSCE
tAW
tHA
tPWE
WE
tBW
BHE, BLE
tSD
tHD
DATA I/O
Write Cycle No. 2 (BLE or BHE Controlled)
tWC
ADDRESS
BHE, BLE
tSA
tBW
tAW
tHA
tPWE
WE
tSCE
CE
tSD
tHD
DATA I/O
Notes:
12. Data I/O is high impedance if OE or BHE and/or BLE= VIH.
13. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state.
Document #: 001-06443 Rev. **
Page 5 of 8
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CY7C1020BN
Switching Waveforms (continued)
Write Cycle No. 3 (WE Controlled, OE LOW)
tWC
ADDRESS
tSCE
CE
tAW
tHA
tSA
tPWE
WE
tBW
BHE, BLE
tHZWE
tSD
tHD
DATA I/O
tLZWE
Truth Table
CE
OE
WE
H
X
L
L
L
X
BLE
BHE
X
X
X
High Z
High Z
Power-Down
Standby (ISB)
H
L
L
Data Out
Data Out
Read – All bits
Active (ICC)
L
H
Data Out
High Z
Read – Lower bits only
Active (ICC)
H
L
High Z
Data Out
Read – Upper bits only
Active (ICC)
L
L
Data In
Data In
Write – All bits
Active (ICC)
L
H
Data In
High Z
Write – Lower bits only
Active (ICC)
H
L
High Z
Data In
Write – Upper bits only
Active (ICC)
L
I/O1–I/O8
I/O9–I/O16
Mode
Power
L
H
H
X
X
High Z
High Z
Selected, Outputs Disabled
Active (ICC)
L
X
X
H
H
High Z
High Z
Selected, Outputs Disabled
Active (ICC)
Ordering Information
Speed
(ns)
12
15
Ordering Code
Package
Diagram
Package Type
Operating
Range
CY7C1020BN-12VC
51-85082
44-Lead (400-Mil) Molded SOJ
Commercial
CY7C1020BN-12VXC
51-85082
44-Lead (400-Mil) Molded SOJ (Pb-free)
Commercial
CY7C1020BN-12ZC
51-85087
44-pin TSOP Type II
Commercial
CY7C1020BN-12ZXC
51-85087
44-pin TSOP Type II (Pb-free)
Commercial
CY7C1020BN-15ZC
51-85087
44-pin TSOP Type II
Commercial
CY7C1020BN-15ZXC
51-85087
44-pin TSOP Type II (Pb-free)
Commercial
Please contact local sales representative regarding availability of these parts.
Document #: 001-06443 Rev. **
Page 6 of 8
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CY7C1020BN
Package Diagrams
44-Lead (400-Mil) Molded SOJ (51-85082)
51-85082-*B
44-Pin TSOP II (51-85087)
51-85087-*A
All product and company names mentioned in this document may be the trademarks of their respective holders.
Document #: 001-06443 Rev. **
Page 7 of 8
© Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
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CY7C1020BN
Document History Page
Document Title: CY7C1020BN 32K x 16 Static RAM
Document #: 001-06443
REV.
**
ECN NO.
426812
Issue
Date
See ECN
Document #: 001-06443 Rev. **
Orig. of
Change
NXR
Description of Change
New Data Sheet
Page 8 of 8
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