CY7C1370C CY7C1372C 512K x 36/1M x 18 Pipelined SRAM with NoBL™ Architecture Features Functional Description • Pin-compatible and functionally equivalent to ZBT™ • Supports 250-MHz bus operations with zero wait states — Available speed grades are 250, 225, 200 and 167 MHz • Internally self-timed output buffer control to eliminate the need to use asynchronous OE • Fully registered (inputs and outputs) for pipelined operation • Byte Write capability The CY7C1370C and CY7C1372C are 3.3V, 512K x 36 and 1M x 18 Synchronous pipelined burst SRAMs with No Bus Latency™ (NoBL) logic, respectively. They are designed to support unlimited true back-to-back Read/Write operations with no wait states. The CY7C1370C and CY7C1372C are equipped with the advanced (NoBL) logic required to enable consecutive Read/Write operations with data being transferred on every clock cycle. This feature dramatically improves the throughput of data in systems that require frequent Write/Read transitions. The CY7C1370C and CY7C1372C are pin compatible and functionally equivalent to ZBT devices. All synchronous inputs pass through input registers controlled by the rising edge of the clock. All data outputs pass through output registers controlled by the rising edge of the clock. The clock input is qualified by the Clock Enable (CEN) signal, which when deasserted suspends operation and extends the previous clock cycle. • Single 3.3V power supply • 3.3V/2.5V I/O power supply • Fast clock-to-output times — 2.6 ns (for 250-MHz device) — 2.8 ns (for 225-MHz device) Write operations are controlled by the Byte Write Selects (BWa–BWd for CY7C1370C and BWa–BWb for CY7C1372C) and a Write Enable (WE) input. All writes are conducted with on-chip synchronous self-timed write circuitry. — 3.0 ns (for 200-MHz device) — 3.4 ns (for 167-MHz device) • Clock Enable (CEN) pin to suspend operation • Synchronous self-timed writes • Available in 100 TQFP, 119 BGA, and 165 fBGA packages • IEEE 1149.1 JTAG Boundary Scan Three synchronous Chip Enables (CE1, CE2, CE3) and an asynchronous Output Enable (OE) provide for easy bank selection and output three-state control. In order to avoid bus contention, the output drivers are synchronously three-stated during the data portion of a write sequence. • Burst capability—linear or interleaved burst order • “ZZ” Sleep Mode option and Stop Clock option Logic Block Diagram-CY7C1370C (512K x 36) A0, A1, A ADDRESS REGISTER 0 A1 A1' D1 Q1 A0 A0' BURST D0 Q0 LOGIC MODE CLK CEN ADV/LD C C WRITE ADDRESS REGISTER 1 WRITE ADDRESS REGISTER 2 S E N S E ADV/LD BWa BWb BWc BWd WRITE REGISTRY AND DATA COHERENCY CONTROL LOGIC WRITE DRIVERS MEMORY ARRAY A M P S WE O U T P U T R E G I S T E R S E INPUT REGISTER 1 OE CE1 CE2 CE3 ZZ Cypress Semiconductor Corporation Document #: 38-05233 Rev. *D E O U T P U T D A T A S T E E R I N G INPUT REGISTER 0 B U F F E R S DQs DQPa DQPb DQPc DQPd E E READ LOGIC SLEEP CONTROL • 3901 North First Street • San Jose, CA 95134 • 408-943-2600 Revised June 03, 2004 CY7C1370C CY7C1372C Logic Block Diagram-CY7C1372C (1M x 18) A0, A1, A ADDRESS REGISTER 0 A1 A1' D1 Q1 A0 A0' BURST D0 Q0 LOGIC MODE CLK CEN ADV/LD C C WRITE ADDRESS REGISTER 1 WRITE ADDRESS REGISTER 2 ADV/LD BWa WRITE REGISTRY AND DATA COHERENCY CONTROL LOGIC WRITE DRIVERS MEMORY ARRAY BWb WE S E N S E A M P S O U T P U T D A T A R E G I S T E R S S T E E R I N G E INPUT REGISTER 1 E OE CE1 CE2 CE3 ZZ O U T P U T B U F F E R S DQs DQPa DQPb E INPUT REGISTER 0 E READ LOGIC Sleep Control Selection Guide CY7C1370C-250 CY7C1370C-225 CY7C1370C-200 CY7C1370C-167 CY7C1372C-250 CY7C1372C-225 CY7C1372C-200 CY7C1372C-167 Maximum Access Time Maximum Operating Current Maximum CMOS Standby Current 2.6 350 70 2.8 325 70 3.0 300 70 3.4 275 70 Unit ns mA mA Shaded areas contain advance information. Please contact your local Cypress sales representative for availability of these parts. Document #: 38-05233 Rev. *D Page 2 of 27 CY7C1370C CY7C1372C Pin Configurations 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 NC DQPb NC DQb NC DQb VDDQ VDDQ VSS VSS NC DQb DQb NC DQb DQb DQb DQb VSS VSS VDDQ V DDQ CY7C1372C (1M × 18) 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 Document #: 38-05233 Rev. *D A NC NC VDDQ VSS NC DQPa DQa DQa VSS VDDQ DQa DQa VSS NC VDD ZZ DQa DQa VDDQ VSS DQa DQa NC NC VSS VDDQ NC NC NC A A A A A A A E(36) E(72) VSS VDD E(288) E(144) A A A A A A A E(36) E(72) VSS VDD 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 DQb DQb DQb DQb NC VSS VDD NC NC VDD VSS ZZ DQb DQa DQa DQb VDDQ VDDQ VSS VSS DQa DQb DQa DQb DQa DQPb NC DQa VSS VSS VDDQ VDDQ NC DQa DQa NC DQPa NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 MODE A A A A A1 A0 CY7C1370C (512K × 36) E(288) E(144) DQc DQc NC VDD NC VSS DQd DQd VDDQ VSS DQd DQd DQd DQd VSS VDDQ DQd DQd DQPd 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 VSS DQc DQc DQc DQc VSS VDDQ 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 MODE A A A A A1 A0 DQPc DQc DQc VDDQ A A A A CE1 CE2 NC NC BWb BWa CE3 VDD VSS CLK WE CEN OE ADV/LD A A A A 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 A A CE1 CE2 BWd BWc BWb BWa CE3 VDD VSS CLK WE CEN OE ADV/LD A A 100-pin TQFP Packages Page 3 of 27 CY7C1370C CY7C1372C Pin Configurations (continued) 119-ball BGA Pinout CY7C1370C (512K × 36) – 14 × 22 BGA 1 2 3 4 5 6 7 A VDDQ A A A A A VDDQ B C D E F G H J K L M N P NC NC DQc CE2 A DQPc A A VSS ADV/LD VDD NC A A VSS CE3 A DQPb NC NC DQb DQc DQc VSS CE1 VSS DQb DQb OE A VSS DQb VDDQ BWb DQb DQb WE VDD VSS NC DQb VDD DQb VDDQ CLK NC VSS BWa DQa DQa DQa DQa VDDQ R T U VDDQ DQc VSS DQc DQc DQc VDDQ DQc VDD BWc VSS NC DQd DQd DQd DQd BWd VDDQ DQd VSS DQa DQd VSS CEN A1 VSS DQd VSS DQa DQa DQd DQPd VSS A0 VSS DQPa DQa NC A MODE VDD NC E(72) A A NC A A NC E(36) ZZ VDDQ TMS TDI TCK TDO NC VDDQ VSS CY7C1372C (1M x 18)–14 x 22 BGA A B C D E F G H J K L M N P R T U Document #: 38-05233 Rev. *D 1 2 3 4 5 6 7 VDDQ A A A A A VDDQ NC CE2 A A NC A VSS ADV/LD VDD NC A NC DQb A VSS CE3 A DQPa NC NC CE1 VSS NC DQa OE A VSS DQa VDDQ VSS VSS NC NC DQa VDD DQa NC VDDQ DQa NC DQb VSS VDDQ NC VSS NC DQb VDDQ DQb NC VDD BWb VSS NC WE VDD NC NC DQb VSS CLK VSS NC DQb NC VSS NC DQa NC VDDQ DQb VSS NC VDDQ DQb NC VSS CEN A1 BWa VSS VSS DQa NC NC DQPb VSS A0 VSS NC DQa NC NC A MODE VDD NC A E(72) A A E(36) A A ZZ VDDQ TMS TDI TCK TDO NC VDDQ Page 4 of 27 CY7C1370C CY7C1372C Pin Configurations (continued) 165-Ball fBGA Pinout 1 2 A B C D E F G H J K L M N P E(288) A R CY7C1370C (512K × 36) – 13 × 15 fBGA 3 4 5 6 7 8 9 10 11 ADV/LD A A NC CLK CEN WE OE A A E(144) VSS VSS VSS VDD VDDQ VSS VSS VSS VDDQ NC DQb DQPb DQb CE1 BWc BWb CE3 BWd VSS VDD BWa VSS NC A CE2 DQPc DQc NC DQc VDDQ VDDQ DQc DQc VDDQ VDD VSS VSS VSS VDD VDDQ DQb DQb DQc DQc VDDQ VDD VSS VSS VSS VDD VDDQ DQb DQb DQc NC DQd DQc NC / VDD DQd VDDQ NC VDDQ VDD VDD VDD VSS VSS VSS VSS VSS VSS VSS VSS VSS VDD VDD VDD VDDQ NC VDDQ DQb NC DQa DQb ZZ DQa DQd DQd VDDQ VDD VSS VSS VSS VDD VDDQ DQa DQa DQd DQd VDDQ VDD VSS VSS VSS VDD VDDQ DQa DQa DQd DQPd DQd NC VDDQ VDDQ VDD VSS VSS NC VSS NC VSS NC VDD VSS VDDQ VDDQ DQa NC DQa DQPa NC E(72) A A TDI A1 TDO A A A NC MODE E(36) A A TMS A0 TCK A A A A 8 9 10 11 A A A CY7C1372C (1M × 18) – 13 × 15 fBGA 1 2 3 4 5 6 A B C D E F G H J K L M N P E(288) A CE1 BWb NC CE3 CEN ADV/LD NC BWa CLK VSS VDD VSS VSS VSS VSS WE VSS VSS OE VSS R NC A CE2 NC NC NC DQb VDDQ VDDQ 7 A A E(144) VDD VDDQ VDDQ NC NC DQPa DQa NC DQb VDDQ VDD VSS VSS VSS VDD VDDQ NC DQa NC DQb VDDQ VDD VSS VSS VSS VDD VDDQ NC DQa NC NC DQb DQb NC / VDD NC VDDQ NC VDDQ VDD VDD VDD VSS VSS VSS VSS VSS VSS VSS VSS VSS VDD VDD VDD VDDQ NC VDDQ NC NC DQa DQa ZZ NC DQb NC VDDQ VDD VSS VSS VSS VDD VDDQ DQa NC DQb NC VDDQ VDD VSS VSS VSS VDD VDDQ DQa NC DQb DQPb NC NC VDDQ VDDQ VDD VSS VSS NC VSS NC VSS NC VDD VSS VDDQ VDDQ DQa NC NC NC NC E(72) A A TDI A1 TDO A A A NC MODE E(36) A A TMS A0 TCK A A A A Document #: 38-05233 Rev. *D Page 5 of 27 CY7C1370C CY7C1372C Pin Definitions Pin Name I/O Type Pin Description A0 A1 A InputSynchronous Address Inputs used to select one of the address locations. Sampled at the rising edge of the CLK. BWa BWb BWc BWd InputSynchronous Byte Write Select Inputs, active LOW. Qualified with WE to conduct writes to the SRAM. Sampled on the rising edge of CLK. BWa controls DQa and DQPa, BWb controls DQb and DQPb, BWc controls DQc and DQPc, BWd controls DQd and DQPd. WE InputSynchronous Write Enable Input, active LOW. Sampled on the rising edge of CLK if CEN is active LOW. This signal must be asserted LOW to initiate a write sequence. ADV/LD InputSynchronous Advance/Load Input used to advance the on-chip address counter or load a new address. When HIGH (and CEN is asserted LOW) the internal burst counter is advanced. When LOW, a new address can be loaded into the device for an access. After being deselected, ADV/LD should be driven LOW in order to load a new address. CLK InputClock Clock Input. Used to capture all synchronous inputs to the device. CLK is qualified with CEN. CLK is only recognized if CEN is active LOW. CE1 InputSynchronous Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE2 and CE3 to select/deselect the device. CE2 InputSynchronous Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction with CE1 and CE3 to select/deselect the device. CE3 InputSynchronous Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE1 and CE2 to select/deselect the device. OE InputAsynchronous Output Enable, active LOW. Combined with the synchronous logic block inside the device to control the direction of the I/O pins. When LOW, the I/O pins are allowed to behave as outputs. When deasserted HIGH, I/O pins are three-stated, and act as input data pins. OE is masked during the data portion of a write sequence, during the first clock when emerging from a deselected state and when the device has been deselected. CEN InputSynchronous Clock Enable Input, active LOW. When asserted LOW the clock signal is recognized by the SRAM. When deasserted HIGH the clock signal is masked. Since deasserting CEN does not deselect the device, CEN can be used to extend the previous cycle when required. DQa DQb DQc DQd I/OSynchronous Bidirectional Data I/O lines. As inputs, they feed into an on-chip data register that is triggered by the rising edge of CLK. As outputs, they deliver the data contained in the memory location specified by A[17:0] during the previous clock rise of the read cycle. The direction of the pins is controlled by OE and the internal control logic. When OE is asserted LOW, the pins can behave as outputs. When HIGH, DQa–DQd are placed in a three-state condition. The outputs are automatically three-stated during the data portion of a write sequence, during the first clock when emerging from a deselected state, and when the device is deselected, regardless of the state of OE. DQPa DQPb DQPc DQPd I/OSynchronous Bidirectional Data Parity I/O lines. Functionally, these signals are identical to DQ[31:0]. During write sequences, DQPa is controlled by BWa, DQPb is controlled by BWb, DQPc is controlled by BWc, and DQPd is controlled by BWd. MODE Input Strap Pin Mode Input. Selects the burst order of the device. Tied HIGH selects the interleaved burst order. Pulled LOW selects the linear burst order. MODE should not change states during operation. When left floating MODE will default HIGH, to an interleaved burst order. TDO JTAG serial output Serial data-out to the JTAG circuit. Delivers data on the negative edge of TCK. Synchronous TDI JTAG serial input Serial data-In to the JTAG circuit. Sampled on the rising edge of TCK. Synchronous TMS Test Mode Select This pin controls the Test Access Port state machine. Sampled on the rising edge of TCK. Synchronous TCK JTAG-Clock VDD Power Supply VDDQ Clock input to the JTAG circuitry. Power supply inputs to the core of the device. I/O Power Supply Power supply for the I/O circuitry. Document #: 38-05233 Rev. *D Page 6 of 27 CY7C1370C CY7C1372C Pin Definitions (continued) Pin Name I/O Type VSS Ground Pin Description Ground for the device. Should be connected to ground of the system. NC – No connects. This pin is not connected to the die. NC / VDD E(36,72, 144, 288) – – Can either be left unconnected or connected to VDD. Must not be connected to VSS. These pins are not connected. They will be used for expansion to the 36M, 72M, 144M and 288M densities. ZZ InputAsynchronous ZZ “sleep” Input. This active HIGH input places the device in a non-time critical “sleep” condition with data integrity preserved. During normal operation, this pin can be connected to Vss or left floating. Functional Overview The CY7C1370C and CY7C1372C are synchronous-pipelined Burst NoBL SRAMs designed specifically to eliminate wait states during Write/Read transitions. All synchronous inputs pass through input registers controlled by the rising edge of the clock. The clock signal is qualified with the Clock Enable input signal (CEN). If CEN is HIGH, the clock signal is not recognized and all internal states are maintained. All synchronous operations are qualified with CEN. All data outputs pass through output registers controlled by the rising edge of the clock. Maximum access delay from the clock rise (tCO) is 3.0 ns (200-MHz device). Accesses can be initiated by asserting all three Chip Enables (CE1, CE2, CE3) active at the rising edge of the clock. If Clock Enable (CEN) is active LOW and ADV/LD is asserted LOW, the address presented to the device will be latched. The access can either be a read or write operation, depending on the status of the Write Enable (WE). BW[a:d] can be used to conduct byte write operations. Write operations are qualified by the Write Enable (WE). All writes are simplified with on-chip synchronous self-timed write circuitry. Three synchronous Chip Enables (CE1, CE2, CE3) and an asynchronous Output Enable (OE) simplify depth expansion. All operations (Reads, Writes, and Deselects) are pipelined. ADV/LD should be driven LOW once the device has been deselected in order to load a new address for the next operation. Single Read Accesses A read access is initiated when the following conditions are satisfied at clock rise: (1) CEN is asserted LOW, (2) CE1, CE2, and CE3 are ALL asserted active, (3) the Write Enable input signal WE is deasserted HIGH, and (4) ADV/LD is asserted LOW. The address presented to the address inputs is latched into the Address Register and presented to the memory core and control logic. The control logic determines that a read access is in progress and allows the requested data to propagate to the input of the output register. At the rising edge of the next clock the requested data is allowed to propagate through the output register and onto the data bus within 3.2 ns (200-MHz device) provided OE is active LOW. After the first clock of the read access the output buffers are controlled by OE and the internal control logic. OE must be driven LOW in order for the device to drive out the requested data. During the second clock, a subsequent operation (Read/Write/Deselect) can be initiated. Deselecting the device is also pipelined. Therefore, when the SRAM is deselected at clock rise by one Document #: 38-05233 Rev. *D of the chip enable signals, its output will three-state following the next clock rise. Burst Read Accesses The CY7C1370C and CY7C1372C have an on-chip burst counter that allows the user the ability to supply a single address and conduct up to four Reads without reasserting the address inputs. ADV/LD must be driven LOW in order to load a new address into the SRAM, as described in the Single Read Access section above. The sequence of the burst counter is determined by the MODE input signal. A LOW input on MODE selects a linear burst mode, a HIGH selects an interleaved burst sequence. Both burst counters use A0 and A1 in the burst sequence, and will wrap-around when incremented sufficiently. A HIGH input on ADV/LD will increment the internal burst counter regardless of the state of chip enables inputs or WE. WE is latched at the beginning of a burst cycle. Therefore, the type of access (Read or Write) is maintained throughout the burst sequence. Single Write Accesses Write access are initiated when the following conditions are satisfied at clock rise: (1) CEN is asserted LOW, (2) CE1, CE2, and CE3 are ALL asserted active, and (3) the write signal WE is asserted LOW. The address presented to A0–A16 is loaded into the Address Register. The write signals are latched into the Control Logic block. On the subsequent clock rise the data lines are automatically three-stated regardless of the state of the OE input signal. This allows the external logic to present the data on DQ and DQP (DQa,b,c,d/DQPa,b,c,d for CY7C1370C and DQa,b/DQPa,b for CY7C1372C). In addition, the address for the subsequent access (Read/Write/Deselect) is latched into the Address Register (provided the appropriate control signals are asserted). On the next clock rise the data presented to DQ and DQP (DQa,b,c,d/DQPa,b,c,d for CY7C1370C & DQa,b/DQPa,b for CY7C1372C) (or a subset for byte write operations, see Write Cycle Description table for details) inputs is latched into the device and the write is complete. The data written during the Write operation is controlled by BW (BWa,b,c,d for CY7C1370C and BWa,b for CY7C1372C) signals. The CY7C1370C/CY7C1372C provides byte write capability that is described in the Write Cycle Description table. Asserting the Write Enable input (WE) with the selected Byte Write Select (BW) input will selectively write to only the desired bytes. Bytes not selected during a byte write operation will remain unaltered. A synchronous self-timed write mechanism has been provided to simplify the write operations. Byte write Page 7 of 27 CY7C1370C CY7C1372C capability has been included in order to greatly simplify Read/Modify/Write sequences, which can be reduced to simple byte write operations. Because the CY7C1370C and CY7C1372C are common I/O devices, data should not be driven into the device while the outputs are active. The Output Enable (OE) can be deasserted HIGH before presenting data to the DQ and DQP (DQa,b,c,d/DQPa,b,c,d for CY7C1370C and DQa,b/DQPa,b for CY7C1372C) inputs. Doing so will three-state the output drivers. As a safety precaution, DQ and DQP (DQa,b,c,d/ DQPa,b,c,d for CY7C1370C and DQa,b/DQPa,b for CY7C1372C) are automatically three-stated during the data portion of a write cycle, regardless of the state of OE. clock cycles are required to enter into or exit from this “sleep” mode. While in this mode, data integrity is guaranteed. Accesses pending when entering the “sleep” mode are not considered valid nor is the completion of the operation guaranteed. The device must be deselected prior to entering the “sleep” mode. CE1, CE2, and CE3, must remain inactive for the duration of tZZREC after the ZZ input returns LOW. Interleaved Burst Address Table (MODE = Floating or VDD) First Address Second Address Third Address Fourth Address A1,A0 A1,A0 A1,A0 A1,A0 Burst Write Accesses 00 01 10 11 The CY7C1370C/CY7C1372C has an on-chip burst counter that allows the user the ability to supply a single address and conduct up to four WRITE operations without reasserting the address inputs. ADV/LD must be driven LOW in order to load the initial address, as described in the Single Write Access section above. When ADV/LD is driven HIGH on the subsequent clock rise, the chip enables (CE1, CE2, and CE3) and WE inputs are ignored and the burst counter is incremented. The correct BW (BWa,b,c,d for CY7C1370C and BWa,b for CY7C1372C) inputs must be driven in each cycle of the burst write in order to write the correct bytes of data. 01 00 11 10 10 11 00 01 11 10 01 00 Linear Burst Address Table (MODE = GND) First Address Second Address Third Address Fourth Address A1,A0 A1,A0 A1,A0 A1,A0 00 01 10 11 Sleep Mode 01 10 11 00 The ZZ input pin is an asynchronous input. Asserting ZZ places the SRAM in a power conservation “sleep” mode. Two 10 11 00 01 11 00 01 10 ZZ Mode Electrical Characteristics Parameter IDDZZ tZZS tZZREC tZZI tRZZI Description Snooze mode standby current Device operation to ZZ ZZ recovery time ZZ active to snooze current ZZ Inactive to exit snooze current Test Conditions ZZ > VDD − 0.2V ZZ > VDD − 0.2V ZZ < 0.2V This parameter is sampled This parameter is sampled Min. Max 60 2tCYC 2tCYC 2tCYC 0 Unit mA ns ns ns ns Truth Table[1, 2, 3, 4, 5, 6, 7] Operation Deselect Cycle Continue Deselect Cycle Read Cycle (Begin Burst) Read Cycle (Continue Burst) NOP/Dummy Read (Begin Burst) Dummy Read (Continue Burst) Write Cycle (Begin Burst) Write Cycle (Continue Burst) Address Used None None External Next External Next External Next CE ZZ ADV/LD WE BWx OE CEN CLK H X L X L X L X L L L L L L L L L H L H L H L H X X H X H X L X X X X X X X L L X X L L H H X X L L L L L L L L L-H L-H L-H L-H L-H L-H L-H L-H DQ Three-State Three-State Data Out (Q) Data Out (Q) Three-State Three-State Data In (D) Data In (D) Notes: 1. X = “Don't Care”, 1 = Logic HIGH, 0 = Logic LOW, CE stands for ALL Chip Enables active. BWx = 0 signifies at least one Byte Write Select is active, BWx = Valid signifies that the desired byte write selects are asserted, see Write Cycle Description table for details. 2. Write is defined by WE and BW[a:d]. See Write Cycle Description table for details. 3. When a write cycle is detected, all I/Os are tri-stated, even during byte writes. 4. The DQ and DQP pins are controlled by the current cycle and the OE signal. 5. CEN = H inserts wait states. 6. Device will power-up deselected and the I/Os in a tri-state condition, regardless of OE. 7. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles.During a read cycle DQs and DQP[a:d] = Three-state when OE is inactive or when the device is deselected, and DQs=data when OE is active. Document #: 38-05233 Rev. *D Page 8 of 27 CY7C1370C CY7C1372C Truth Table[1, 2, 3, 4, 5, 6, 7] (continued) Address Used Operation CE ZZ ADV/LD WE BWx OE CEN CLK DQ NOP/WRITE ABORT (Begin Burst) None L L L L H X L L-H Three-State WRITE ABORT (Continue Burst) Next X L H X H X L L-H Three-State IGNORE CLOCK EDGE (Stall) Current X L X X X X H L-H – SNOOZE MODE None X H X X X X X X Three-State Partial Write Cycle Description[1, 2, 3, 8] Function (CY7C1370C) WE BWd BWc BWb BWa Read H X X X X Write – No bytes written L H H H H Write Byte a – (DQa and DQPa) L H H H L Write Byte b – (DQb and DQPb) L H H L H Write Bytes b, a L H H L L Write Byte c – (DQc and DQPc) L H L H H Write Bytes c, a L H L H L Write Bytes c, b L H LL L H Write Bytes c, b, a L H L L L Write Byte d – (DQd and DQPd) L L H H H Write Bytes d, a L L H H L Write Bytes d, b L L H L H Write Bytes d, b, a L L H L L Write Bytes d, c L L L H H Write Bytes d, c, a L L L H L Write Bytes d, c, b L L L L H Write All Bytes L L L L L Function (CY7C1372C) WE BWb BWa Read H x x Write – No Bytes Written L H H Write Byte a – (DQa and DQPa) L H L Write Byte b – (DQb and DQPb) L L H Write Both Bytes L L L Note: 8. Table only lists a partial listing of the byte write combinations. Any combination of BW[a:d] is valid. Appropriate write will be done based on which byte write is active. Document #: 38-05233 Rev. *D Page 9 of 27 CY7C1370C CY7C1372C IEEE 1149.1 Serial Boundary Scan (JTAG) The CY7C1370C/CY7C1372C incorporates a serial boundary scan Test Access Port (TAP) in the BGA package only. The TQFP package does not offer this functionality. This port operates in accordance with IEEE Standard 1149.1-1900, but does not have the set of functions required for full 1149.1 compliance. These functions from the IEEE specification are excluded because their inclusion places an added delay in the critical speed path of the SRAM. Note that the TAP controller functions in a manner that does not conflict with the operation of other devices using 1149.1 fully compliant TAPs. The TAP operates using JEDEC standard 3.3V or 2.5V I/O logic levels. Disabling the JTAG Feature It is possible to operate the SRAM without using the JTAG feature. To disable the TAP controller, TCK must be tied LOW (VSS) to prevent clocking of the device. TDI and TMS are internally pulled up and may be unconnected. They may alternately be connected to VDD through a pull-up resistor. TDO should be left unconnected. Upon power-up, the device will come up in a reset state which will not interfere with the operation of the device. Test Access Port–Test Clock The test clock is used only with the TAP controller. All inputs are captured on the rising edge of TCK. All outputs are driven from the falling edge of TCK. Test Mode Select The TMS input is used to give commands to the TAP controller and is sampled on the rising edge of TCK. It is allowable to leave this pin unconnected if the TAP is not used. The pin is pulled up internally, resulting in a logic HIGH level. Test Data-In (TDI) The TDI pin is used to serially input information into the registers and can be connected to the input of any of the registers. The register between TDI and TDO is chosen by the instruction that is loaded into the TAP instruction register. For information on loading the instruction register, see the TAP Controller State Diagram. TDI is internally pulled up and can be unconnected if the TAP is unused in an application. TDI is connected to the Most Significant Bit (MSB) on any register. Test Data Out (TDO) circuitry. Only one register can be selected at a time through the instruction registers. Data is serially loaded into the TDI pin on the rising edge of TCK. Data is output on the TDO pin on the falling edge of TCK. Instruction Register Three-bit instructions can be serially loaded into the instruction register. This register is loaded when it is placed between the TDI and TDO pins as shown in the TAP Controller Block Diagram. Upon power-up, the instruction register is loaded with the IDCODE instruction. It is also loaded with the IDCODE instruction if the controller is placed in a reset state as described in the previous section. When the TAP controller is in the CaptureIR state, the two least significant bits are loaded with a binary “01” pattern to allow for fault isolation of the board level serial test path. Bypass Register To save time when serially shifting data through registers, it is sometimes advantageous to skip certain states. The bypass register is a single-bit register that can be placed between TDI and TDO pins. This allows data to be shifted through the SRAM with minimal delay. The bypass register is set LOW (VSS) when the BYPASS instruction is executed. Boundary Scan Register The boundary scan register is connected to all the input and output pins on the SRAM. Several no connect (NC) pins are also included in the scan register to reserve pins for higher density devices. The ×36 configuration has a 69-bit-long register, and the ×18 configuration has a 69-bit-long register. The boundary scan register is loaded with the contents of the RAM Input and Output ring when the TAP controller is in the Capture-DR state and is then placed between the TDI and TDO pins when the controller is moved to the Shift-DR state. The EXTEST, SAMPLE/PRELOAD and SAMPLE Z instructions can be used to capture the contents of the Input and Output ring. The Boundary Scan Order tables show the order in which the bits are connected. Each bit corresponds to one of the bumps on the SRAM package. The MSB of the register is connected to TDI, and the LSB is connected to TDO. Identification (ID) Register The TDO output pin is used to serially clock data-out from the registers. The output is active depending upon the current state of the TAP state machine (see TAP Controller State Diagram). The output changes on the falling edge of TCK. TDO is connected to the Least Significant Bit (LSB) of any register. The ID register is loaded with a vendor-specific, 32-bit code during the Capture-DR state when the IDCODE command is loaded in the instruction register. The IDCODE is hardwired into the SRAM and can be shifted out when the TAP controller is in the Shift-DR state. The ID register has a vendor code and other information described in the Identification Register Definitions table. Performing a TAP Reset TAP Instruction Set A Reset is performed by forcing TMS HIGH (VDD) for five rising edges of TCK. This RESET does not affect the operation of the SRAM and may be performed while the SRAM is operating. At power-up, the TAP is reset internally to ensure that TDO comes up in a High-Z state. Eight different instructions are possible with the three-bit instruction register. All combinations are listed in the Instruction Code table. Three of these instructions are listed as RESERVED and should not be used. The other five instructions are described in detail below. TAP Registers The TAP controller used in this SRAM is not fully compliant to the 1149.1 convention because some of the mandatory 1149.1 instructions are not fully implemented. The TAP controller cannot be used to load address, data, or control signals into Registers are connected between the TDI and TDO pins and allow data to be scanned into and out of the SRAM test Document #: 38-05233 Rev. *D Page 10 of 27 CY7C1370C CY7C1372C the SRAM and cannot preload the Input or Output buffers. The SRAM does not implement the 1149.1 commands EXTEST or INTEST or the PRELOAD portion of SAMPLE/PRELOAD; rather it performs a capture of the Inputs and Output ring when these instructions are executed. Instructions are loaded into the TAP controller during the Shift-IR state when the instruction register is placed between TDI and TDO. During this state, instructions are shifted through the instruction register through the TDI and TDO pins. To execute the instruction once it is shifted in, the TAP controller needs to be moved into the Update-IR state. EXTEST EXTEST is a mandatory 1149.1 instruction which is to be executed whenever the instruction register is loaded with all 0s. EXTEST is not implemented in the TAP controller, and therefore this device is not compliant to the 1149.1 standard. The TAP controller does recognize an all-0 instruction. When an EXTEST instruction is loaded into the instruction register, the SRAM responds as if a SAMPLE/PRELOAD instruction has been loaded. There is one difference between the two instructions. Unlike the SAMPLE/PRELOAD instruction, EXTEST places the SRAM outputs in a High-Z state. IDCODE The IDCODE instruction causes a vendor-specific, 32-bit code to be loaded into the instruction register. It also places the instruction register between the TDI and TDO pins and allows the IDCODE to be shifted out of the device when the TAP controller enters the Shift-DR state. The IDCODE instruction is loaded into the instruction register upon power-up or whenever the TAP controller is given a test logic reset state. When the SAMPLE/PRELOAD instructions are loaded into the instruction register and the TAP controller is in the Capture-DR state, a snapshot of data on the inputs and output pins is captured in the boundary scan register. The user must be aware that the TAP controller clock can only operate at a frequency up to 10 MHz, while the SRAM clock operates more than an order of magnitude faster. Because there is a large difference in the clock frequencies, it is possible that during the Capture-DR state, an input or output will undergo a transition. The TAP may then try to capture a signal while in transition (metastable state). This will not harm the device, but there is no guarantee as to the value that will be captured. Repeatable results may not be possible. To guarantee that the boundary scan register will capture the correct value of a signal, the SRAM signal must be stabilized long enough to meet the TAP controller's capture set-up plus hold times (tCS and tCH). The SRAM clock input might not be captured correctly if there is no way in a design to stop (or slow) the clock during a SAMPLE/PRELOAD instruction. If this is an issue, it is still possible to capture all other signals and simply ignore the value of the CK and CK# captured in the boundary scan register. Once the data is captured, it is possible to shift out the data by putting the TAP into the Shift-DR state. This places the boundary scan register between the TDI and TDO pins. Note that since the PRELOAD part of the command is not implemented, putting the TAP into the Update to the Update-DR state while performing a SAMPLE/PRELOAD instruction will have the same effect as the Pause-DR command. Bypass The SAMPLE Z instruction causes the boundary scan register to be connected between the TDI and TDO pins when the TAP controller is in a Shift-DR state. It also places all SRAM outputs into a High-Z state. When the BYPASS instruction is loaded in the instruction register and the TAP is placed in a Shift-DR state, the bypass register is placed between the TDI and TDO pins. The advantage of the BYPASS instruction is that it shortens the boundary scan path when multiple devices are connected together on a board. SAMPLE/PRELOAD Reserved SAMPLE Z SAMPLE/PRELOAD is a 1149.1 mandatory instruction. The PRELOAD portion of this instruction is not implemented, so the TAP controller is not fully 1149.1-compliant. Document #: 38-05233 Rev. *D These instructions are not implemented but are reserved for future use. Do not use these instructions. Page 11 of 27 CY7C1370C CY7C1372C TAP Controller State Diagram[9] 1 TEST-LOGIC RESET 0 TEST-LOGIC/ IDLE 1 1 SELECT DR-SCAN 0 0 1 1 CAPTURE-DR CAPTURE-DR 0 0 0 SHIFT-DR 1 1 EXIT1-DR 1 EXIT1-IR 0 0 PAUSE-DR 0 0 PAUSE-IR 1 1 0 EXIT2-DR EXIT2-IR 1 1 UPDATE-DR 1 0 SHIFT-IR 1 0 1 SELECT IR-SCAN 0 UPDATE-IR 1 0 Note: 9. The 0/1 next to each state represents the value at TMS at the rising edge of TCK. Document #: 38-05233 Rev. *D Page 12 of 27 CY7C1370C CY7C1372C TAP Controller Block Diagram 0 Bypass Register Selection Circuitry 2 1 0 Selection Circuitry TDO Instruction Register TDI 31 30 29 . . 2 1 0 1 0 Identification Register 68 . . . . 2 Boundary Scan Register TCK TMS TAP Controller TAP Electrical Characteristics Over the Operating Range[10, 11] Parameter Description Test Conditions VOH1 Output HIGH Voltage VOH2 Output HIGH Voltage VOL1 Output LOW Voltage IOL = 8.0 mA VOL2 Output LOW Voltage VIH Input HIGH Voltage VDDQ = 3.3V VIL Input LOW Voltage VDDQ = 2.5V IX Input Load Current GND ≤ VI ≤ VDDQ IX Input Load Current TMS and TDI GND ≤ VI ≤ VDDQ Min. IOH = –4.0 mA VDDQ = 3.3V 2.4 IOH = –1.0 mA VDDQ = 2.5V 1.7 IOH = –100 µA VDDQ = 3.3V 2.9 VDDQ = 2.5V 2.1 Max. Unit V V VDDQ = 3.3V 0.4 V IOL = 1.0 mA VDDQ = 2.5V 0.4 V IOL = 100 µA VDDQ = 3.3V 0.2 V VDDQ = 2.5V 0.2 V 2.0 VDD + 0.3 V VDDQ = 2.5V 1.7 VDD + 0.3 V VDDQ = 3.3V –0.5 0.7 V –0.3 0.7 V –5 5 µA –5 5 µA TAP AC Switching Characteristics Over the Operating Range[12, 13] Parameter Description Min. Max. Unit 10 MHz tTCYC TCK Clock Cycle Time tTF TCK Clock Frequency tTH TCK Clock HIGH 40 ns tTL TCK Clock LOW 40 ns 100 ns Notes: 10. All voltage referenced to ground. 11. Overshoot: VIH(AC) < VDD + 1.5V for t < tTCYC/2; undershoot: VIL(AC) > −0.5V for t < tTCYC/2. 12. tCS and tCH refer to the set-up and hold time requirements of latching data from the boundary scan register. 13. Test conditions are specified using the load in TAP AC test conditions. tR/tF = 1 ns. Document #: 38-05233 Rev. *D Page 13 of 27 CY7C1370C CY7C1372C TAP AC Switching Characteristics Over the Operating Range[12, 13] (continued) Parameter Description Min. Max. Unit Set-up Times tTMSS TMS Set-up to TCK Clock Rise 10 ns tTDIS TDI Set-up to TCK Clock Rise 10 ns tCS Capture Set-up to TCK Rise 10 ns tTMSH TMS Hold after TCK Clock Rise 10 ns tTDIH TDI Hold after Clock Rise 10 ns tCH Capture Hold after clock rise 10 ns Hold Times Output Times tTDOV TCK Clock LOW to TDO Valid tTDOX TCK Clock LOW to TDO Invalid 20 ns 0 ns TAP Timing and Test Conditions 1.25V for 2.5V VDDQ ALL INPUT PULSES 50Ω 2.5V 1.25V TDO Z0 = 50Ω (a) VSS CL = 20 pF tTH GND 1.5 ns 1.5 ns tTL Test Clock TCK tTCYC tTMSS tTMSH Test Mode Select TMS tTDIS tTDIH Test Data-In TDI Test Data-Out TDO tTDOV Document #: 38-05233 Rev. *D tTDOX Page 14 of 27 CY7C1370C CY7C1372C Identification Register Definitions CY7C1370C CY7C1372C Revision Number (31:29) Instruction Field 010 010 Cypress Device ID (28:12) 01010001000100101 Cypress JEDEC ID (11:1) 00000110100 00000110100 ID Register Presence (0) 1 1 Description Reserved for version number. 01010001000010101 Reserved for future use. Allows unique identification of SRAM vendor. Indicate the presence of an ID register. Scan Register Sizes Register Name Bit Size(x18) Bit Size (x36) Instruction 3 3 Bypass 1 1 ID 32 32 Boundary Scan 70 70 Identification Codes Instruction Code Description EXTEST 000 Captures the Input/Output ring contents. Places the boundary scan register between the TDI and TDO. Forces all SRAM outputs to High-Z state. This instruction is not 1149.1-compliant. IDCODE 001 Loads the ID register with the vendor ID code and places the register between TDI and TDO. This operation does not affect SRAM operation. SAMPLE Z 010 Captures the Input/Output contents. Places the boundary scan register between TDI and TDO. Forces all SRAM output drivers to a High-Z state. RESERVED 011 Do Not Use: This instruction is reserved for future use. SAMPLE/PRELOAD 100 Captures the Input/Output ring contents. Places the boundary scan register between TDI and TDO. Does not affect the SRAM operation. This instruction does not implement 1149.1 preload function and is therefore not 1149.1-compliant. RESERVED 101 Do Not Use: This instruction is reserved for future use. RESERVED 110 Do Not Use: This instruction is reserved for future use. BYPASS 111 Places the bypass register between TDI and TDO. This operation does not affect SRAM operation. Document #: 38-05233 Rev. *D Page 15 of 27 CY7C1370C CY7C1372C 119-ball BGA Boundary Scan Order Bit# 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 Bit# 1 2 3 4 5 6 7 CY7C1370C (512K x 36) Ball ID Bit# Ball ID 36 P4 K4 H4 37 N4 M4 38 R6 F4 39 T5 B4 40 T3 A4 41 R2 G4 42 R3 C6 43 P2 A6 44 P1 D6 45 N2 D7 46 L2 E6 47 K1 G6 48 N1 H7 49 M2 E7 50 L1 F6 51 K2 G7 52 Not Bonded (Preset to 1) H6 53 H1 T7 54 G2 K7 55 E2 L6 56 D1 N6 57 H2 P7 58 G1 K6 59 F2 L7 60 E1 M6 61 D2 N7 62 A5 P6 63 A3 B5 64 E4 B3 65 B2 C5 66 L3 C3 67 G3 C2 68 G5 A2 69 L5 T4 70 B6 CY7C1372C (1M x 18) Ball ID Bit# 37 K4 H4 38 M4 39 F4 40 B4 36 A4 41 G4 42 Document #: 38-05233 Rev. *D 8 C6 43 9 A6 44 10 T6 45 11 46 14 15 16 17 Not Bonded (Preset to 0) Not Bonded (Preset to 0) Not Bonded (Preset to 0) D6 E7 F6 G7 18 19 20 21 22 H6 T7 K7 L6 N6 53 54 55 56 57 23 P7 58 24 59 29 30 31 Not Bonded (Preset to 0) Not Bonded (Preset to 0) Not Bonded (Preset to 0) Not Bonded (Preset to 0) Not Bonded (Preset to 0) Not Bonded (Preset to 0) Not Bonded (Preset to 0) B5 B3 C5 32 33 C3 C2 67 68 34 35 A2 T2 69 70 12 13 25 26 27 28 Ball ID N4 R6 T5 T3 P4 R2 R3 47 Not Bonded (Preset to 0) Not Bonded (Preset to 0) Not Bonded (Preset to 0) Not Bonded (Preset to 0) Not Bonded (Preset to 0) P2 48 N1 49 50 51 52 M2 L1 K2 Not Bonded (Preset to 1) H1 G2 E2 D1 Not Bonded (Preset to 0) Not Bonded (Preset to 0) Not Bonded (Preset to 0) Not Bonded (Preset to 0) Not Bonded (Preset to 0) Not Bonded (Preset to 0) 60 61 Not Bonded (Preset to 0) 62 A5 63 A3 64 65 66 E4 B2 Not Bonded (Preset to 0) G3 Not Bonded (Preset to 0) L5 B6 Page 16 of 27 CY7C1370C CY7C1372C 165-Ball fBGA Boundary Scan Order Bit# 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 CY7C1370C (512K x 36) Ball ID Bit# B6 36 B7 37 A7 38 B8 39 A8 40 B9 41 A9 42 B10 43 A10 44 C11 45 E10 46 F10 47 G10 48 D10 49 D11 50 E11 51 F11 52 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 G11 H11 J10 K10 L10 M10 J11 K11 L11 M11 N11 R11 R10 R9 R8 P10 P9 P8 Bit# 1 2 3 4 5 CY7C1372C (1M x 18) Ball ID Bit# B6 36 B7 37 A7 38 B8 39 A8 40 Document #: 38-05233 Rev. *D 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 Ball ID R6 P6 R4 R3 P4 P3 R1 N1 L2 K2 J2 M2 M1 L1 K1 J1 Not Bonded (Preset to 1) G2 F2 E2 D2 G1 F1 E1 D1 C1 A2 B2 A3 B3 B4 A4 A5 B5 A6 Ball ID R6 P6 R4 R3 P4 Bit# 6 7 8 CY7C1372C (1M x 18) Ball ID Bit# B9 41 A9 42 B10 43 47 Ball ID P3 R1 Not Bonded (Preset to 0) Not Bonded (Preset to 0) Not Bonded (Preset to 0) Not Bonded (Preset to 0) N1 48 M1 49 L1 50 51 52 62 K1 J1 Not Bonded (Preset to 1) G2 F2 E2 D2 Not Bonded (Preset to 0) Not Bonded (Preset to 0) Not Bonded (Preset to 0) Not Bonded (Preset to 0) Not Bonded (Preset to 0) A2 63 B2 64 65 66 A3 B3 Not Bonded (Preset to 0) Not Bonded (Preset to 0) A4 B5 A6 9 A10 44 10 A11 45 11 46 15 16 17 Not Bonded (Preset to 0) Not Bonded (Preset to 0) Not Bonded (Preset to 0) Not Bonded (Preset to 0) D11 E11 F11 18 19 20 21 22 G11 H11 J10 K10 L10 53 54 55 56 57 23 M10 58 24 59 29 30 31 Not Bonded (Preset to 0) Not Bonded (Preset to 0) Not Bonded (Preset to 0) Not Bonded (Preset to 0) Not Bonded (Preset to 0) R11 R10 R9 32 R8 67 33 34 35 P10 P9 P8 68 69 70 12 13 14 25 26 27 28 60 61 Page 17 of 27 CY7C1370C CY7C1372C Maximum Ratings Current into Outputs (LOW)......................................... 20 mA (Above which the useful life may be impaired. For user guidelines, not tested.) Static Discharge Voltage.......................................... > 2001V (per MIL-STD-883, Method 3015) Storage Temperature ................................. –65°C to +150°C Latch-up Current.................................................... > 200 mA Ambient Temperature with Power Applied............................................. –55°C to +125°C Operating Range Supply Voltage on VDD Relative to GND........ –0.5V to +4.6V DC to Outputs in Tri-State ................... –0.5V to VDDQ + 0.5V DC Input Voltage....................................–0.5V to VDD + 0.5V Ambient Temperature Range Commercial Industrial VDD VDDQ 0°C to +70°C 3.3V–5%/+10% 2.5V –5% to VDD –40°C to +85°C Electrical Characteristics Over the Operating Range[14, 15] Parameter Description Test Conditions Min. VDD Power Supply Voltage VDDQ I/O Supply Voltage VOH Output HIGH Voltage VDD = Min., IOH = −4.0 mA, VDDQ = 3.3V 2.4 VDD = Min., IOH= −1.0 mA, VDDQ = 2.5V 2.0 VOL Output LOW Voltage VDD = Min., IOL= 8.0 mA, VDDQ = 3.3V VIH Input HIGH Voltage VDDQ = 3.3V VIL Input LOW Voltage[14] VDDQ = 2.5V IX Input Load Current GND ≤ VI ≤ VDDQ Max. Unit 3.135 3.6 V VDDQ = 3.3V 3.135 VDD V VDDQ = 2.5V 2.375 2.625 V 0.4 VDD = Min., IOL= 1.0 mA, VDDQ = 2.5V V V V 0.4 V 2.0 VDD + 0.3V V VDDQ = 2.5V 1.7 VDD + 0.3V V VDDQ = 3.3V –0.3 0.8 V –0.3 0.7 V –5 5 µA Input Current of MODE –30 30 µA IOZ Output Leakage Current GND ≤ VI ≤ VDDQ, Output Disabled –5 5 µA IDD VDD Operating Supply ISB1 Automatic CE Power-down Current—TTL Inputs VDD = Max., IOUT = 0 mA, f = fMAX = 1/tCYC 4.0-ns cycle, 250 MHz 350 mA 4.4-ns cycle, 225 MHz 325 mA 5.0-ns cycle, 200 MHz 300 mA 6.0-ns cycle, 167 MHz 275 mA Max. VDD, Device Deselected, 4.0-ns cycle, 250 MHz VIN ≥ VIH or VIN ≤ VIL, f = fMAX = 4.4-ns cycle, 225 MHz 1/tCYC 5.0-ns cycle, 200 MHz 120 mA 110 mA 100 mA 6.0-ns cycle, 167 MHz 90 mA ISB2 Automatic CE Max. VDD, Device Deselected, All speed grades Power-down VIN ≤ 0.3V or VIN > VDDQ − 0.3V, Current—CMOS Inputs f = 0 70 mA ISB3 Max. VDD, Device Deselected, 4.0-ns cycle, 250 MHz Automatic CE Power-down VIN ≤ 0.3V or VIN > VDDQ − 0.3V, 4.4-ns cycle, 225 MHz Current—CMOS Inputs f = fMAX = 1/tCYC 5.0-ns cycle, 200 MHz 105 mA ISB4 Automatic CE Power-down Current—TTL Inputs Max. VDD, Device Deselected, VIN ≥ VIH or VIN ≤ VIL, f = 0 100 mA 95 mA 6.0-ns cycle, 167 MHz 85 mA All speed grades 80 mA Shaded areas contain advance information. Notes: 14. Overshoot: VIH(AC) < VDD +1.5V (Pulse width less than tCYC/2), undershoot: VIL(AC)> -2V (Pulse width less than tCYC/2). 15. TPower-up: Assumes a linear ramp from 0V to VDD (min.) within 200ms. During this time VIH < VDD and VDDQ < VDD. Document #: 38-05233 Rev. *D Page 18 of 27 CY7C1370C CY7C1372C Capacitance[16] Parameter Description Test Conditions CIN Input Capacitance CCLK Clock Input Capacitance CI/O Input/Output Capacitance BGA Max. TA = 25°C, f = 1 MHz, VDD = 2.5V VDDQ = 2.5V fBGA Max. TQFP Max. Unit 8 9 5 pF 8 9 5 pF 8 9 5 pF AC Test Loads and Waveforms R=1667Ω 2.5V OUTPUT ALL INPUT PULSES Output Z0 = 50Ω RL = 50Ω VDD 5 pF VL = 1.25V INCLUDING JIG AND SCOPE (a) 0V R = 1538Ω 90% 10% [16] 90% 10% 1.25V < 1.0 ns < 1.0 ns (c) (b) Thermal Resistance[16] Parameters Description QJA Thermal Resistance (Junction to Ambient) QJC Thermal Resistance (Junction to Case) Test Conditions BGA Typ. fBGA Typ. TQFP Typ. Unit Notes Test conditions follow standard test methods and procedures for measuring thermal impedance, per EIA / JESD51. 45 46 31 °C/W 17 7 3 6 °C/W 17 Switching Characteristics Over the Operating Range [ 21, 22] -250 Parameter Description [17] VCC (typical) to the first access read or write tPower Min. Max. 1 -225 Min. Max. 1 -200 -167 Min. Max. Min. Max. Unit 1 1 ms Clock tCYC Clock Cycle Time FMAX Maximum Operating Frequency tCH Clock HIGH 1.7 2.0 2.0 2.2 ns tCL Clock LOW 1.7 2.0 2.0 2.2 ns 4.0 4.4 250 5 225 6 200 ns 166 MHz Output Times tCO Data Output Valid After CLK Rise tEOV OE LOW to Output Valid tDOH Data Output Hold After CLK Rise tCHZ Clock to High-Z[18, 19, 20] tCLZ Clock to Low-Z[18, 19, 20] tEOHZ tEOLZ 2.6 2.8 2.6 1.0 2.8 1.0 2.6 1.0 [18, 19, 20] OE HIGH to Output High-Z OE LOW to Output Low-Z[18, 19, 20] 3.0 1.3 2.8 1.0 2.6 0 3.0 3.0 3.4 ns ns 3.4 1.3 3.0 0 ns 1.3 1.3 2.8 0 3.4 ns 3.4 0 ns ns ns Shaded areas contain advance information. Notes: 16. Tested initially and after any design or process changes that may affect these parameters. 17. This part has a voltage regulator internally; tpower is the time power needs to be supplied above Vdd minimum initially, before a Read or Write operation can be initiated. 18. tCHZ, tCLZ, tEOLZ, and tEOHZ are specified with AC test conditions shown in (b) of AC Test Loads. Transition is measured ± 200 mV from steady-state voltage. 19. At any given voltage and temperature, tEOHZ is less than tEOLZ and tCHZ is less than tCLZ to eliminate bus contention between SRAMs when sharing the same data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed to achieve High-Z prior to Low-Z under the same system conditions. 20. This parameter is sampled and not 100% tested. 21. Timing reference is 1.5V when VDDQ=3.3V and is 1.25V when VDDQ=2.5V. 22. Test conditions shown in (a) of AC Test Loads unless otherwise noted. Document #: 38-05233 Rev. *D Page 19 of 27 CY7C1370C CY7C1372C Switching Characteristics Over the Operating Range [ 21, 22] (continued) -250 Parameter Description -225 Min. Max. Min. -200 Max. -167 Min. Max. Min. Max. Unit Set-up Times tAS Address Set-up Before CLK Rise 1.2 1.4 1.4 1.5 ns tDS Data Input Set-up Before CLK Rise 1.2 1.4 1.4 1.5 ns tCENS CEN Set-up Before CLK Rise WE, BWx Set-up Before CLK Rise 1.2 1.4 1.4 1.5 ns 1.2 1.4 1.4 1.5 ns ADV/LD Set-up Before CLK Rise Chip Select Set-up 1.2 1.4 1.4 1.5 ns 1.2 1.4 1.4 1.5 ns tAH Address Hold After CLK Rise 0.3 0.4 0.4 0.5 ns tDH tWES tALS tCES Hold Times Data Input Hold After CLK Rise 0.3 0.4 0.4 0.5 ns tCENH CEN Hold After CLK Rise 0.3 0.4 0.4 0.5 ns tWEH WE, BWx Hold After CLK Rise 0.3 0.4 0.4 0.5 ns ADV/LD Hold after CLK Rise Chip Select Hold After CLK Rise 0.3 0.4 0.4 0.5 ns 0.3 0.4 0.4 0.5 ns tALH tCEH Switching Waveforms Read/Write/Timing[23,24,25] 1 2 3 t CYC 4 5 6 A3 A4 7 8 9 A5 A6 A7 10 CLK tCENS tCENH tCH tCL CEN tCES tCEH CE ADV/LD WE BWx A1 ADDRESS A2 tCO tAS tDS tAH Data In-Out (DQ) tDH D(A1) tCLZ D(A2) D(A2+1) tDOH Q(A3) tOEV Q(A4) tCHZ Q(A4+1) D(A5) Q(A6) tOEHZ tDOH tOELZ OE WRITE D(A1) WRITE D(A2) BURST WRITE D(A2+1) READ Q(A3) READ Q(A4) DON’T CARE BURST READ Q(A4+1) WRITE D(A5) READ Q(A6) WRITE D(A7) DESELECT UNDEFINED Notes: 23. For this waveform ZZ is tied low. 24. When CE is LOW, CE1 is LOW, CE2 is HIGH and CE3 is LOW. When CE is HIGH,CE1 is HIGH or CE2 is LOW or CE3 is HIGH. 25. Order of the Burst sequence is determined by the status of the MODE (0=Linear, 1=Interleaved).Burst operations are optional. Document #: 38-05233 Rev. *D Page 20 of 27 CY7C1370C CY7C1372C Switching Waveforms (continued) NOP,STALL AND DESELECT CYCLES[23,24,26] 1 2 A1 A2 3 4 5 A3 A4 6 7 8 9 10 CLK CEN CE ADV/LD WE BWx ADDRESS A5 tCHZ D(A1) Data Q(A2) D(A4) Q(A3) Q(A5) In-Out (DQ) WRITE D(A1) READ Q(A2) STALL READ Q(A3) WRITE D(A4) STALL DON’T CARE ZZ Mode NOP READ Q(A5) DESELECT CONTINUE DESELECT UNDEFINED Timing[27,28] CLK t ZZ ZZ I t ZZREC t ZZI SUPPLY I DDZZ t RZZI ALL INPUTS (except ZZ) Outputs (Q) DESELECT or READ Only High-Z DON’T CARE Notes: 26. The IGNORE CLOCK EDGE or STALL cycle (Clock 3) illustrated CEN being used to create a pause. A write is not performed during this cycle 27. Device must be deselected when entering ZZ mode. See cycle description table for all possible signal conditions to deselect the device. 28. I/Os are in High-Z when exiting ZZ sleep mode. Document #: 38-05233 Rev. *D Page 21 of 27 CY7C1370C CY7C1372C Ordering Information Speed (MHz) 250 Ordering Code CY7C1370C-250AC Package Name A101 Package Type 100-lead Thin Quad Flat Pack (14 x 20 x 1.4 mm) Operating Range Commercial CY7C1372C-250AC CY7C1370C-250BGC BG119 119-ball Ball Grid Array (14 x 22 x 2.4 mm) CY7C1372C-250BGC CY7C1370C-250BZC BB165A 165-ball Fine Pitch Ball Grid Array (13 x 15 x 1.2 mm) CY7C1372C-250BZC 225 CY7C1370C-225AC A101 100-lead Thin Quad Flat Pack (14 x 20 x 1.4 mm) CY7C1372C-225AC CY7C1370C-225BGC BG119 119-ball Ball Grid Array (14 x 22 x 2.4 mm) CY7C1372C-225BGC CY7C1370C-225BZC BB165A 165-ball Fine Pitch Ball Grid Array (13 x 15 x 1.2 mm) CY7C1372C-225BZC 200 CY7C1370C-200AC A101 100-lead Thin Quad Flat Pack (14 x 20 x 1.4 mm) CY7C1372C-200AC CY7C1370C-200BGC BG119 119-ball Ball Grid Array (14 x 22 x 2.4 mm) CY7C1372C-200BGC CY7C1370C-200BZC BB165A 165-ball Fine Pitch Ball Grid Array (13 x 15 x 1.2 mm) CY7C1372C-200BZC 167 CY7C1370C-167AC A101 100-lead Thin Quad Flat Pack (14 x 20 x 1.4 mm) CY7C1372C-167AC CY7C1370C-167BGC BG119 119-ball Ball Grid Array (14 x 22 x 2.4 mm) CY7C1372C-167BGC CY7C1370C-167BZC BB165A 165-ball Fine Pitch Ball Grid Array (13 x 15 x 1.2 mm) CY7C1372C-167BZC Document #: 38-05233 Rev. *D Page 22 of 27 CY7C1370C CY7C1372C Ordering Information (continued) Speed (MHz) 250 Ordering Code CY7C1370C-250AI Package Name A101 Package Type 100-lead Thin Quad Flat Pack (14 x 20 x 1.4 mm) Operating Range Industrial CY7C1372C-250AI CY7C1370C-250BGI BG119 119-ball Ball Grid Array (14 x 22 x 2.4 mm) CY7C1372C-250BGI CY7C1370C-250BZI BB165A 165-ball Fine Pitch Ball Grid Array (13 x 15 x 1.2 mm) CY7C1372C-250BZI 225 CY7C1370C-225AI A101 100-lead Thin Quad Flat Pack (14 x 20 x 1.4 mm) CY7C1372C-225AI CY7C1370C-225BGI BG119 119-ball Ball Grid Array (14 x 22 x 2.4 mm) CY7C1372C-225BGI CY7C1370C-225BZI BB165A 165-ball Fine Pitch Ball Grid Array (13 x 15 x 1.2 mm) CY7C1372C-225BZI 200 CY7C1370C-200AI A101 100-lead Thin Quad Flat Pack (14 x 20 x 1.4 mm) CY7C1372C-200AI CY7C1370C-200BGI BG119 119-ball Ball Grid Array (14 x 22 x 2.4 mm) CY7C1372C-200BGI CY7C1370C-200BZI BB165A 165-ball Fine Pitch Ball Grid Array (13 x 15 x 1.2 mm) CY7C1372C-200BZI 167 CY7C1370C-167AI A101 100-lead Thin Quad Flat Pack (14 x 20 x 1.4 mm) CY7C1372C-167AI CY7C1370C-167BGI BG119 119-ball Ball Grid Array (14 x 22 x 2.4 mm) CY7C1372C-167BGI CY7C1370C-167BZI BB165A 165-ball Fine Pitch Ball Grid Array (13 x 15 x 1.2 mm) CY7C1372C-167BZI Shaded areas contain advance information. Please contact your local Cypress sales representative for availability of these parts. Document #: 38-05233 Rev. *D Page 23 of 27 CY7C1370C CY7C1372C Package Diagrams 100-Pin Thin Plastic Quad Flatpack (14 x 20 x 1.4 mm) A101 DIMENSIONS ARE IN MILLIMETERS. 16.00±0.20 1.40±0.05 14.00±0.10 100 81 80 1 20.00±0.10 22.00±0.20 0.30±0.08 0.65 TYP. 30 SEE DETAIL 50 0.20 MAX. 1.60 MAX. STAND-OFF 0.05 MIN. 0.15 MAX. 0.25 GAUGE PLANE 0.10 0° MIN. 0°-7° A 51 31 R 0.08 MIN. 0.20 MAX. 12°±1° (8X) SEATING PLANE R 0.08 MIN. 0.20 MAX. 0.60±0.15 0.20 MIN. 1.00 REF. DETAIL Document #: 38-05233 Rev. *D A 51-85050-*A Page 24 of 27 CY7C1370C CY7C1372C Package Diagrams (continued) 119 Lead PBGA (14 x 22 x 2.4 mm) BG119 51-85115-*B Document #: 38-05233 Rev. *D Page 25 of 27 CY7C1370C CY7C1372C Package Diagrams (continued) 165-Ball FBGA (13 x 15 x 1.2 mm) BB165A 51-85122-*C ZBT is a registered trademark of Integrated Device Technology. No Bus Latency and NoBL are trademarks of Cypress Semiconductor. All product and company names mentioned in this document are trademarks of their respective holders. Document #: 38-05233 Rev. *D Page 26 of 27 © Cypress Semiconductor Corporation, 2004. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. CY7C1370C CY7C1372C Document History Page Document Title: CY7C1370C/CY7C1372C 512K x 36/1M x 18 Pipelined SRAM with NoBL™ Architecture Document Number: 38-05233 REV. ECN No. Issue Date Orig. of Change Description of Change ** 116273 08/27/02 SKX New Data Sheet *A 121536 11/21/02 DSG Updated package diagrams 51-85115 (BG119) to rev. *B and 51-85122 (BB165A) to rev. *C *B 206100 see ECN RKF Final Data Sheet *C 225487 See ECN VBL Update Ordering Info section: unshade active part numbers *D 231349 See ECN DIM Pin H2 (165 fBGA) changed from NC to NC/VDD. Document #: 38-05233 Rev. *D Page 27 of 27