A4931 3-Phase Brushless DC Motor Pre-Driver Features and Benefits Description ▪ Drives 6 N-channel MOSFETs ▪ Synchronous rectification for low power dissipation ▪ Internal UVLO and thermal shutdown circuitry ▪ Hall element inputs ▪ PWM current limiting ▪ Dead time protection ▪ FG outputs ▪ Standby mode ▪ Lock detect protection ▪ Overvoltage protection The A4931 is a complete 3-phase brushless DC motor pre-driver. The device is capable of driving a wide range of N-channel power MOSFETs and can support motor supply voltages up to 30 V. Commutation logic is determined by three Hall-element inputs spaced at 120°. Other features include fixed off-time pulse width modulation (PWM) current control for limiting inrush current, locked-rotor protection with adjustable delay, thermal shutdown, overvoltage monitor, and synchronous rectification. Internal synchronous rectification reduces power dissipation by turning on the appropriate MOSFETs during current decay, thus shorting the body diode with the low RDS(on) MOSFET. Overvoltage protection disables synchronous rectification when the motor pumps the supply voltage beyond the overvoltage threshold during current recirculation. Package: 28-contact QFN (ET package) The A4931 offers enable, direction, and brake inputs that can control current using either phase or enable chopping. Logic outputs FG1 and FG2 can be used to accurately measure motor rotation. Output signals toggle state during Hall transitions, providing an accurate speed output to a microcontroller or speed control circuit. Approximate Scale 1:1 Operating temperature range is –20°C to 105°C. The A4931 is supplied in a 5 mm × 5 mm, 28-terminal QFN package with exposed thermal pad. This small footprint package is lead (Pb) free with 100% matte tin leadframe plating. Typical Application 0.1 μF 0.1 μF 0.1 μF 2 kΩ VIN CLD HBIAS CP1 CP2 VCP VBB VIN GHA SA GLA M FG1 A4931 System Control Logic FG2 BRAKEZ ENABLE DIR GHB SB GLB GHC SC GLC SENSE GND HA+ HA– HB+ HB– HC+ HC– 4931-DS, Rev. 2 0.1 μF A4931 3-Phase Brushless DC Motor Pre-Driver Selection Guide Part Number A4931MET-T A4931METTR-T Packing Package 73 pieces per tube 1500 pieces per reel 5 mm x 5 mm, 0.90 mm nominal height QFN Absolute Maximum Ratings Characteristic Load Supply Voltage Symbol Notes VBB Motor Phase Output SX tw < 500 ns Hall Input VHx DC Logic Input Voltage Range VIN Units 38 V –3 V –0.3 to 7 V –0.3 to 7 V Operating Ambient Temperature TA –20 to 105 ºC Maximum Junction Temperature TJ(max) 150 ºC Tstg –40 to 150 ºC Rating Units 32 ºC/W 2 ºC/W Storage Temperature Range M Rating Thermal Characteristics Characteristic Symbol Package Thermal Resistance, Junction RθJA to Ambient Package Thermal Resistance, Junction RθJP to Exposed Pad *For additional information, refer to the Allegro website. Test Conditions* 4-layer PCB based on JEDEC standard Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 2 A4931 3-Phase Brushless DC Motor Pre-Driver Functional Block Diagram 0.1 μF CLD Lock Detect CP1 CP2 0.1 μF FG1 VCP CHARGE PUMP 0.1 μF HBIAS 2 kΩ HA+ HALL HA- HB+ HALL VIN Enable 0.1 μF VBB VREG OVP VCP Communication Logic VREG GHA SA HB- GHB SB GLB GATE DRIVE HC+ HALL HC- GHC SC GLC Control Logic FG1 FG2 GLA BRAKEZ SENSE System Logic DIR RSENSE 200 mV ENABLE VIN GND Terminal List Number Name Hall input A 15 GLB Low side gate drive B Hall input A 16 GLA Low side gate drive A HB+ Hall input B 17 GHC High side gate drive C HB - Hall input B 18 SC HC+ Hall input C 19 GHB HC- Hall input C 20 SB 7 GND Ground 21 GHA 8 HBIAS Hall bias power supply output 22 SA 9 CP1 Charge pump capacitor terminal 23 FG1 10 CP2 Charge pump capacitor terminal 24 FG2 FG 2 speed control output (ΦA input) 11 VBB Supply voltage 25 CLD Locked rotor detect timing capacitor 12 VCP Reservoir capacitor terminal 26 DIR 13 SENSE Sense resistor connection 27 ENABLE Logic input – external PWM control 14 GLC Low side gate drive C 28 BRAKEZ Logic input – motor brake (active low) Number Name 1 HA+ 2 HA - 3 4 5 6 Description Description High side source connection C High side gate drive B High side source connection B High side gate drive A High side source connection A FG 1 speed control output (3 Φ inputs) Logic input – motor direction Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 3 A4931 3-Phase Brushless DC Motor Pre-Driver ELECTRICAL CHARACTERISTICS* Valid at TA= 25°C, VBB = 24 V, unless noted otherwise Characteristics Supply Voltage Range Motor Supply Current Symbol VBB IBB Test Conditions Min. Typ. Max. Operating 8 – VBBOV V fPWM < 30 kHz, CLOAD = 1000 pF – 5 6 mA – 3 3.5 mA 7.2 7.5 7.8 V IHBIASlim 30 – – mA VIN(1) 2 – – V VIN(0) – – 0.8 V HBIAS VHBIAS HBIAS Current Limit Charge pump on, outputs disabled, Standby mode Units 0 mA ≤ IHBIAS ≤ 24 mA Control Logic Logic Input Voltage Logic Input Current Input Pin Glitch Reject IIN(1) VIN = 2 V –1 <1.0 1 μA IIN(0) VIN = 0.8 V –1 <–1.0 1 μA ENB pin 350 500 650 ns DIR, BRAKEZ pins 700 1000 1300 ns To outputs off 2.1 3 3.9 ms tGLITCH ENB Standby Pulse Propagation Delay tdENB HBIAS Wake-up Delay, Standby Mode tdHBIAS CHBIAS = 0.1 μF – 15 25 μs High-Side Gate Drive Output VGS(H) Relative to VBB, IGATE = 2 mA 7 – – V Low-Side Gate Drive Output VGS(L) IGATE = 2 mA 7 – – V Gate Drive Gate Drive Current (Sourcing) IGate 20 30 – mA Gate Drive Pull Down Resistance RGate GH = GL = 4 V 10 28 40 Ω Dead Time tdead 700 1000 1300 ns Current Limit Input Threshold VREF 180 200 220 mV Fixed Off-Time tOFF 18 28 37 μs TJTSD 155 170 185 °C Protection Thermal Shutdown Temperature Thermal Shutdown Hysteresis TJTSDhys VBB UVLO Enable Threshold VBBUV VBB UVLO Hysteresis VCP UVLO Lock Detect Duration VBB Overvoltage Threshold Rising VBB 14 15 26 °C 6.2 7 7.85 V 0.4 0.75 1 V Relative to VBB 4.6 – 6 V tlock C = 0.1 μF 1.5 2 2.5 s VBBOV Rising VBB 30 33 37.5 V VIN = 0.2 to 3.5 V –1 0 1 μA VBBUVhys VCPUV Hall Logic Hall Input Current IHALL Common Mode Input Range VCMR 0.2 – 3.5 V AC Input Voltage Range VHALL 60 – – mVp-p –10 – 10 mV Hall Threshold Vth Difference in Hall inputs at FG1 transition Hysteresis VHYS –5 12 25 mV Pulse Reject Filter tpulse – 2 – μs FG FG Output Saturation Voltage FG Leakage Current VFG(sat) IFG = 2 mA – – 0.5 V IFGlkg VFG = 5 V – – 1 μA *Typical data are for initial design estimations only, and assume optimum manufacturing and application conditions. Performance may vary for individual units, within the specified maximum and minimum limits. For input and output current specifications, negative current is defined as coming out of (sourcing) the specified device pin. Specifications throughout the allowed operating temperature range are guaranteed by design and characterization. Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 4 A4931 3-Phase Brushless DC Motor Pre-Driver Logic States Table (See timing charts, below) X = Don’t Care, Z = high impedance Inputs Condition DIR = 1 (Forward) Resulting Pre-Driver Outputs HA HB HC BRAKEZ ENB A + – + HI LO Motor Output GHA GLA GHB GLB GHC GLC HI LO LO HI LO A B C LO HI LO Z B + – – HI LO HI LO LO LO LO HI HI Z LO C + + – HI LO LO LO HI LO LO HI Z HI LO D – + – HI LO LO HI HI LO LO LO LO HI Z E – + + HI LO LO HI LO LO HI LO LO Z HI F – – + HI LO LO LO LO HI HI LO Z LO HI A + – + HI LO LO HI HI LO LO LO LO HI Z F – – + HI LO LO LO HI LO LO HI Z HI LO E – + + HI LO HI LO LO LO LO HI HI Z LO D – + – HI LO HI LO LO HI LO LO HI LO Z C + + – HI LO LO LO LO HI HI LO Z LO HI B + – – HI LO LO HI LO LO HI LO LO Z HI Fault* + + + HI X LO LO LO LO LO LO Z Z Z Fault* – – – HI X LO LO LO LO LO LO Z Z Z Brake* X X X LO X LO HI LO HI LO HI LO LO LO DIR = 0 (Reverse) * DIR = Don’t Care DIR = 1 = FOR A B C D DIR = 0 = REV E A F HA HA HB HB HC HC FG1 FG1 SA SA SB SB SC SC F E D C B Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 5 A4931 3-Phase Brushless DC Motor Pre-Driver Power-up and Standby Modes Timing Diagram VBB VBBUV Charge Pump HBIAS Voltage tdENB 3 ms Standby Mode Turn off Hall Bias Supply ENB Outputs Enabled Outputs Disabled Outputs Enabled Power-up and Standby Modes Timing Diagram VBB VBBUV VBB+7.5 V VCPUV Charge Pump 7.5V VHBIAS HBIAS Voltage ENB PWM Outputs Enabled Outputs Disabled Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 6 A4931 3-Phase Brushless DC Motor Pre-Driver Functional Description Current Regulation Load current is regulated by an internal fixed off-time PWM control circuit. When the outputs of the full bridge are turned on, current increases in the motor winding until it reaches a value, ITRIP , given by: ITRIP = 200 mV / RSENSE . When ITRIP is reached, the sense comparator resets the source enable latch, turning off the source driver. At this point, load inductance causes the current to recirculate for the fixed off-time period. Enable Logic The Enable input terminal (ENB pin) allows external PWM. ENB low turns on the selected sink-source pair. ENB high switches off the appropriate drivers and the load current decays. If ENB is held low, the current will rise until it reaches the level set by the internal current control circuit. Typically PWM frequency is in 20 kHz to 30 kHz range. If the ENB high pulse width exceeds 3 ms, the gate outputs are disabled. The Enable logic is summarized in the following table: ENB Pin Setting Outputs Outputs State 0 On Drive 1 Source Chopped Slow Decay with Synchronous Rectification 1 for > 3 ms typical Off Disable Fixed Off-Time The A4931 fixed off-time is set to 24 μs nominal. PWM Blank Timer When a source driver turns on, a current spike occurs due to the reverse recovery currents of the clamp diodes as well as switching transients related to distributed capacitance in the load. To prevent this current spike from erroneously resetting the source Enable latch, the sense comparator is blanked. The blanking timer runs after the off-time counter completes, in order to provide the blanking function. The blanking timer is reset when ENB is chopped or DIR is changed. With external PWM control, a DIR change or an ENB on triggers the blanking function. The duration is fixed at 1.5 μs. Synchronous Rectification When a PWM-off cycle is triggered, either by a chop command on ENB or by an internal fixed off-time cycle, load current recirculates. The A4931 synchronous rectification feature turns on the appropriate MOSFETs during the current decay, and effectively shorts out the body diodes with the low RDS(on) driver. This lowers power dissipation significantly and can eliminate the need for external Schottky diodes. Brake Mode A logic low on the BRAKEZ pin activates Brake mode. A logic high allows normal operation. Braking turns on all three sink drivers, effectively shorting out the motor-generated BEMF. The BRAKEZ input overrides the ENB input and also the Lock Detect function. It is important to note that the internal PWM current control circuit does not limit the current when braking, because the current does not flow through the sense resistor. The maximum current can be approximated by VBEMF / RLOAD. Care should be taken to insure that the maximum ratings of the A4391 are not exceeded in the worse case braking situation, high speed and high inertial load. HBIAS Function This function provides a power supply of 7.5 V, current-limited to 30 mA. This reference voltage is used to power the logic sections of the IC and also to power the external Hall elements. Standby Mode To prevent excessive power dissipation due to the current draw of the external Hall elements, Standby mode turns off the HBIAS output voltage. Standby mode is triggered by holding ENB high for longer than 3 ms. Note that Brake mode overrides Standby mode, so hold the BRAKEZ pin high in order to enter Standby mode. Charge Pump The internal charge pump is used to generate a supply above VBB to drive the high-side MOSFETs. The volt- Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 7 A4931 3-Phase Brushless DC Motor Pre-Driver age on the VCP pin is internally monitored, and in case of a fault Hall State Reporting The FG1 pin is an open drain output condition, the outputs of the device are disabled. that changes state at each transition of an external Hall element. Fault Shutdown In the event of a fault due to excessive The FG2 pin is an open drain output that changes state at each HAx transition. junction temperature or due to low voltage on VCP or VBB, the outputs of the device are disabled until the fault condition Lock Detect Function The IC will evaluate a locked rotor condition under either of these two different conditions: is removed. At power-up the UVLO circuit disables the drivers. These fault conditions are latched and can only be cleared by any one of the following actions: • The FG1 signal is not consistently changing. • The proper commutation sequence is not being followed. The motor can be locked in a condition in which it toggles between • Rising or falling edge on the DIR pin two specific Hall device states. • VBB UVLO threshold exceeded (during power-up cycle) Both of these fault conditions are allowed to persist for period • ENB pin held high for > tlock / 2 of time, tlock. tlock is set by capacitor connected to CLD pin. CLD produces a triangle waveform (1.67 V peak-to-peak) with fre- Overvoltage Protection VBB is monitored to determine if quency linearly related to the capacitor value. tlock is defined as a hazardous voltage is present due to the motor generator pump- 127 cycles of this triangle waveform, or: ing up the supply bus. When the voltage exceeds VBBOV , the synchronous rectification feature is disabled. Overtemperature Protection If die temperature exceeds approximately 170°C, the Thermal Shutdown function will dis- tlock = CLD × 20 s/μF After the wait time, tlock , has expired, the outputs are disabled, and the fault is latched. The Lock Detect function can be disabled by connecting CLD to GND. able the outputs until the internal temperature falls below the When the A4931 is in Brake mode, the Lock Detect counter is 15°C hysteresis. disabled. Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 8 A4931 3-Phase Brushless DC Motor Pre-Driver ET Package, 28-Contact QFN 0.30 5.00 ±0.15 1.15 28 1 2 0.50 28 1 A 5.00 ±0.15 3.15 4.80 3.15 29X D SEATING PLANE 0.08 C C 4.80 C +0.05 0.25 –0.07 PCB Layout Reference View 0.90 ±0.10 0.50 For Reference Only (reference JEDEC MO-220VHHD-1) Dimensions in millimeters Exact case and lead configuration at supplier discretion within limits shown +0.20 0.55 –0.10 A Terminal #1 mark area B 3.15 2 1 28 3.15 B Exposed thermal pad (reference only, terminal #1 identifier appearance at supplier discretion) C Reference land pattern layout (reference IPC7351 QFN50P500X500X100-29V1M); All pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary to meet application process requirements and PCB layout tolerances; when mounting on a multilayer PCB, thermal vias at the exposed thermal pad land can improve thermal dissipation (reference EIA/JEDEC Standard JESD51-5) D Coplanarity includes exposed thermal pad and terminals Copyright ©2007-2008, Allegro MicroSystems, Inc. The products described here are manufactured under one or more U.S. patents or U.S. patents pending. Allegro MicroSystems, Inc. reserves the right to make, from time to time, such departures from the detail specifications as may be required to permit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the information being relied upon is current. Allegro’s products are not to be used in life support devices or systems, if a failure of an Allegro product can reasonably be expected to cause the failure of that life support device or system, or to affect the safety or effectiveness of that device or system. The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, Inc. assumes no responsibility for its use; nor for any infringement of patents or other rights of third parties which may result from its use. For the latest version of this document, visit our website: www.allegromicro.com Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 9