C1019V33 CY7C1019B/ CY7C10191B 128K x 8 Static RAM Features • High speed — tAA = 10, 12, 15 ns • CMOS for optimum speed/power • Center power/ground pinout • Automatic power-down when deselected • Easy memory expansion with CE and OE options • Functionally equivalent to CY7C1019 Functional Description The CY7C1019B/10191B is a high-performance CMOS static RAM organized as 131,072 words by 8 bits. Easy memory expansion is provided by an active LOW Chip Enable (CE), an active LOW Output Enable (OE), and three-state drivers. This device has an automatic power-down feature that significantly reduces power consumption when deselected. Writing to the device is accomplished by taking Chip Enable (CE) and Write Enable (WE) inputs LOW. Data on the eight I/O pins (I/O0 through I/O7) is then written into the location specified on the address pins (A0 through A16). Reading from the device is accomplished by taking Chip Enable (CE) and Output Enable (OE) LOW while forcing Write Enable (WE) HIGH. Under these conditions, the contents of the memory location specified by the address pins will appear on the I/O pins. The eight input/output pins (I/O0 through I/O7) are placed in a high-impedance state when the device is deselected (CE HIGH), the outputs are disabled (OE HIGH), or during a write operation (CE LOW, and WE LOW). The CY7C1019B/10191B is available in standard 32-pin TSOP Type II and 400-mil-wide SOJ packages. Customers should use part number CY7C10191B when ordering parts with 10 ns tAA, and CY7C1019B when ordering 12 and 15 ns tAA. ogic Block Diagram Pin Configurations SOJ / TSOPII Top View A0 A1 A2 A3 I/O0 CE I/O0 I/O1 VCC V SS INPUT BUFFER I/O1 I/O2 512 x 256 x 8 ARRAY SENSE AMPS ROW DECODER A0 A1 A2 A3 A4 A5 A6 A7 A8 I/O3 I/O2 I/O3 WE A4 A5 A6 A7 I/O4 I/O5 CE COLUMN DECODER I/O6 POWER DOWN 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 A16 A15 A14 A13 OE I/O7 I/O6 VSS VCC I/O5 I/O4 A12 A11 A10 A9 A8 I/O7 A9 A 10 A 11 A 12 A 13 A 14 A 15 A 16 WE OE 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Cypress Semiconductor Corporation Document #: 38-05026 Rev. *A • 3901 North First Street • San Jose • CA 95134 • 408-943-2600 Revised August 13, 2002 CY7C1019B/ CY7C10191B Selection Guide 7C10191B-10 7C1019B-12 7C1019B-15 Maximum Access Time (ns) 10 12 15 Maximum Operating Current (mA) 150 140 130 Maximum Standby Current (mA) 10 10 10 − 1 1 L Maximum Ratings Current into Outputs (LOW) ........................................ 20 mA (Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ................................. –65°C to +150°C Ambient Temperature with Power Applied............................................. –55°C to +125°C Static Discharge Voltage............................................ >2001V (per MIL-STD-883, Method 3015) Latch-Up Current..................................................... >200 mA Operating Range Supply Voltage on VCC to Relative GND[1] .... –0.5V to +7.0V Range DC Voltage Applied to Outputs in High Z State[1] ....................................–0.5V to VCC + 0.5V Commercial DC Input Voltage[1].................................–0.5V to VCC + 0.5V Industrial Ambient Temperature[2] VCC 0°C to +70°C 5V ± 10% –40°C to +85°C 5V ± 10% Electrical Characteristics Over the Operating Range Parameter Description Test Conditions 7C10191B-10 7C1019B-12 Min. Min. Max. Max. VOH Output HIGH Voltage VCC = Min., IOH = – 4.0 mA VOL Output LOW Voltage VCC = Min., IOL = 8.0 mA VIH Input HIGH Voltage 2.2 VCC + 0.3 2.2 VCC + 0.3 VIL Input LOW Voltage[1] –0.3 0.8 –0.3 IIX Input Load Current GND < VI < VCC –1 +1 IOZ Output Leakage Current GND < VI < VCC, Output Disabled –5 +5 ICC VCC Operating Supply Current VCC = Max., IOUT = 0 mA, f = fMAX = 1/tRC 150 ISB1 Automatic CE Power-Down Current —TTL Inputs Max. VCC, CE > VIH VIN > VIH or L VIN < VIL, f = fMAX Automatic CE Power-Down Current —CMOS Inputs Max. VCC, CE > VCC – 0.3V, L VIN > VCC – 0.3V, or VIN < 0.3V, f = 0 ISB2 2.4 7C1019B-15 Min. 2.4 0.4 Max. 2.4 0.4 Unit V 0.4 V 2.2 VCC + 0.3 V 0.8 –0.3 0.8 V –1 +1 –1 +1 µA –5 +5 –5 +5 µA 140 130 mA 40 40 40 mA 20 20 20 10 10 10 − 1 1 mA Capacitance[3] Parameter Description CIN Input Capacitance COUT Output Capacitance Test Conditions TA = 25°C, f = 1 MHz, VCC = 5.0V Max. Unit 6 pF 8 pF Notes: 1. VIL (min.) = –2.0V for pulse durations of less than 20 ns. 2. TA is the “Instant On” case temperature. 3. Tested initially and after any design or process changes that may affect these parameters. Document #: 38-05026 Rev. *A Page 2 of 9 CY7C1019B/ CY7C10191B AC Test Loads and Waveforms ALL INPUT PULSES R1 480Ω R1 480Ω 5V 5V OUTPUT 3.0V 90% OUTPUT 30 pF R2 255Ω INCLUDING JIG AND SCOPE (a) R2 255Ω 5 pF INCLUDING JIG AND SCOPE (b) 90% 10% GND 10% ≤ 3 ns ≤ 3 ns THÉVENIN EQUIVALENT 167Ω 1.73V OUTPUT Equivalent to: Switching Characteristics[4] Over the Operating Range 7C10191B-10 Parameter Description Min. Max. 7C1019B-12 Min. Max. 7C1019B-15 Min. Max. Unit Read Cycle tRC Read Cycle Time tAA Address to Data Valid tOHA Data Hold from Address Change tACE CE LOW to Data Valid 10 12 15 ns tDOE OE LOW to Data Valid 5 6 7 ns tLZOE OE LOW to Low Z OE HIGH to High tHZOE 10 10 3 tLZCE CE LOW to Low tHZCE CE HIGH to High Z[5, 6] tPU CE LOW to Power-Up 12 3 0 10 ns 7 ns 7 ns 3 6 ns 0 12 ns ns 0 3 0 15 6 5 ns 3 0 5 CE HIGH to Power-Down tPD 15 3 0 Z[5, 6] Z[6] 12 ns 15 ns [7, 8] Write Cycle tWC Write Cycle Time 10 12 15 ns tSCE CE LOW to Write End 8 9 10 ns tAW Address Set-Up to Write End 7 8 10 ns tHA Address Hold from Write End 0 0 0 ns tSA Address Set-Up to Write Start 0 0 0 ns tPWE WE Pulse Width 7 8 10 ns tSD Data Set-Up to Write End 5 6 8 ns tHD Data Hold from Write End 0 0 0 ns tLZWE WE HIGH to Low Z[6] 3 3 3 ns tHZWE WE LOW to High Z[5, 6] 5 6 7 ns Notes: 4. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified IOL/IOH and 30-pF load capacitance. 5. tHZOE, tHZCE, and tHZWE are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured ±500 mV from steady-state voltage. 6. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device. 7. The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. CE and WE must be LOW to initiate a write, and the transition of any of these signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write. 8. The minimum write cycle time for Write Cycle no. 3 (WE controlled, OE LOW) is the sum of tHZWE and tSD. Document #: 38-05026 Rev. *A Page 3 of 9 CY7C1019B/ CY7C10191B Data Retention Characteristics Over the Operating Range (L Version Only) Parameter ICCDR tCDR Description Conditions VCC for Data Retention VDR Data Retention Current [3] Chip Deselect to Data Retention Time tR Min. No input may exceed VCC + 0.5V VCC = VDR = 2.0V, CE > VCC – 0.3V, VIN > VCC – 0.3V or VIN < 0.3V Max. 2.0 V 300 Operation Recovery Time Unit µA 0 ns 200 µs Data Retention Waveform DATA RETENTION MODE 3.0V VCC VDR > 2V tCDR 3.0V tR CE Switching Waveforms Read Cycle No. 1[9, 10] tRC ADDRESS tAA tOHA DATA OUT PREVIOUS DATA VALID DATA VALID Read Cycle No. 2 (OE Controlled)[10, 11] ADDRESS tRC CE tACE OE tHZOE tDOE DATA OUT tLZOE HIGH IMPEDANCE tLZCE VCC SUPPLY CURRENT tHZCE HIGH IMPEDANCE DATA VALID tPD tPU 50% ICC 50% ISB Notes: 9. Device is continuously selected. OE, CE = VIL. 10. WE is HIGH for read cycle. 11. Address valid prior to or coincident with CE transition LOW. Document #: 38-05026 Rev. *A Page 4 of 9 CY7C1019B/ CY7C10191B Switching Waveforms (continued) Write Cycle No. 1 (CE Controlled)[12, 13] tWC ADDRESS tSCE CE tSA tSCE tAW tHA tPWE WE tSD DATA I/O tHD DATA VALID Write Cycle No. 2 (WE Controlled, OE HIGH During Write)[12, 13] tWC ADDRESS tSCE CE tAW tSA tHA tPWE WE OE tSD DATA I/O tHD DATAIN VALID NOTE 14 tHZOE Notes: 12. Data I/O is high impedance if OE = VIH. 13. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state. 14. During this period the I/Os are in the output state and input signals should not be applied. Document #: 38-05026 Rev. *A Page 5 of 9 CY7C1019B/ CY7C10191B Switching Waveforms (continued) Write Cycle No. 3 (WE Controlled, OE LOW)[13] tWC ADDRESS tSCE CE tAW tSA tHA tPWE WE tSD NOTE 14 DATA I/O tHD DATA VALID tLZWE tHZWE Truth Table CE OE WE I/O0–I/O7 Mode Power H X X High Z Power-Down Standby (ISB) X X X High Z Power-Down Standby (ISB) L L H Data Out Read Active (ICC) L X L Data In Write Active (ICC) L H H High Z Selected, Outputs Disabled Active (ICC) Ordering Information Speed (ns) 10 12 15 Ordering Code CY7C10191B-10VC CY7C1019B-12VC CY7C1019B-12ZC CY7C1019B-15VC CY7C1019B-15VI CY7C1019B-15ZC CY7C1019B-15ZI Document #: 38-05026 Rev. *A Package Name V33 V33 ZS32 V33 V33 ZS32 ZS32 Package Type 32-Lead 400-Mil Molded SOJ 32-Lead 400-Mil Molded SOJ 32-Lead TSOP Type II 32-Lead 400-Mil Molded SOJ 32-Lead 400-Mil Molded SOJ 32-Lead TSOP Type II 32-Lead TSOP Type II Operating Range Commercial Commercial Commercial Commercial Industrial Commercial Industrial Page 6 of 9 CY7C1019B/ CY7C10191B Package Diagrams 32-Lead (400-Mil) Molded SOJ V33 51-85033-A 51-85033-*B Document #: 38-05026 Rev. *A Page 7 of 9 CY7C1019B/ CY7C10191B Package Diagrams (continued) 32-Lead TSOP II ZS32 51-85095 All product or company names mentioned in this document may be the trademarks of their respective holders. Document #: 38-05026 Rev. *A Page 8 of 9 © Cypress Semiconductor Corporation, 2002. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. CY7C1019B/ CY7C10191B Document Title: CY7C1019B/CY7C10191B 128K x 8 Static RAM Document Number: 38-05026 REV. ECN NO. Issue Date Orig. of Change ** 109949 09/25/01 SZV Change from Spec number: 38-01115 to 38-05026 *A 116170 08/14/02 HGK 1. SOJ (400-mil) package outline replacing incorrect SOJ package 2. Pin for pin compatible with CY7C1019 3. Industrial packages added to Ordering Information Document #: 38-05026 Rev. *A Description of Change Page 9 of 9