046B CY7C1046B 1M x 4 Static RAM Features • High speed — tAA = 12 ns • Low active power — 935 mW (max.) • Low CMOS standby power (L version) — 2.75 mW (max.) • 2.0V Data Retention (400 µW at 2.0V retention) • Automatic power-down when deselected • TTL-compatible inputs and outputs • Easy memory expansion with CE and OE features Functional Description The CY7C1046B is a high-performance CMOS static RAM organized as 1,048,576 words by 4 bits. Easy memory expan- sion is provided by an active LOW Chip Enable (CE), an active LOW Output Enable (OE), and three-state drivers. Writing to the device is accomplished by taking Chip Enable (CE) and Write Enable (WE) inputs LOW. Data on the four I/O pins (I/O0 through I/O3) is then written into the location specified on the address pins (A0 through A19). Reading from the device is accomplished by taking Chip Enable (CE) and Output Enable (OE) LOW while forcing Write Enable (WE) HIGH. Under these conditions, the contents of the memory location specified by the address pins will appear on the I/O pins. The four input/output pins (I/O0 through I/O3) are placed in a high-impedance state when the device is deselected (CE HIGH), the outputs are disabled (OE HIGH), or during a write operation (CE LOW, and WE LOW). The CY7C1046B is available in a standard 400-mil-wide 32-pin SOJ package with center power and ground (revolutionary) pinout. Logic Block Diagram Pin Configuration SOJ Top View INPUT BUFFER ROW DECODER I/O0 1M x 4 ARRAY SENSE AMPS A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A0 A1 A2 A3 A4 CE I/O0 VCC GND I/O1 WE A5 A6 A7 A8 A9 I/O1 I/O2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 A19 A18 A17 A16 A15 OE I/O3 GND VCC I/O2 A14 A13 A12 A11 A10 NC I/O3 1046B–2 COLUMN DECODER CE POWER DOWN OE A 11 A 12 A 13 A14 A15 A16 A17 A18 A19 WE 1046B–1 Selection Guide 7C1046B-12 7C1046B-15 7C1046B-20 Maximum Access Time (ns) 12 15 20 Maximum Operating Current (mA) 170 150 130 8 8 8 0.5 0.5 0.5 Maximum CMOS Standby Current (mA) Com’l L version Shaded areas contain advance information. Cypress Semiconductor Corporation Document #: 38-05144 Rev. ** • 3901 North First Street • San Jose • CA 95134 • 408-943-2600 Revised September 6, 2001 CY7C1046B Maximum Ratings Current into Outputs (LOW) ........................................ 20 mA Static Discharge Voltage ........................................... >2001V (per MIL-STD-883, Method 3015) (Above which the useful life may be impaired. For user guidelines, not tested.) Latch-Up Current..................................................... >200 mA Storage Temperature ................................. –65°C to +150°C Operating Range Ambient Temperature with Power Applied............................................. –55°C to +125°C Supply Voltage on VCC to Relative GND[1] .... –0.5V to +7.0V Range DC Voltage Applied to Outputs in High Z State[1] ....................................–0.5V to VCC + 0.5V Commercial Ambient Temperature[2] VCC 0°C to +70°C 4.5V–5.5V DC Input Voltage[1] ................................–0.5V to VCC + 0.5V Electrical Characteristics Over the Operating Range Parameter Description Test Conditions 7C1046B-12 7C1046B-15 7C1046B-20 Min. Min. Min. Max. 2.4 Max. Unit 0.4 V VOH Output HIGH Voltage VCC = Min., IOH = –4.0 mA VOL Output LOW Voltage VCC = Min., IOL = 8.0 mA VIH Input HIGH Voltage 2.2 VCC + 0.3 2.2 VCC + 0.3 2.2 VCC + 0.3 V VIL Input LOW Voltage[1] –0.3 0.8 –0.3 0.8 –0.3 0.8 V IIX Input Load Current GND < VI < VCC –1 +1 –1 +1 –1 +1 µA IOZ Output Leakage Current GND < VOUT < VCC, Output Disabled –1 +1 –1 +1 –1 +1 µA ICC VCC Operating Supply Current VCC = Max., f = fMAX = 1/tRC 170 150 130 mA ISB1 Automatic CE Power-Down Current —TTL Inputs Max. VCC, CE > VIH VIN > VIH or VIN < VIL, f = fMAX 20 20 20 mA ISB2 Automatic CE Power-Down Current —CMOS Inputs Com’l 8 8 8 mA L version 0.5 0.5 0.5 Max. VCC, CE > VCC – 0.3V, VIN > VCC – 0.3V, or VIN < 0.3V, f = 0 2.4 Max. 0.4 2.4 0.4 V Shaded areas contain advance information. Capacitance[3] Parameter Description CIN Input Capacitance COUT I/O Capacitance Test Conditions TA = 25°C, f = 1 MHz, VCC = 5.0V Max. Unit 6 pF 6 pF Note: 1. VIL (min.) = –2.0V for pulse durations of less than 20 ns. 2. TA is the “Instant On” case temperature. 3. Tested initially and after any design or process changes that may affect these parameters. Document #: 38-05144 Rev. ** Page 2 of 8 CY7C1046B AC Test Loads and Waveforms R1 481 Ω 5V 5V OUTPUT ALL INPUT PULSES R1 481 Ω Vcc 90% OUTPUT 30 pF R2 255 Ω INCLUDING JIG AND SCOPE (a) GND R2 255 Ω 5 pF INCLUDING JIG AND SCOPE (b) 90%VCC 10% 10%VCC Rise Time:1 V/ns Fall Time:1 V/ns 1046B–4 1046B–3 THÉVENIN EQUIVALENT 167Ω 1.73V OUTPUT Equivalent to: Switching Characteristics[4] Over the Operating Range 7C1046B-12 Parameter Description Min. Max. 7C1046B-15 7C1046B-20 Min. Min. Max. Max. Unit READ CYCLE tpower VCC(typical) to the first access[5] 1 1 1 µs tRC Read Cycle Time 12 15 20 ns tAA Address to Data Valid tOHA Data Hold from Address Change tACE CE LOW to Data Valid 12 15 20 ns tDOE OE LOW to Data Valid 6 7 8 ns [7] tLZOE OE LOW to Low Z tHZOE OE HIGH to High Z[6, 7] tLZCE CE LOW to Low Z [7] 12 3 0 3 CE HIGH to High Z tPU CE LOW to Power-Up tPD CE HIGH to Power-Down 6 3 0 12 ns 8 7 ns ns 8 0 15 ns ns 0 7 3 0 20 3 0 6 [6, 7] tHZCE 15 3 ns ns 20 ns [8, 9] WRITE CYCLE tWC Write Cycle Time 12 15 20 ns tSCE CE LOW to Write End 8 10 15 ns tAW Address Set-Up to Write End 8 10 15 ns tHA Address Hold from Write End 0 0 0 ns tSA Address Set-Up to Write Start 0 0 0 ns tPWE WE Pulse Width 8 10 12 ns tSD Data Set-Up to Write End 6 8 10 ns tHD Data Hold from Write End 0 0 0 ns 3 3 3 ns tLZWE tHZWE WE HIGH to Low Z [7] WE LOW to High Z [6, 7] 6 7 8 ns Notes: 4. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified IOL/IOH and 30-pF load capacitance. 5. This part has a voltage regulator which steps down the voltage from 5V to 3.3V internally. tpower time has to be provided initially before a read/write operation is started. 6. tHZOE, tHZCE, and tHZWE are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured ±500 mV from steady-state voltage. 7. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device. 8. The internal write time of the memory is defined by the overlap of CE LOW, and WE LOW. CE and WE must be LOW to initiate a write, and the transition of either of these signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write. 9. The minimum write cycle time for Write Cycle no. 3 (WE controlled, OE LOW) is the sum of tHZWE and tSD. Document #: 38-05144 Rev. ** Page 3 of 8 CY7C1046B Data Retention Characteristics Over the Operating Range Parameter VDR Conditions[10] Description Min. VCC for Data Retention ICCDR tCDR Data Retention Current [3] Com’l VCC = VDR = 2.0V, CE > VCC – 0.3V VIN > VCC – 0.3V or VIN < 0.3V Chip Deselect to Data Retention Time tR Max Unit 2.0 Operation Recovery Time V µA 200 0 ns 200 µs Data Retention Waveform DATA RETENTION MODE 3.0V VCC 3.0V VDR > 2V tR tCDR CE 1046B–5 Switching Waveforms Read Cycle No. 1[11, 12] tRC ADDRESS tAA tOHA DATA OUT PREVIOUS DATA VALID DATA VALID 1046B–6 Read Cycle No. 2 (OE Controlled)[12, 13] ADDRESS tRC CE tACE OE tHZOE tDOE DATA OUT tLZOE HIGH IMPEDANCE tLZCE VCC SUPPLY CURRENT tHZCE HIGH IMPEDANCE DATA VALID tPD tPU 50% ICC 50% ISB 1046B–7 Notes: 10. No input may exceed VCC + 0.5V. 11. Device is continuously selected. OE, CE = VIL. 12. WE is HIGH for read cycle. 13. Address valid prior to or coincident with CE transition LOW. Document #: 38-05144 Rev. ** Page 4 of 8 CY7C1046B Switching Waveforms (continued) Write Cycle No. 1 (CE Controlled)[14, 15] tWC ADDRESS tSCE CE tSA tSCE tHA tAW tPWE WE tSD DATA I/O tHD DATA VALID 1046B–8 Write Cycle No. 2 (WE Controlled, OE HIGH During Write)[14, 15] tWC ADDRESS tSCE CE tAW tSA tHA tPWE WE OE tSD DATA I/O tHD DATAIN VALID NOTE 16 tHZOE 1046B–9 Notes: 14. Data I/O is high impedance if OE = VIH. 15. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state. 16. During this period the I/Os are in the output state and input signals should not be applied. Document #: 38-05144 Rev. ** Page 5 of 8 CY7C1046B Switching Waveforms (continued) Write Cycle No. 3 (WE Controlled, OE LOW)[15] tWC ADDRESS tSCE CE tAW tSA tHA tPWE WE tSD DATA I/O NOTE 16 tHD DATA VALID tLZWE tHZWE 1046B–10 Ordering Information Speed (ns) Ordering Code Package Name Package Type 12 CY7C1046B-12VC V33 32-Lead (400-Mil) Molded SOJ 15 CY7C1046B-15VC V33 32-Lead (400-Mil) Molded SOJ 20 CY7C1046B-20VC V33 32-Lead (400-Mil) Molded SOJ 12 CY7C1046BL-12VC V33 32-Lead (400-Mil) Molded SOJ 15 CY7C1046BL-15VC V33 32-Lead (400-Mil) Molded SOJ 20 CY7C1046BL-20VC V33 32-Lead (400-Mil) Molded SOJ Operating Range Commercial Shaded areas contain advance information. Document #: 38-05144 Rev. ** Page 6 of 8 CY7C1046B Package Diagram 32-Lead (400-Mil) Molded SOJ V33 51-85033-A Document #: 38-05144 Rev. ** Page 7 of 8 © Cypress Semiconductor Corporation, 2001. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. CY7C1046B Document Title: CY7C1046B 1M x 4 Static RAM Document Number: 38-05144 REV. ECN NO. Issue Date Orig. of Change Description of Change ** 109888 09/22/01 SZV Change from Spec number: 38-00948 to 38-05144 Document #: 38-05144 Rev. ** Page 8 of 8