CY7C106BN CY7C1006BN 256K x 4 Static RAM Features Functional Description The CY7C106BN and CY7C1006BN are high-performance CMOS static RAMs organized as 262,144 words by 4 bits. Easy memory expansion is provided by an active LOW Chip Enable (CE), an active LOW Output Enable (OE), and three-state drivers. These devices have an automatic power-down feature that reduces power consumption by more than 65% when the devices are deselected. • High speed — tAA = 15 ns • CMOS for optimum speed/power • Low active power — 495 mW • Low standby power Writing to the devices is accomplished by taking Chip Enable (CE) and Write Enable (WE) inputs LOW. Data on the four I/O pins (I/O0 through I/O3) is then written into the location specified on the address pins (A0 through A17). — 275 mW • 2.0V data retention (optional) • Automatic power-down when deselected • TTL-compatible inputs and outputs Reading from the devices is accomplished by taking Chip Enable (CE) and Output Enable (OE) LOW while forcing Write Enable (WE) HIGH. Under these conditions, the contents of the memory location specified by the address pins will appear on the four I/O pins. The four input/output pins (I/O0 through I/O3) are placed in a high-impedance state when the devices are deselected (CE HIGH), the outputs are disabled (OE HIGH), or during a write operation (CE and WE LOW). The CY7C106BN is available in a standard 400-mil-wide SOJ; the CY7C1006BN is available in a standard 300-mil-wide SOJ. Logic Block Diagram Pin Configuration SOJ Top View 512 x 512 x 4 ARRAY I/O3 SENSE AMPS A1 A2 A3 A4 A5 A6 A7 A8 A9 ROW DECODER INPUT BUFFER I/O2 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 CE OE GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VCC A17 A16 A15 A14 A13 A12 A11 NC I/O3 I/O2 I/O1 I/O0 WE I/O1 I/O0 A0 POWER DOWN CE WE A10 A11 A12 A13 A14 A15 A16 A17 COLUMN DECODER Cypress Semiconductor Corporation Document #: 001-06429 Rev. ** OE • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised February 1, 2006 [+] Feedback CY7C106BN CY7C1006BN Selection Guide 7C106BN-15 7C1006BN-15 7C106BN-20 7C1006BN-20 Maximum Access Time (ns) 15 20 Maximum Operating Current (mA) 80 75 Maximum Standby Current (mA) 30 30 Maximum Ratings Current into Outputs (LOW)......................................... 20 mA (Above which the useful life may be impaired. For user guidelines, not tested.) Static Discharge Voltage ........................................... >2001V (per MIL-STD-883, Method 3015) Storage Temperature ................................–65×C to +150×C Latch-Up Current ..................................................... >200 mA Ambient Temperature with Power Applied............................................–55×C to +125×C Operating Range Supply Voltage on VCC Relative to GND[1] .... –0.5V to +7.0V DC Voltage Applied to Outputs in High Z State[1] ....................................–0.5V to VCC + 0.5V DC Input Voltage[1] .................................–0.5V to VCC + 0.5V Ambient Temperature[2] 0°C to +70°C –45°C to +85°C Range Commercial Industrial VCC 5V ± 10% Electrical Characteristics Over the Operating Range 7C106BN-15 7C1006BN-15 Parameter Description Test Conditions Min. 7C106BN-20 7C1006BN-20 Max. Min. Max. Unit VOH Output HIGH Voltage VCC = Min., IOH = –4.0 mA VOL Output LOW Voltage VCC = Min., IOL = 8.0 mA VIH Input HIGH Voltage 2.2 VCC + 0.3 2.2 VCC + 0.3 V VIL Input LOW Voltage[1] –0.3 0.8 –0.3 0.8 V IIX Input Leakage Current GND < VI < VCC –1 +1 –1 +1 mA IOZ Output Leakage Current GND < VI < VCC, Output Disabled –5 +5 –5 +5 mA IOS Output Short Circuit Current[3] VCC = Max., VOUT = GND –300 –300 mA ICC VCC Operating Supply Current VCC = Max., IOUT = 0 mA, f = fMAX = 1/tRC 80 75 mA ISB1 Automatic CE Power-Down Current —TTL Inputs Max. VCC, CE > VIH, VIN > VIH or VIN < VIL, f = fMAX 30 30 mA ISB2 Automatic CE Power-Down Current —CMOS Inputs Max. VCC, CE > VCC – 0.3V, VIN > VCC – 0.3V or VIN < 0.3V, f=0 10 10 mA 2.4 2.4 0.4 Com’l V 0.4 V Capacitance[4] Parameter CIN: Addresses CIN: Controls COUT Description Input Capacitance Test Conditions TA = 25×C, f = 1 MHz, VCC = 5.0V Output Capacitance Max. 7 10 10 Unit pF pF pF Notes: 1. VIL (min.) = –2.0V for pulse durations of less than 20 ns. 2. TA is the “instant on” case temperature. 3. Not more than 1 output should be shorted at one time. Duration of the short circuit should not exceed 30 seconds. 4. Tested initially and after any design or process changes that may affect these parameters. Document #: 001-06429 Rev. ** Page 2 of 8 [+] Feedback CY7C106BN CY7C1006BN AC Test Loads and Waveforms R1 480Ω R1 480Ω 5V 5V OUTPUT OUTPUT R2 255Ω 30 pF 90% INCLUDING JIG AND SCOPE (a) Equivalent to: 90% 10% 10% R2 GND 255Ω 5 pF INCLUDING JIG AND SCOPE ALL INPUT PULSES 3.0V Rise Time < 1V/ns Fall Time < 1V/ns (b) THÉVENIN EQUIVALENT 167Ω OUTPUT 1.73V Switching Characteristics Over the Operating Range[5] 7C106B-15 7C1006B-15 Parameter Description Min. Max. 7C106B-20 7C1006B-20 Min. Max. Unit READ CYCLE tRC Read Cycle Time tAA Address to Data Valid tOHA Data Hold from Address Change tACE CE LOW to Data Valid tDOE OE LOW to Data Valid tLZOE OE LOW to Low Z tHZOE OE HIGH to High Z[6, 7] tLZCE CE LOW to Low Z[7] tHZCE CE HIGH to High Z[6, 7] tPU CE LOW to Power-Up tPD CE HIGH to Power-Down 15 20 15 ns 20 ns 15 20 ns 7 8 ns 8 ns 3 3 0 ns 0 7 3 ns 3 7 0 ns 8 0 15 ns ns 20 ns WRITE CYCLE[8, 9] tWC Write Cycle Time 15 20 ns tSCE CE LOW to Write End 12 15 ns tAW Address Set-Up to Write End 12 15 ns tHA Address Hold from Write End 0 0 ns tSA Address Set-Up to Write Start 0 0 ns tPWE WE Pulse Width 12 15 ns tSD Data Set-Up to Write End 8 10 ns tHD Data Hold from Write End 0 0 ns 3 3 ns tLZWE tHZWE WE HIGH to Low Z[7] WE LOW to High Z[6, 7] 7 8 ns Notes: 5. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified IOL/IOH and 30–pF load capacitance. 6. tHZOE, tHZCE, and tHZWE are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured ±500 mV from steady-state voltage. 7. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device. 8. The internal write time of the memory is defined by the overlap of CE and WE LOW. CE and WE must be LOW to initiate a write, and the transition of either of these signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write. 9. The minimum write cycle time for Write Cycle No. 3 (WE controlled, OE LOW) is the sum of tHZWE and tSD. Document #: 001-06429 Rev. ** Page 3 of 8 [+] Feedback CY7C106BN CY7C1006BN Data Retention Characteristics Over the Operating Range Parameter VDR tR Min. VCC for Data Retention ICCDR tCDR Conditions[10] Description Data Retention Current [4] VCC = VDR = 2.0V, CE > VCC – 0.3V, VIN > VCC – 0.3V or VIN < 0.3V Chip Deselect to Data Retention Time [4] Max. 2.0 Operation Recovery Time Unit V 250 µA 0 ns 200 ms Data Retention Waveform DATA RETENTION MODE 4.5V VCC 4.5V VDR > 2V tCDR tR CE Switching Waveforms Read Cycle No.1[11, 12] 1 tRC ADDRESS tOHA DATA OUT tAA PREVIOUS DATA VALID DATA VALID Read Cycle No. 2 (OE Controlled)[12, 13] ADDRESS tRC CE tACE OE tHZOE tDOE DATA OUT tLZOE HIGH IMPEDANCE tLZCE VCC SUPPLY CURRENT tHZCE HIGH IMPEDANCE DATA VALID tPD tPU 50% ICC 50% ISB Notes: 10. No input may exceed VCC +0.5V. 11. Device is continuously selected, OE and CE = VIL. 12. WE is HIGH for read cycle. 13. Address valid prior to or coincident with CE transition LOW. Document #: 001-06429 Rev. ** Page 4 of 8 [+] Feedback CY7C106BN CY7C1006BN Switching Waveforms (continued) Write Cycle No. 1 (CE Controlled)[14, 15] tWC ADDRESS tSCE CE tSA tAW tHA tPWE WE tSD DATA I/O tHD DATA VALID Write Cycle No. 2 (WE Controlled, OE HIGH During Write)[14, 15] tWC ADDRESS tSCE CE tAW tSA tHA tPWE WE OE tSD DATA I/O tHD DATA VALID tHZOE Notes: 14. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state. 15. Data I/O is high impedance if OE = VIH. Document #: 001-06429 Rev. ** Page 5 of 8 [+] Feedback CY7C106BN CY7C1006BN Switching Waveforms (continued) Write Cycle No. 3 (WE Controlled, OE LOW)[9, 15] tWC ADDRESS tSCE CE tAW tSA tHA tPWE WE tSD DATA I/O tHD DATA VALID tLZWE tHZWE Truth Table CE OE WE Input/Output Mode Power H X X High Z Power-Down Standby (ISB) L L H Data Out Read Active (ICC) L X L Data In Write Active (ICC) L H H High Z Selected, Outputs Disabled Active (ICC) Ordering Information Speed (ns) 15 20 Ordering Code CY7C106BN-15VC CY7C1006BN-15VC CY7C106BN-20VC Package Diagram 51-85032 51-85031 51-85032 Package Type 28-Lead (400-Mil) Molded SOJ 28-Lead (300-Mil) Molded SOJ 28-Lead (400-Mil) Molded SOJ Operating Range Commercial Commercial Please contact local sales representative regarding availability of these parts. Document #: 001-06429 Rev. ** Page 6 of 8 [+] Feedback CY7C106BN CY7C1006BN Package Diagrams 28-pin (300-Mil) Molded SOJ (51-85031) NOTE : 1. JEDEC STD REF MO088 2. BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION/END FLASH MOLD PROTRUSION/END FLASH SHALL NOT EXCEED 0.006 in (0.152 mm) PER SIDE MIN. MAX. 3. DIMENSIONS IN INCHES DETAIL A EXTERNAL LEAD DESIGN PIN 1 ID 14 1 0.291 0.300 15 0.330 0.350 0.026 0.032 0.013 0.019 28 0.014 0.020 OPTION 1 0.697 0.713 OPTION 2 SEATING PLANE 0.120 0.140 0.007 0.013 A 0.050 TYP. 0.004 0.025 MIN. 0.262 0.272 51-85031-*C 28-Lead (400-Mil) Molded SOJ (51-85032) PIN 1 I.D 14 1 .395 .405 15 MIN. MAX. DIMENSIONS IN INCHES .435 .445 28 .720 .730 SEATING PLANE .128 .148 .026 .032 .050 TYP. .015 .020 .007 .013 0.004 .025 MIN. .360 .380 51-85032.*B All product or company names mentioned in this document may be the trademarks of their respective holders. Document #: 001-06429 Rev. ** Page 7 of 8 © Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. [+] Feedback CY7C106BN CY7C1006BN Document History Page Document Title: CY7C106BN/CY7C1006BN 256K x 4 Static RAM Document Number: 001-06429 REV. ECN NO. Issue Date Orig. of Change Description of Change ** 423847 See ECN NXR New Data sheet Document #: 001-06429 Rev. ** Page 8 of 8 [+] Feedback