SPECTRALINEAR CY28RS400OXC

CY28RS400
Clock Generator for ATI£ RS400 Chipset
Features
• Low-voltage frequency select input
• I2C support with readback capabilities
• Supports Intel£ CPU
• Selectable CPU frequencies
• Ideal Lexmark Spread Spectrum profile for maximum
electromagnetic interference (EMI) reduction
• Differential CPU clock pairs
• 3.3V power supply
• 100 MHz differential SRC clocks
• 56-pin SSOP and TSSOP packages
• 48 MHz USB clock
• 33 MHz PCI clock
Block Diagram
XIN
XOUT
CPU_STP#
CLKREQ[0:1]#
VDD_REF
REF[0:2]
PLL Ref Freq
Divider
Network
FS_[C:A]
VTT_PWRGD#
IREF
PCI
REF
USB_48
x8
x1
x3
x1
PLL2
I2C
Logic
Xin
XOUT
VDD_48
VDD_CPU
USB_48
CPUT[0:2], CPUC[0:2],
VSS_48
VDD_SRC
VTT_PWRGD#/PD
SRCT[0:5],SRCC[0:5]
SCLK
SDATA
VDD_SRCS
SRCST[0:1],SRCSC[0:1]
FSC
CLKREQ#0
VDD_PCI
CLKREQ#1
PCI
SRCT5
SRCC5
VDD_SRC
VSS_SRC
VDD_48 MHz
SRCT4
SRCC4
SRCT3
USB_48
SRCC3
VSS_SRC
VDD_SRC
SRCT2
SRCC2
SRCT1
SRCC1
VSS_SRC
SRCST1
SRCSC1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
CY28RS400
PD
SDATA
SCLK
SRC
x3
Pin Configuration
XTAL
OSC
PLL1
CPU
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
VDD_REF
VSS_REF
REF0/FSA
REF1/FSB
REF2
VDD_PCI
PCI0/409_410
VSS_PCI
CPU_STOP#
CPUT0
CPUC0
VDD_CPU
VSS_CPU
CPUT1
CPUC1
CPUT2
CPUC2
VDDA
VSSA
IREF
VSS_SRC1
VDD_SRC1
SRCT0
SRCC0
VDD_SRCS
VSS_SRCS
SRCST0
SRCSC0
56 SSOP/TSSOP
Rev 1.0, November 22, 2006
2200 Laurelwood Road, Santa Clara, CA 95054
Page 1 of 18
Tel:(408) 855-0555
Fax:(408) 855-0550
www.SpectraLinear.com
CY28RS400
Pin Description
Pin No.
Name
47,46,43,42,
41,40
CPUT/C[2:0]
50
PCI0/409_410
I/O,
PD
37
IREF
I
54
REF0/ FSA
I/O, SE, 14.318 MHz REF clock ouput/ CPU Frequency Select. Intel£ Type-5 buffer.
53
REF1/FSB
I/O, SE 14.318 MHz REF clock ouput/ CPU Frequency Select. Intel Type-5 buffer.
52
REF2
7
SCLK
8
SDATA
27, 28, 30, 29
SRCST/C[1:0]
12, 13, 16,
17, 18, 19,
22, 23, 24, 25
,34,33
SRCT/C[5:0]
10,11
CLKREQ#[0:1]
Type
Description
O, DIF Differential CPU clock output.
Intel Type-X buffer.
33 MHz clock output/CPU Frequency table Select
Intel Type-5 buffer.
0 = 410 frequency select table
1 = 409 frequency select table.
This has an internal pull-down
A precision resistor attached to this pin is connected to the internal current reference.
O, SE 14.318 MHz REF clock ouput. Intel Type-5 buffer.
I,PU
SMBus-compatible SCLOCK.This pin has an internal pullup, but is tri-stated in power-down.
I/O, PU SMBus compatible SDATA.This pin has an internal pullup, but is tri-stated in power-down.
O, DIF Differential Selectable Serial reference clock. Intel Type-X buffer. Includes overclock
support through SMBUS
O, DIF 100 MHz Differential Serial reference clock. Intel Type-X buffer.
I, SE, Output Enable control for SRCT/C. Output enable control required by Minicard
PD specification. These pins have an internal pull-down.
0 = Selected SRC outputs are enabled, 1 = Selected SRC outputs are disabled
4
USB_48
6
VTT_PWRGD#/PD
O, SE 48 MHz clock output. Intel Type-3A buffer.
I
PD
3.3V LVTTL input. This pin is a level sensitive strobe used to latch the FS_A, FS_B,
FS_C and 409_410 inputs. After asserting VTT_PWRGD# (active low), this pin
becomes a realtime input for asserting power down (active high)
48
CPU_STP#
I, PU
3.3V LVTTL input. This pin is used to gate the CPU outputs. CPU outputs are turned
off two cycles after assertion of this pin
9
FSC
I
3
VDD_48
PWR
3.3V LVTTL input. CPU Clock Frequency Select
45
VDD_CPU
PWR
3.3V power supply for CPU outputs
51
VDD_PCI
PWR
3.3V power supply for PCI outputs
3.3V power supply for USB outputs
56
VDD_REF
PWR
3.3V power supply for REF outputs
14, 21
VDD_SRC
PWR
3.3V power supply for SRC outputs
35
VDD_SRC1
PWR
3.3V power supply for SRC outputs
32
VDD_SRCS
PWR
3.3V power supply for SRCS outputs
39
VDDA
PWR
3.3V Analog Power for PLLs
5
VSS_48
GND
Ground for USB outputs
44
VSS_CPU
GND
Ground for CPU outputs
49
VSS_PCI
GND
Ground for PCI outputs
55
VSS_REF
GND
Ground for REF outputs
15, 20, 26
VSS_SRC
GND
Ground for SRC outputs
36
VSS_SRC1
GND
Ground for SRC outputs
31
VSS_SRCS
GND
Ground for SRCS outputs
38
VSSA
GND
1
XIN
I
14.318 MHz Crystal Input
2
XOUT
O
14.318 MHz Crystal Output
Rev 1.0, November 22, 2006
Analog Ground
Page 2 of 18
CY28RS400
Frequency Select Pins (FS_A, FS_B, FS_C and
409_410)
a valid low on VTT_PWRGD# has been sampled, all further
VTT_PWRGD#, FS_A, FS_B, FS_C and 409-410 transitions
will be ignored. There are 2 CPU frequency select tables. One
based on the CK409 specifications and one based on the
CK410 specifications. The table to be used is determined by
the value latched on the PCI0/409_410 pin by the
VTT_PWRGD/PD# pin. A '0' on this pin selects the 410
frequency table and a '1' on this pin selects the 409 frequency
table. In the 409 table, only the FS_A and FS_B pins influence
the frequency selection.
Host clock frequency selection is achieved by applying the
appropriate logic levels to FS_A, FS_B, FS_C and 409_410
inputs prior to VTT_PWRGD# assertion (as seen by the clock
synthesizer). Upon VTT_PWRGD# being sampled low by the
clock chip (indicating processor VTT voltage is stable), the
clock chip samples the FS_A, FS_B, FS_C and 409_410 input
values. For all logic levels of FS_A, FS_B, FS_C and 409_410
VTT_PWRGD# employs a one-shot functionality in that once
Table 1. Frequency Select Table (FS_A FS_B FS_C) 410 mode, 409_410 = 0
FS_C
FS_B
FS_A
CPU
SRC
PCIF/PCI
REF0
USB
1
0
1
100 MHz
100 MHz
33 MHz
14.318 MHz
48 MHz
0
0
1
133 MHz
100 MHz
33 MHz
14.318 MHz
48 MHz
0
1
0
200 MHz
100 MHz
33 MHz
14.318 MHz
48 MHz
0
0
0
266 MHz
100 MHz
33 MHz
14.318 MHz
48 MHz
1
1
1
Reserved
100 MHz
33 MHz
14.318 MHz
48 MHz
Table 2. Frequency Select Table (FS_A FS_B) 410 mode, 409_410 = 1
FS_B
FS_A
CPU
SRC
PCIF/PCI
REF0
USB
0
0
100 MHz
100 MHz
33 MHz
14.318 MHz
48 MHz
0
1
133 MHz
100 MHz
33 MHz
14.318 MHz
48 MHz
1
0
200 MHz
100 MHz
33 MHz
14.318 MHz
48 MHz
Serial Data Interface
Data Protocol
To enhance the flexibility and function of the clock synthesizer,
a two-signal serial interface is provided. Through the Serial
Data Interface, various device functions, such as individual
clock output buffers, can be individually enabled or disabled.
The registers associated with the Serial Data Interface
initializes to their default setting upon power-up, and therefore
use of this interface is optional. Clock device register changes
are normally made upon system initialization, if any are
required. The interface cannot be used during system
operation for power management functions.
The clock driver serial protocol accepts byte write, byte read,
block write, and block read operations from the controller. For
block write/read operation, the bytes must be accessed in
sequential order from lowest to highest byte (most significant
bit first) with the ability to stop after any complete byte has
been transferred. For byte write and byte read operations, the
system controller can access individually indexed bytes. The
offset of the indexed byte is encoded in the command code,
as described in Table 3.
The block write and block read protocol is outlined in Table 4
while Table 5 outlines the corresponding byte write and byte
read protocol. The slave receiver address is 11010010 (D2h).
Table 3. Command Code Definition
Bit
7
Description
0 = Block read or block write operation, 1 = Byte read or byte write operation
(6:5)
Chip select address, set to ‘00’ to access device
(4:0)
Byte offset for byte read or byte write operation. For block read or block write operations, these bits should be '00000'
Table 4. Block Read and Block Write Protocol
Block Write Protocol
Bit
1
8:2
9
Description
Start
Slave address – 7 bits
Write
Block Read Protocol
Bit
1
8:2
9
Description
Start
Slave address – 7 bits
Write
10
Acknowledge from slave
10
Acknowledge from slave
18:11
Command Code – 8 bits
18:11
Command Code – 8 bits
19
Acknowledge from slave
19
Acknowledge from slave
Rev 1.0, November 22, 2006
Page 3 of 18
CY28RS400
Table 4. Block Read and Block Write Protocol (continued)
Block Write Protocol
Bit
27:20
28
36:29
37
45:38
Description
Byte Count – 8 bits
Block Read Protocol
Bit
20
Acknowledge from slave
Data byte 1 – 8 bits
Acknowledge from slave
Data byte 2 – 8 bits
46
Acknowledge from slave
....
Data Byte /Slave Acknowledges
....
Data Byte N –8 bits
....
Acknowledge from slave
....
Stop
27:21
Description
Repeat start
Slave address – 7 bits
28
Read = 1
29
Acknowledge from slave
37:30
38
46:39
47
55:48
Byte Count from slave – 8 bits
Acknowledge
Data byte 1 from slave – 8 bits
Acknowledge
Data byte 2 from slave – 8 bits
56
Acknowledge
....
Data bytes from slave / Acknowledge
....
Data Byte N from slave – 8 bits
....
NOT Acknowledge
Table 5. Byte Read and Byte Write Protocol
Byte Write Protocol
Bit
1
8:2
9
Description
Start
Slave address – 7 bits
Write
Byte Read Protocol
Bit
1
8:2
9
Description
Start
Slave address – 7 bits
Write
10
Acknowledge from slave
10
Acknowledge from slave
18:11
Command Code – 8 bits
18:11
Command Code – 8 bits
19
Acknowledge from slave
19
Acknowledge from slave
Data byte – 8 bits
20
Repeated start
27:20
28
Acknowledge from slave
29
Stop
Rev 1.0, November 22, 2006
27:21
28
Slave address – 7 bits
Read
29
Acknowledge from slave
37:30
Data from slave – 8 bits
38
NOT Acknowledge
39
Stop
Page 4 of 18
CY28RS400
Control Registers
Byte 0:Control Register 0
Bit
@Pup
Name
Description
7
1
SRC[T/C]5
SRC[T/C]5 Output Enable
0 = Disable (Hi-Z), 1 = Enable
6
1
SRC[T/C]4
SRC[T/C]4 Output Enable
0 = Disable (Hi-Z), 1 = Enable
5
1
SRC[T/C]3
SRC[T/C]3 Output Enable
0 = Disable (Hi-Z), 1 = Enable
4
1
SRC[T/C]2
SRC[T/C]2 Output Enable
0 = Disable (Hi-Z), 1 = Enable
3
1
SRC[T/C]1
SRC[T/C]1 Output Enable
0 = Disable (Hi-Z), 1 = Enable
2
1
SRC [T/C]0
SRC[T/C]0 Output Enable
0 = Disable (Hi-Z), 1 = Enable
1
1
SRCS[T/C]1
SRCS[T/C]1 Output Enable
0 = Disable (Hi-Z), 1 = Enable
0
1
SRCS[T/C]0
SRCS[T/C]0 Output Enable
0 = Disable (Hi-Z), 1 = Enable
Byte 1: Control Register 1
Bit
@Pup
Name
Description
7
1
REF2
REF2 Output Enable
0 = Disable, 1 = Enable
6
1
REF1
REF1 Output Enable
0 = Disable, 1 = Enable
5
1
REF0
REF0 Output Enable
0 = Disable, 1 = Enable
4
1
PCI0
PCI0 Output Enable
0 = Disable, 1 = Enable
3
1
USB_48
2
1
CPU[T/C]2
CPU[T/C]2 Output Enable
0 = Disable (Hi-Z), 1 = Enable
1
1
CPU[T/C]1
CPU[T/C]1 Output Enable
0 = Disable (Hi-Z), 1 = Enable
0
1
CPU[T/C]0
CPU[T/C]0 Output Enable
0 = Disable (Hi-Z), 1 = Enable
USB_48MHz Output Enable
0 = Disable, 1 = Enable
Byte 2: Control Register 2
Bit
@Pup
Name
7
1
CPUT/C
SRCT/C
Spread Spectrum Selection
‘0’ = -0.35%
‘1’ = -0.50%
6
1
USB_48
48MHz Output Drive Strength
0 = 1x, 1 = 2x
5
1
PCI
33MHz Output Drive Strength
0 = 1x, 1 = 2x
4
0
Reserved
Reserved
3
1
Reserved
Reserved
2
0
CPU
SRC
1
1
Reserved
Rev 1.0, November 22, 2006
Description
CPU/SRC Spread Spectrum Enable
0 = Spread off, 1 = Spread on
Reserved
Page 5 of 18
CY28RS400
Byte 2: Control Register 2 (continued)
Bit
@Pup
Name
0
1
Reserved
Description
Reserved
Byte 3: Control Register 3
Bit
@Pup
Name
7
1
CLKREQ#
Description
6
0
CPU
CPU pd drive mode
0 = CPU clocks driven when power down, 1 = CPU clocks tri-state
5
1
SRC
SRC pd drive mode
0 = SRC clocks driven when power down, 1 = SRC clocks tri-state
4
0
CPU
CPU_STOP# drive mode
0 = CPU clocks driven , 1 = CPU clocks tri-state
3
1
CPU2
Allow control of CPU2 with CPU_STOP#
0 = CPU2 is free running, 1 = CPU2 is stopped with CPU_STOP#
2
1
CPU1
Allow control of CPU1 with CPU_STOP#
0 = CPU1 is free running, 1 = CPU1 is stopped with CPU_STOP#
1
1
CPU0
Allow control of CPU0 with CPU_STOP#
0 = CPU0 is free running, 1 = CPU0 is stopped with CPU_STOP#
0
1
Reserved
CLKREQ# drive mode
0 = SRC clocks driven when stopped, 1 = SRC clocks tri-state when
stopped
Reserved
Byte 4: Control Register 4
Bit
@Pup
Name
Description
7
0
SRC[T/C]5
SRC[T/C]5 CLKREQ0 control
1 = SRC[T/C]5 stoppable by CLKREQ#0 pin
0 = SRC[T/C]5 free running
6
0
SRC[T/C]4
SRC[T/C]4 CLKREQ#0 control
1 = SRC[T/C]4 stoppable by CLKREQ#0 pin
0 = SRC[T/C]4 free running
5
0
SRC[T/C]3
SRC[T/C]3 CLKREQ#0 control
1 = SRC[T/C]3 stoppable by CLKREQ#0 pin
0 = SRC[T/C]3 free running
4
0
SRC[T/C]2
SRC[T/C]2 CLKREQ#0 control
1 = SRC[T/C]2 stoppable by CLKREQ#0 pin
0 = SRC[T/C]2 free running
3
0
SRC[T/C]1
SRC[T/C]1 CLKREQ#0 control
1 = SRC[T/C]1 stoppable by CLKREQ#0 pin
0 = SRC[T/C]1 free running
2
0
SRC[T/C]0
SRC[T/C]0 CLKREQ#0 control
1 = SRC[T/C]1 stoppable by CLKREQ#0 pin
0 = SRC[T/C]1 free running
1
1
Reserved
Reserved
0
1
Reserved
Reserved
Byte 5: Control Register 5
Bit
@Pup
Name
7
0
SRC[T/C]5
SRC[T/C]5 CLKREQ#1 control
1 = SRC[T/C]5 stoppable by CLKREQ#1 pin
0 = SRC[T/C]5 free running
6
0
SRC[T/C]4
SRC[T/C]4 CLKREQ#1 control
1 = SRC[T/C]4 stoppable by CLKREQ#1 pin
0 = SRC[T/C]4 free running
Rev 1.0, November 22, 2006
Description
Page 6 of 18
CY28RS400
Byte 5: Control Register 5 (continued)
Bit
@Pup
Name
Description
5
0
SRC[T/C]3
SRC[T/C]3 CLKREQ#1 control
1 = SRC[T/C]3 stoppable by CLKREQ#1 pin
0 = SRC[T/C]3 free running
4
0
SRC[T/C]2
SRC[T/C]2 CLKREQ#1 control
1 = SRC[T/C]2 stoppable by CLKREQ#1 pin
0 = SRC[T/C]2 free running
3
0
SRC[T/C]1
SRC[T/C]1 CLKREQ#1 control
1 = SRC[T/C]1 stoppable by CLKREQ#1 pin
0 = SRC[T/C]1 free running
2
0
SRC[T/C]0
SRC[T/C]0 CLKREQ#1 control
1 = SRC[T/C]1 stoppable by CLKREQ#1 pin
0 = SRC[T/C]1 free running
1
0
Reserved
Reserved
0
0
Reserved
Reserved
Byte 6: Control Register 6
Bit
@Pup
Name
Description
7
0
TEST_SEL
6
0
TEST_MODE
5
0
REF
4
0
Reserved
Reserved
3
HW
409_410
409_410 reflects the value of the 409_410 pin sampled on power up. 0 =
409_410 was low during VTT_PWRGD# assertion
2
HW
FS_C
FS_C Reflects the value of the FS_C pin sampled on power up. 0 = FS_C
was low during VTT_PWRGD# assertion.
1
HW
FS_B
FS_B Reflects the value of the FS_B pin sampled on power up. 0 = FS_B
was low during VTT_PWRGD# assertion.
0
HW
FS_A
FS_A Reflects the value of the FS_A pin sampled on power up. 0 = FS_A
was low during VTT_PWRGD# assertion.
Name
Description
REF/N or Tri-state Select
1 = REF/N Clock, 0 = Tri-state
Test Clock Mode Entry Control
1 = REF/N or Tri-state mode, 0 = Normal operation
REF output drive strength.
0 = Low drive, 1 = High drive.
Byte 7: Vendor ID
Bit
@Pup
7
0
Revision Code Bit 3
6
0
Revision Code Bit 2
5
0
Revision Code Bit 1
4
1
Revision Code Bit 0
3
1
Vendor ID Bit 3
2
0
Vendor ID Bit 2
1
0
Vendor ID Bit 1
0
0
Vendor ID Bit 0
Rev 1.0, November 22, 2006
Page 7 of 18
CY28RS400
Crystal Recommendations
The CY28RS400 requires a Parallel Resonance Crystal.
Substituting a series resonance crystal will cause the
CY28RS400 to operate at the wrong frequency and violate the
ppm specification. For most applications there is a 300-ppm
frequency shift between series and parallel crystals due to
incorrect loading.
Table 6. Crystal Recommendations
Frequency
(Fund)
Cut
Loading Load Cap
Drive
(max.)
Shunt Cap
(max.)
Motional
(max.)
Tolerance
(max.)
Stability
(max.)
Aging
(max.)
14.31818 MHz
AT
Parallel
0.1 mW
5 pF
0.016 pF
35 ppm
30 ppm
5 ppm
20 pF
Crystal Loading
Crystal loading plays a critical role in achieving low ppm performance. To realize low ppm performance, the total capacitance
the crystal will see must be considered to calculate the appropriate capacitive loading (CL).
The following diagram shows a typical crystal configuration
using the two trim capacitors. An important clarification for the
following discussion is that the trim capacitors are in series
with the crystal not parallel. It’s a common misconception that
load capacitors are in parallel with the crystal and should be
approximately equal to the load capacitance of the crystal.
This is not true.
Figure 1. Crystal Capacitive Clarification
Calculating Load Capacitors
In addition to the standard external trim capacitors, trace
capacitance and pin capacitance must also be considered to
correctly calculate crystal loading. As mentioned previously,
the capacitance on each side of the crystal is in series with the
crystal. This means the total capacitance on each side of the
crystal must be twice the specified crystal load capacitance
(CL). While the capacitance on each side of the crystal is in
series with the crystal, trim capacitors (Ce1,Ce2) should be
calculated to provide equal capacitive loading on both sides.
Clock Chip
Ci2
Ci1
Pin
3 to 6p
X2
X1
Cs1
Cs2
Trace
2.8pF
XTAL
Ce1
Ce2
Trim
33pF
Figure 2. Crystal Loading Example
Rev 1.0, November 22, 2006
Page 8 of 18
CY28RS400
As mentioned previously, the capacitance on each side of the
crystal is in series with the crystal. This mean the total capacitance on each side of the crystal must be twice the specified
load capacitance (CL). While the capacitance on each side of
the crystal is in series with the crystal, trim capacitors
(Ce1,Ce2) should be calculated to provide equal capacitance
loading on both sides.
Use the following formulas to calculate the trim capacitor
values for Ce1 and Ce2.
Load Capacitance (each side)
Ce = 2 * CL – (Cs + Ci)
Total Capacitance (as seen by the crystal)
CLe
=
1
1
( Ce1 + Cs1
+ Ci1 +
1
Ce2 + Cs2 + Ci2
)
CL ................................................... Crystal load capacitance
CLe .........................................Actual loading seen by crystal
using standard value trim capacitors
Ce .....................................................External trim capacitors
Cs ............................................. Stray capacitance (terraced)
Ci .......................................................... Internal capacitance
(lead frame, bond wires etc.)
CL ................................................... Crystal load capacitance
CLe .........................................Actual loading seen by crystal
using standard value trim capacitors
Ce .....................................................External trim capacitors
Cs ............................................. Stray capacitance (terraced)
Ci .......................................................... Internal capacitance
(lead frame, bond wires etc.)
PD (Power-down) Clarification
The VTT_PWRGD# /PD pin is a dual function pin. During initial
power up, the pin functions as VTT_PWRGD#. Once
VTT_PWRGD# has been sampled low by the clock chip, the
pin assumes PD functionality. The PD pin is an asynchronous
active high input used to shut off all clocks cleanly prior to
shutting off power to the device. This signal is synchronized
internal to the device prior to powering down the clock synthesizer. PD is also an asynchronous input for powering up the
system. When PD is asserted high, all clocks need to be driven
to a low value and held prior to turning off the VCOs and the
crystal oscillator.
PD (Power-down) – Assertion
When PD is sampled high by two consecutive rising edges of
CPUC, all single-ended outputs will be held low on their next
high to low transition and differential clocks must held high or
Hi-Zd (depending on the state of the control register drive
mode bit) on the next diff clock# high to low transition within
four clock periods. When the SMBus PD drive mode bit corresponding to the differential (CPU, SRC, and DOT) clock output
of interest is programmed to ‘0’, the clock output are held with
“Diff clock” pin driven high at 2 x Iref, and “Diff clock#” tristate.
If the control register PD drive mode bit corresponding to the
output of interest is programmed to “1”, then both the “Diff
clock” and the “Diff clock#” are three-state. Note the example
below shows CPUT = 133 MHz and PD drive mode = ‘1’ for all
differential outputs. This diagram and description is applicable
to valid CPU frequencies 100,133,200 and 266MHz. In the
event that PD mode is desired as the initial power-on state, PD
must be asserted high in less than 10 uS after asserting
Vtt_PwrGd#.
PD Deassertion
The power-up latency is less than 1.8 ms. This is the time from
the deassertion of the PD pin or the ramping of the power
supply until the time that stable clocks are output from the
clock chip. All differential outputs stopped in a three-state
condition resulting from power down will be driven high in less
than 300 Ps of PD deassertion to a voltage greater than 200
mV. After the clock chip’s internal PLL is powered up and
locked, all outputs will be enabled within a few clock cycles of
each other. Below is an example showing the relationship of
clocks coming up.
PD
CPUT, 133MHz
CPUC, 133MHz
SRCT 100MHz
SRCC 100MHz
USB, 48MHz
DOT96T
DOT96C
PCI, 33 MHz
REF
Figure 3. Power-down Assertion Timing Waveform
Rev 1.0, November 22, 2006
Page 9 of 18
CY28RS400
Tstable
<1.8nS
PD
CPUT, 133MHz
CPUC, 133MHz
SRCT 100MHz
SRCC 100MHz
USB, 48MHz
DOT96T
DOT96C
PCI, 33MHz
REF
Tdrive_PWRDN#
<300PS, >200mV
Figure 4. Power-down Deassertion Timing Waveform
CPU_STP# Assertion
The CPU_STP# signal is an active low input used for
synchronous stopping and starting the CPU output clocks
while the rest of the clock generator continues to function.
When the CPU_STP# pin is asserted, all CPU outputs that are
set with the SMBus configuration to be stoppable via assertion
of CPU_STP# will be stopped within two–six CPU clock
periods after being sampled by two rising edges of the internal
CPUC clock. The final states of the stopped CPU signals are
CPUT = HIGH and CPUC = LOW. There is no change to the
output drive current values during the stopped state. The
CPUT is driven HIGH with a current value equal to 6 x (Iref),
and the CPUC signal will be Hi-Z. When the control register
CPU_STP Hi-Z bit corresponding to the output of interest is
programmed to ‘1’, the final state of the stopped CPU clock is
low (due to external 50 ohm pull-down resistor), both CPUT
clock and CPUC clock outputs will not be driven.
CPU_STP#
CPUT
CPUC
Figure 5. CPU_STP# Assertion Waveform
CPU_STP# Deassertion
The deassertion of the CPU_STP# signal will cause all CPU
outputs that were stopped to resume normal operation in a
synchronous manner. Synchronous manner meaning that no
short or stretched clock pulses will be produce when the clock
resumes. The maximum latency from the deassertion to active
outputs is 2 - 6 CPU clock cycles.
CPU_STP#
CPUT
CPUC
CPUT Internal
CPUC Internal
Tdrive_CPU_STP#,10nS>200mV
Figure 6. CPU_STP# Deassertion Waveform
Rev 1.0, November 22, 2006
Page 10 of 18
CY28RS400
1.8mS
CPU_STOP#
PD
CPUT(Free Running
CPUC(Free Running
CPUT(Stoppable)
CPUC(Stoppable)
Figure 7. CPU_STP#= Driven, CPU_PD = Driven
1.8mS
CPU_STOP#
PD
CPUT(Free Running)
CPUC(Free Running)
CPUT(Stoppable)
CPUC(Stoppable)
Figure 8. CPU_STP# = Hi-Z, CPU_PD = Hi-Z
CLK_REQ[0:1]# Description
The CLKREQ#[1:0] signals are active low input used for clean
stopping and starting selected SRC outputs. The outputs
controlled by CLKREQ#[1:0] are determined by the settings in
register bytes 4 and 5. The CLKREQ# signal is a de-bounced
signal in that it’s state must remain unchanged during two
consecutive rising edges of DIFC to be recognized as a valid
assertion or de-assertion. (The assertion and de-assertion of
this signal is absolutely asynchronous).
CLK_REQ[0:1]# De-assertion [Low to High transition]
The impact of deasserting the CLKREQ#[1:0] pins is all DIF
outputs that are set in the control registers to stoppable via
de-assertion of CLKREQ#[1:0] are to be stopped after their
next transition. When the control register CLKREQ# drive
mode bit is programmed to ‘0’, the final state of all stopped
SRC signals is SRCT clock = High and SRCC = Low. There is
to be no change to the output drive current values, SRCT will
be driven high with a current value equal 6 x Iref,. When the
control register CLKREQ# drive mode bit is programmed to
‘1’, the final state of all stopped DIF signals is low, both SRCT
clock and SRCC clock outputs will not be driven.
CLK_REQ[0:1]# Assertion [High to Low transition]
All differential outputs that were stopped are to resume normal
operation in a glitch free manner. The maximum latency from
the assertion to active outputs is between two–six SRC clock
periods (two clocks are shown) with all SRC outputs resuming
simultaneously. If the CLKREQ#
drive mode bit is
programmed to ‘1’ (three-state), the all stopped SRC outputs
must be driven high within 10 ns of CLKREQ#[1:0] assertion
to a voltage greater than 200 mV.
CLKREQ#X
SRCT(free running)
SRCC(free running)
SRCT(stoppable)
SRCT(stoppable)
Figure 9. CLK_REQ#[0:1] Assertion/Deassertion Waveform
Rev 1.0, November 22, 2006
Page 11 of 18
CY28RS400
FS_A, FS_B,FS_C
VTT_PW RGD#
PW RGD_VRM
0.2-0.3mS
Delay
VDD Clock Gen
State 0
Clock State
W ait for
VTT_PW RGD#
State 1
State 2
Off
Clock Outputs
State 3
On
On
Off
Clock VCO
Device is not affected,
VTT_PW RGD# is ignored
Sample Sels
Figure 10. VTT_PWRGD# Timing Diagram
S2
S1
Delay
>0.25mS
VTT_PWRGD# = Low
Sample
Inputs straps
VDD_A = 2.0V
Wait for <1.8ms
S0
Power Off
S3
VDD_A = off
Normal
Operation
Enable Outputs
VTT_PWRGD# = toggle
Figure 11. Clock Generator Power-up/Run State Diagram
Rev 1.0, November 22, 2006
Page 12 of 18
CY28RS400
Absolute Maximum Conditions
Parameter
Description
Condition
Min.
Max.
Unit
VDD
Core Supply Voltage
–0.5
4.6
V
VDDA
Analog Supply Voltage
–0.5
4.6
V
VIN
Input Voltage
Relative to VSS
–0.5
VDD+0.5
VDC
TS
Temperature, Storage
Non Functional
–65
+150
°C
TA
Temperature, Operating Ambient
Functional
0
70
°C
TJ
Temperature, Junction
Functional
–
150
°C
ESDHBM
ØJC
ØJA
ESD Protection (Human Body Model)
MIL-STD-883, Method 3015
2000
–
V
Dissipation, Junction to Case
Mil-Spec 883E Method 1012.1
–
20
°C/W
–
60
°C/W
Dissipation, Junction to Ambient
JEDEC (JESD 51)
UL-94
Flammability Rating
At 1/8 in.
MSL
Moisture Sensitivity Level
V–0
1
Multiple Supplies: The voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required.
DC Electrical Specifications
Parameter
Description
VDD_REF, 3.3V Operating Voltage
VDD_CPU,
VDD_PCI,
VDD_SRC,
VDD_48,
VIL_FS
FS_A,FS_B and FS_C Input Low Voltage
VIH_FS
FS_A,FS_B and FS_C Input Low Voltage
VILSMBUS Input Low Voltage
Condition
3.3V ± 5%
SDATA, SCLK
VIHSMBUS Input High Voltage
SDATA, SCLK
VIL
Input Low Voltage
VDD
VIH
Input High Voltage
IIL
Input Leakage Current
except Pull-ups or Pull downs 0<VIN<VDD
Min.
Max.
Unit
3.135
3.465
V
VSS – 0.3
0.35
V
0.7
VDD + 0.5
V
–
1.0
V
2.2
–
V
VSS – 0.3
0.8
V
2.0
VDD + 0.3
V
–5
5
mA
VOL
Output Low Voltage
IOL = 1 mA
–
0.4
V
VOH
Output High Voltage
IOH = 1 mA
2.4
-
V
IOZ
High-Impedance Output Current
–10
10
uA
CIN
Input Pin Capacitance
3
5
pF
Output Pin Capacitance
3
5
pF
Pin Inductance
–
7
nH
COUT
LIN
VXIH
Xin High Voltage
0.7*VDD
VDD
V
VXIL
Xin Low Voltage
0
0.3*VDD
V
IDD
Dynamic Supply Current
At max load and frequency
–
450
mA
IPDD
Power Down Supply Current
PD asserted, Outputs driven
–
75
mA
IPDT
Power Down Supply Current
PD asserted, Outputs Hi-Z
–
2
mA
Condition
Min.
Max.
Unit
The device will operate reliably with
input duty cycles up to 30/70 but the
REF clock duty cycle will not be
within specification
47.5
52.5
%
AC Electrical Specifications
Parameter
Description
Crystal
TDC
XIN Duty Cycle
Rev 1.0, November 22, 2006
Page 13 of 18
CY28RS400
AC Electrical Specifications (continued)
Condition
Min.
Max.
Unit
TPERIOD
Parameter
XIN Period
Description
When XIN is driven from an external
clock source
69.841
71.0
ns
T R / TF
XIN Rise and Fall Times
Measured between 0.3VDD and
0.7VDD
–
10.0
ns
TCCJ
XIN Cycle to Cycle Jitter
As an average over 1-Ps duration
–
500
ps
LACC
Long-term Accuracy
Over 150 ms
–
300
ppm
45
55
CPU at 0.7V
TDC
CPUT and CPUC Duty Cycle
Measured at crossing point VOX
TPERIOD
100-MHz CPUT and CPUC Period
Measured at crossing point VOX
9.997001 10.00300
ns
TPERIOD
133-MHz CPUT and CPUC Period
Measured at crossing point VOX
7.497751 7.502251
ns
TPERIOD
200-MHz CPUT and CPUC Period
Measured at crossing point VOX
4.998500 5.001500
ns
TPERIOD
266-MHz CPUT and CPUC Period
Measured at crossing point VOX
3.748875 3.751125
ns
TPERIODSS
100-MHz CPUT and CPUC Period, SSC
Measured at crossing point VOX
9.997001 10.05327
ns
TPERIODSS
133-MHz CPUT and CPUC Period, SSC
Measured at crossing point VOX
7.497751 7.539950
ns
TPERIODSS
200-MHz CPUT and CPUC Period, SSC
Measured at crossing point VOX
4.998500 5.026634
ns
TPERIODSS
266-MHz CPUT and CPUC Period, SSC
Measured at crossing point VOX
3.748875 3.769975
ns
TPERIODAbs
100-MHz CPUT and CPUC Absolute period
Measured at crossing point VOX
9.912001 10.08800
ns
TPERIODAbs
133-MHz CPUT and CPUC Absolute period
Measured at crossing point VOX
7.412751 7.587251
ns
TPERIODAbs
200-MHz CPUT and CPUC Absolute period
Measured at crossing point VOX
4.913500 5.086500
ns
TPERIODAbs
266-MHz CPUT and CPUC Absolute period
Measured at crossing point VOX
3.663875 3.836125
ns
TPERI-
100-MHz CPUT and CPUC Absolute period,
SSC
Measured at crossing point VOX
9.912001 10.13827
ns
133-MHz CPUT and CPUC Absolute period,
SSC
Measured at crossing point VOX
7.412751 7.624950
ns
200-MHz CPUT and CPUC Absolute period,
SSC
Measured at crossing point VOX
4.913500 5.111634
ns
Measured at crossing point VOX
3.663875 3.854975
ns
ODSSAbs
266-MHz CPUT and CPUC Absolute period,
SSC
TCCJ
CPUT/C Cycle to Cycle Jitter
Measured at crossing point VOX
T R / TF
CPUT and CPUC Rise and Fall Times
Measured from VOL = 0.175 to
VOH = 0.525V
TRFM
Rise/Fall Matching
Determined as a fraction of
2*(TR – TF)/(TR + TF)
'TR
'TF
TSKEW
Any CPU to CPU Clock Skew
Measured at crossing point Vox
VHIGH
Voltage High
Math averages Figure 13
Math averages Figure 13
–150
–
mv
250
550
mv
–
VHIGH +
0.3
V
ODSSAbs
TPERIODSSAbs
TPERIODSSAbs
TPERI-
%
–
95
ps
175
700
ps
–
20
%
Rise Time Variation
–
250
ps
Fall Time Variation
–
250
ps
–
100
ps
660
850
mv
VLOW
Voltage Low
VOX
Crossing Point Voltage at 0.7V Swing
VOVS
Maximum Overshoot Voltage
VUDS
Minimum Undershoot Voltage
–0.3
–
V
VRB
Ring Back Voltage
See Figure 13. Measure SE
–
0.2
V
TDC
SRCT and SRCC Duty Cycle
Measured at crossing point VOX
45
55
%
TPERIOD
100-MHz SRCT and SRCC Period
Measured at crossing point VOX
SRC
Rev 1.0, November 22, 2006
9.997001 10.00300
ns
Page 14 of 18
CY28RS400
AC Electrical Specifications (continued)
Parameter
Description
Condition
Min.
Max.
Unit
TPERIODSS
100-MHz SRCT and SRCC Period, SSC
Measured at crossing point VOX
9.997001 10.05327
ns
TPERIODAbs
100-MHz SRCT and SRCC Absolute Period
Measured at crossing point VOX
10.12800 9.872001
ns
TPERI-
100-MHz SRCT and SRCC Absolute Period, SSC Measured at crossing point VOX
9.872001 10.17827
ns
ODSSAbs
TSKEW
Any SRCT/C to SRCT/C Clock Skew
Measured at crossing point VOX
–
250
ps
TSKEW
Any SRCS clock to Any SRCS clock Skew
Measured at crossing point Vox
-
250
ps
TCCJ
SRCT/C Cycle to Cycle Jitter
Measured at crossing point VOX
–
125
ps
LACC
SRCT/C Long Term Accuracy
Measured at crossing point VOX
–
300
ppm
T R / TF
SRCT and SRCC Rise and Fall Times
Measured from VOL = 0.175 to
VOH = 0.525V
175
700
ps
TRFM
Rise/Fall Matching
Determined as a fraction of
2*(TR – TF)/(TR + TF)
–
20
%
'TR
Rise TimeVariation
–
125
ps
'TF
Fall Time Variation
–
125
ps
VHIGH
Voltage High
Math averages Figure 13
660
850
mv
Math averages Figure 13
–150
–
mv
250
550
mV
–
VHIGH +
0.3
V
VLOW
Voltage Low
VOX
Crossing Point Voltage at 0.7V Swing
VOVS
Maximum Overshoot Voltage
VUDS
Minimum Undershoot Voltage
–0.3
–
V
VRB
Ring Back Voltage
See Figure 13. Measure SE
–
0.2
V
TDC
PCI Duty Cycle
Measurement at 1.5V
45
55
%
TPERIOD
Spread Disabled PCI Period
Measurement at 1.5V
29.99100 30.00900
ns
TPERIODSS
Spread Enabled PCI Period, SSC
Measurement at 1.5V
29.9910 30.15980
ns
TPERIODAbs
Spread Disabled PCI Period
Measurement at 1.5V
29.49100 30.50900
ns
TPERI-
Spread Enabled PCI Period, SSC
Measurement at 1.5V
29.49100 30.65980
ns
THIGH
PCI high time
Measurement at 2.4V
12.0
–
TLOW
PCI low time
Measurement at 0.4V
12.0
–
ns
T R / TF
PCI rise and fall times
Measured between 0.8V and 2.0V
1.0
4.0
V/n
s
TCCJ
PCI Cycle to Cycle Jitter
Measurement at 1.5V
–
500
ps
TDC
Duty Cycle
Measurement at 1.5V
45
55
%
TPERIOD
Period
Measurement at 1.5V
20.83125 20.83542
ns
TPERIODAbs
Absolute Period
Measurement at 1.5V
20.48125 21.18542
ns
THIGH
USB high time
Measurement at 2.4V
8.094
10.036
ns
TLOW
USB low time
Measurement at 0.4V
7.694
9.836
ns
T R / TF
Rise and Fall Times
Measured between 0.8V and 2.0V
1.0
2.0
V/n
s
TCCJ
Cycle to Cycle Jitter
Measurement at 1.5V
–
350
ps
PCI
ODSSAbs
ns
USB
REF
TDC
REF Duty Cycle
Measurement at 1.5V
45
55
%
TPERIOD
REF Period
Measurement at 1.5V
69.8203
69.8622
ns
TPERIODAbs
REF Absolute Period
Measurement at 1.5V
68.82033 70.86224
ns
Rev 1.0, November 22, 2006
Page 15 of 18
CY28RS400
AC Electrical Specifications (continued)
Parameter
Description
Condition
T R / TF
REF Rise and Fall Times
Measured between 0.8V and 2.0V
TCCJ
REF Cycle to Cycle Jitter
Measurement at 1.5V
Min.
Max.
Unit
0.5
4.0
V/n
s
–
1000
ps
–
1.8
ms
10.0
–
ns
0
–
ns
ENABLE/DISABLE and SET-UP
TSTABLE
Clock Stabilization from Power-up
TSS
Stopclock Set-up Time
TSH
Stopclock Hold Time
Test and Measurement Set-up
For PCI Single-ended Signals and Reference
The following diagram shows the test load configurations for
the single-ended PCI, USB, and REF output signals.
:
PCI/
USB
Measurement
Point
:
5pF
:
Measurement
Point
:
5pF
:
Measurement
Point
:
5pF
:
:
:
:
Measurement
Point
REF
5pF
Measurement
Point
5pF
Figure 12. Single-ended Load Configuration
For Differential CPU and SRC Output Signals
The following diagram shows the test load configuration for the
differential CPU and SRC outputs.
CPUT
SRCT
CPUC
SRCC
IR E F
:
:
:
:
M e a s u re m e n t
P o in t
2pF
:
:
M e a s u re m e n t
P o in t
2pF
:
Figure 13. 0.7V Load Configuration
Rev 1.0, November 22, 2006
Page 16 of 18
CY28RS400
3 .3 V s ig n a l s
T DC
-
-
3 .3 V
2 .4 V
1 .5 V
0 .4 V
0V
TF
TR
Figure 14. Single-ended Output Signals (for AC Parameters Measurement)
Ordering Information
Part Number
Package Type
Product Flow
Standard
CY28RS400OC
56-pin SSOP
Commercial, 0q to 70qC
CY28RS400OCT
56-pin SSOP – Tape and Reel
Commercial, 0q to 70qC
CY28RS400ZC
56-pin TSSOP
Commercial, 0q to 70qC
CY28RS400ZCT
56-pin TSSOP – Tape and Reel
Commercial, 0q to 70qC
56-pin SSOP
Commercial, 0q to 70qC
Lead-free
CY28RS400OXC
CY28RS400OXCT
56-pin SSOP – Tape and Reel
Commercial, 0q to 70qC
CY28RS400ZXC
56-pin TSSOP
Commercial, 0q to 70qC
CY28RS400ZXCT
56-pin TSSOP – Tape and Reel
Commercial, 0q to 70qC
Package Diagrams
56-Lead Shrunk Small Outline Package O56
.020
1
28
0.395
0.420
0.292
0.299
DIMENSIONS IN INCHES MIN.
MAX.
29
56
0.720
0.730
SEATING PLANE
0.088
0.092
0.095
0.110
0.005
0.010
.010
GAUGE PLANE
0.110
0.025
BSC
Rev 1.0, November 22, 2006
0.008
0.0135
0.008
0.016
0°-8°
0.024
0.040
51 85062 *C
Page 17 of 18
CY28RS400
Package Diagrams (continued)
56-Lead Thin Shrunk Small Outline Package, Type II (6 mm x 12 mm) Z56
0.249[0.009]
28
1
DIMENSIONS IN MM[INCHES] MIN.
MAX.
REFERENCE JEDEC MO-153
7.950[0.313]
8.255[0.325]
PACKAGE WEIGHT 0.42gms
5.994[0.236]
6.198[0.244]
PART #
Z5624 STANDARD PKG.
ZZ5624 LEAD FREE PKG.
29
56
13.894[0.547]
14.097[0.555]
1.100[0.043]
MAX.
GAUGE PLANE
0.25[0.010]
0.20[0.008]
0.851[0.033]
0.950[0.037]
0.500[0.020]
BSC
0.170[0.006]
0.279[0.011]
0.051[0.002]
0.152[0.006]
0°-8°
0.508[0.020]
0.762[0.030]
0.100[0.003]
0.200[0.008]
SEATING
PLANE
51-85060-*C
While SLI has reviewed all information herein for accuracy and reliability, Spectra Linear Inc. assumes no responsibility for the use of any circuitry or for the infringement of any patents or other rights of third parties which would result from each use. This product is intended for use in
normal commercial applications and is not warranted nor is it intended for use in life support, critical medical instruments, or any other application requiring extended temperature range, high reliability, or any other extraordinary environmental requirements unless pursuant to additional
processing by Spectra Linear Inc., and expressed written agreement by Spectra Linear Inc. Spectra Linear Inc. reserves the right to change any
circuitry or specification without notice.
Rev 1.0, November 22, 2006
Page 18 of 18