MAXIM MAX9389ETJ

19-2688; Rev 0; 1/03
Differential 8:1 ECL/PECL Multiplexer with
Dual Output Buffers
Features
♦ 310ps Propagation Delay
Three single-ended select inputs, SEL0, SEL1, and SEL2,
control the mux function. The mux select inputs are compatible with ECL/PECL logic, and are internally referenced to the on-chip reference output (VBB1, VBB2),
nominally VCC - 1.425V. The select inputs accept signals
between VCC and VEE. Internal pulldowns to VEE ensure
a low default condition if the select inputs are left open.
♦ -2.375V to -5.5V Supplies for Differential
LVECL/ECL
The differential inputs D_, D_ can be configured to
accept a single-ended signal when the unused complementary input is connected to the on-chip reference
output (V BB1, V BB2). All the differential inputs have
internal bias and clamping circuits that ensure a low
output state when the inputs are left open.
The MAX9389 operates with a wide supply range VCC VEE of 2.375V to 5.5V. The device is offered in 32-pin
TQFP and thin QFN packages, and operates over the
-40°C to +85°C extended temperature range.
♦ Guaranteed 2.7GHz Operating Frequency
♦ 0.3psRMS Random Jitter
♦ <30ps Output-to-Output Skew
♦ +2.375V to +5.5V Supplies for Differential
LVPECL/PECL
♦ Outputs Low for Open Inputs
♦ Dual Output Buffers
♦ >2kV ESD Protection (Human Body Model)
Ordering Information
PART
TEMP RANGE
PIN-PACKAGE
MAX9389EHJ
-40°C to +85°C
32 TQFP
MAX9389ETJ*
-40°C to +85°C
32 Thin QFN
*Future product—contact factory for availability.
Applications
Functional Diagram
High-Speed Telecom and Datacom Applications
Central-Office Backplane Clock Distribution
D0
DSLAM/DLC
D0
MAX9389
D1
Pin Configurations
VEE
Q0
Q0
VCC
Q1
Q1
VCC
SEL2
TOP VIEW
32
31
30
29
28
27
26
25
D1
D2
VCC
D2
VEE
D3
Q0
D3
VCC
1
24 SEL1
VBB2
2
23 SEL0
VBB1
3
MUX
8:1
D4
Q0
D4
Q1
D5
Q1
22 VCC
D5
D0
D0
21 D7
4
MAX9389
5
20 D7
VBB1
D6
VBB2
D6
D1
6
19 D6
D7
D1
7
18 D6
D7
VCC
8
17 VEE
VCC
10
11
12
13
14
15
16
D2
D2
D3
D3
D4
D4
D5
D5
SEL0
9
232kΩ
180kΩ
SEL1
D_
D_
SEL2
165kΩ
TQFP
VEE
180kΩ
180kΩ
VEE
Pin Configurations continued at end of data sheet.
________________________________________________________________ Maxim Integrated Products
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
1
MAX9389
General Description
The MAX9389 is a fully differential, high-speed, low-jitter,
8-to-1 ECL/PECL multiplexer (mux) with dual output
buffers. The device is designed for clock and data distribution applications, and features extremely low propagation delay (310ps typ) and output-to-output skew
(30ps max).
MAX9389
Differential 8:1 ECL/PECL Multiplexer with
Dual Output Buffers
ABSOLUTE MAXIMUM RATINGS
VCC - VEE ..............................................................-0.3V to +6.0V
Inputs (D_, D_, SEL_) to VEE ......................-0.3V to (VCC + 0.3V)
D_ to D_...............................................................................±3.0V
Continuous Output Current .................................................50mA
Surge Output Current........................................................100mA
VBB_ Sink/Source Current ..............................................±600µA
Continuous Power Dissipation (TA = +70°C)
32-Lead TQFP (derate 13.1mW/°C above +70°C) ...1047mW
θJA in Still Air..........................................................+76°C/W
θJC .........................................................................+25°C/W
32-Lead QFN (derate 21.3mW/°C above +70°C) .....1702mW
θJA in Still Air..........................................................+47°C/W
θJC ...........................................................................+2°C/W
Operating Temperature Range ...........................-40°C to +85°C
Junction Temperature ......................................................+150°C
Storage Temperature Range .............................-65°C to +150°C
ESD Protection
Human Body Model (D_, D_, Q_, Q_, SEL_, VBB_) .............≥2kV
Soldering Temperature (10s) ...........................................+300°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
(VCC - VEE = 2.375V to 5.5V, outputs loaded with 50Ω ±1% to VCC - 2V. Typical values are at VCC - VEE = 3.3V, VIHD = VCC - 1V,
VILD = VCC - 1.5V, unless otherwise noted.) (Notes 1–4)
PARAMETER
SYMBOL
CONDITIONS
-40°C
MIN
TYP
+25°C
MAX
MIN
TYP
+85°C
MAX
MIN
TYP
MAX
UNITS
INPUT (D_, D_, SEL_)
Single-Ended
Input High
Voltage
VIH
VBB_ connected to the
unused input, Figure 1
VCC 1.225
VCC 0.880
VCC 1.225
VCC 0.880
VCC 1.225
VCC 0.880
V
Single-Ended
Input Low
Voltage
VIL
VBB_ connected to the
unused input, Figure 1
VCC 1.945
VCC 1.625
VCC 1.945
VCC 1.625
VCC 1.945
VCC 1.625
V
Differential Input
High Voltage
VIHD
Figure 1
VEE +
1.2
VCC
VEE +
1.2
VCC
VEE +
1.2
VCC
V
Differential Input
Low Voltage
VILD
Figure 1
VEE
VCC 0.095
VEE
VCC 0.095
VEE
VCC 0.095
V
VCC VEE
0.095
VCC VEE
0.095
VIHD VILD
VCC - VEE <
3.0V
0.095
Differential Input
Voltage
VCC VEE
VCC - VEE ≥
3.0V
0.095
3.000
0.095
3.000
0.095
3.000
-60
+60
-60
+60
-60
+60
µA
VCC 1.145
VCC 0.895
VCC 1.145
VCC 0.895
VCC 1.145
VCC 0.895
V
Input Current
IIN
Figure 1
VIH, VIL, VIHD, VILD
V
OUTPUT (Q_, Q_)
Single-Ended
Output High
Voltage
2
VOH
Figure 2
_______________________________________________________________________________________
Differential 8:1 ECL/PECL Multiplexer with
Dual Output Buffers
(VCC - VEE = 2.375V to 5.5V, outputs loaded with 50Ω ±1% to VCC - 2V. Typical values are at VCC - VEE = 3.3V, VIHD = VCC - 1V,
VILD = VCC - 1.5V, unless otherwise noted.) (Notes 1–4)
+25°C
SYMBOL
Single-Ended
Output Low
Voltage
VOL
Figure 2
VCC 1.945
VOH VOL
Figure 2
650
830
VCC 1.525
VCC 1.425
VCC 1.325
50
70
Differential
Output Voltage
CONDITIONS
-40°C
PARAMETER
MIN
TYP
MAX
MIN
VCC 1.695
VCC 1.945
TYP
+85°C
MAX
MIN
VCC 1.695
VCC 1.945
650
840
VCC 1.525
VCC 1.425
VCC 1.325
53
70
TYP
MAX
VCC 1.695
UNITS
V
650
840
mV
VCC 1.525
VCC 1.425
VCC 1.325
V
55
70
mA
REFERENCE OUTPUT (VBB_ )
Reference
Voltage Output
VBB1
VBB2
IBB1 + IBB2 = ±0.5mA
(Note 5)
POWER SUPPLY
Supply Current
IEE
(Note 6)
AC ELECTRICAL CHARACTERISTICS
(VCC - VEE = 2.375V to 5.5V, outputs loaded with 50Ω ±1% to VCC - 2V, VIHD - VILD = 0.15V to 1V, fIN ≤ 2.5GHz, input duty cycle = 50%,
input transition time = 125ps (20% to 80%). Typical values are at VCC - VEE = 3.3V, VIHD = VCC - 1V, VILD = VCC - 1.5V, fIN = 622 MHz,
input duty cycle = 50%, input transition time = 125ps (20% to 80%.)) (Note 7)
PARAMETER
SYMBOL
CONDITIONS
-40°C
+25°C
+85°C
UNITS
MIN
TYP
MAX
MIN
TYP
MAX
MIN
TYP
MAX
216
301
370
237
310
416
255
329
456
ps
1.34
2
1.25
2
1.44
2
ns
Differential Inputto-Output Delay
tPLHD,
tPHLD
Figure 2
SEL_-to-Output
Delay
tPLH2,
tPHL2
Figure 4, input
transition time = 500ps
(20% to 80%) (Note 8)
Output-to-Output
Skew
tSKOO
Figure 5 (Note 9)
15
15
30
ps
Input-to-Output
Skew
tSKIO
Figure 6 (Note 10)
50
50
55
ps
Part-to-Part
Skew
tSKPP
(Note 11)
125
150
160
ps
Added Random
Jitter (Note 12)
Added
Deterministic
Jitter (Note 12)
tRJ
TDJ
fIN = 156MHz
Clock
fIN = 622MHz
pattern
fIN = 2.5GHz
PRBS
223 - 1
0.3
1.15
0.3
1.15
0.3
1.15
0.3
1.15
0.3
1.15
0.3
1.15
0.3
1.15
0.3
1.15
0.3
1.15
fIN = 156Mbps
33
95
33
95
33
95
fIN = 622Mbps
21
61
21
61
21
61
psRMS
psP-P
_______________________________________________________________________________________
3
MAX9389
DC ELECTRICAL CHARACTERISTICS (continued)
Differential 8:1 ECL/PECL Multiplexer with
Dual Output Buffers
MAX9389
AC ELECTRICAL CHARACTERISTICS (continued)
(VCC - VEE = 2.375V to 5.5V, outputs loaded with 50Ω ±1% to VCC - 2V, VIHD - VILD = 0.15V to 1V, fIN ≤ 2.5GHz, input duty cycle = 50%,
input transition time = 125ps (20% to 80%). Typical values are at VCC - VEE = 3.3V, VIHD = VCC - 1V, VILD = VCC - 1.5V, fIN = 622 MHz,
input duty cycle = 50%, input transition time = 125ps (20% to 80%.)) (Note 7)
PARAMETER
SYMBOL
-40°C
CONDITIONS
MIN
TYP
+25°C
MAX
MIN
TYP
+85°C
MAX
MIN
TYP
MAX
UNITS
Switching
Frequency
fMAX
VOH - VOL ≥ 300mV,
Figure 2
2.7
2.7
2.7
GHz
Select Toggle
Frequency
fSEL
VOH - VOL ≥ 300mV,
Figure 4
100
100
100
MHz
Output Rise and
Fall Time
(20% to 80%)
tR, tF
Figure 2
67
105
138
74
117
155
81
128
165
ps
Note 1: Measurements are made with the device in thermal equilibrium.
Note 2: Current into an I/O pin is defined as positive. Current out of an I/O pin is defined as negative.
Note 3: DC parameters production tested at TA = +25°C and guaranteed by design over the full operating temperature range.
Note 4: Single-ended data input operation using VBB_ is limited to (VCC - VEE) ≥ 3.0V.
Note 5: Use VBB_ only for inputs that are on the same device as the VBB_ reference.
Note 6: All pins open except VCC and VEE.
Note 7: Guaranteed by design and characterization. Limits are set at ±6 sigma.
Note 8: Measured from the 50% point of the input signal with the 50% point equal to VBB, to the 50% point of the output signal.
Note 9: Measured between outputs of the same part at the signal crossing points for a same-edge transition.
Note 10: Measured between input-to-output paths of the same part at the signal crossing points for a same-edge transition of the
differential input signal.
Note 11: Measured between outputs of different parts at the signal crossing points under identical conditions for a same-edge
transition.
Note 12: Device jitter added to the differential input signal.
Typical Operating Characteristics
(VCC - VEE = 3.3V, VIHD = VCC - 1V, VILD = VCC - 1.5V, outputs loaded with 50Ω ±1% to VCC - 2V, fIN = 622MHz, input duty cycle = 50%,
input transition time = 125ps (20% to 80%), unless otherwise noted.)
55.0
52.5
50.0
47.5
45.0
42.5
-40
-15
10
35
TEMPERATURE (°C)
4
700
600
500
400
60
85
MAX9389 toc03
MAX9389 toc02
800
140
130
120
FALL
110
RISE
100
300
90
200
40.0
150
RISE/FALL TIME (ps)
SUPPLY CURRENT (mA)
57.5
900
DIFFERENTIAL OUTPUT VOLTAGE (mV)
ALL PINS ARE OPEN EXCEPT VCC AND VEE
MAX9389 toc01
60.0
OUTPUT RISE/FALL TIME
vs. TEMPERATURE
DIFFERENTIAL OUTPUT VOLTAGE (VOH - VOL)
vs. FREQUENCY
SUPPLY CURRENT vs. TEMPERATURE
0
0.5
1.0
1.5
2.0
FREQUENCY (GHz)
2.5
3.0
-40
-15
10
35
TEMPERATURE (°C)
_______________________________________________________________________________________
60
85
Differential 8:1 ECL/PECL Multiplexer with
Dual Output Buffers
PROPAGATION DELAY vs. HIGH VOLTAGE
OF DIFFERENTIAL INPUT (VIHD)
308
292
276
330
MAX9389 toc05
324
PROPAGATION DELAY vs. TEMPERATURE
350
MAX9389 toc04
VIHD - VILD = 150mV
PROPAGATION DELAY (ps)
PROPAGATION DELAY (ps)
340
tPHL
310
tPLH
290
270
260
250
1.2
1.5
1.8
2.1
2.4
2.7
VIHD (V)
3.0
3.3
-40
-15
10
35
60
85
TEMPERATURE (°C)
Pin Description
PIN
NAME
FUNCTION
1, 8, 22,
26, 29
VCC
Positive Supply Input. Bypass each VCC to VEE with 0.1µF and 0.01µF ceramic capacitors. Place the
capacitors as close to the device as possible with the smaller value capacitor closest to the device.
2
VBB2
Reference Output Voltage 2. Connect to the inverting or noninverting data input to provide a
reference for single-ended operation. When used, bypass VBB2 to VCC with a 0.01µF ceramic
capacitor. Otherwise leave open.
3
VBB1
Reference Output Voltage 1. Connect to the inverting or noninverting data input to provide a
reference for single-ended operation. When used, bypass VBB1 to VCC with a 0.01µF ceramic
capacitor. Otherwise leave open.
4
D0
Noninverting Differential Input 0. Internal 232kΩ to VCC and 180kΩ to VEE.
5
D0
Inverting Differential Input 0. Internal 180kΩ to VCC and 180kΩ to VEE.
6
D1
Noninverting Differential Input 1. Internal 232kΩ to VCC and 180kΩ to VEE.
7
D1
Inverting Differential Input 1. Internal 180kΩ to VCC and 180kΩ to VEE.
Noninverting Differential Input 2. Internal 232kΩ to VCC and 180kΩ to VEE.
9
D2
10
D2
Inverting Differential Input 2. Internal 180kΩ to VCC and 180kΩ to VEE.
11
D3
Noninverting Differential Input 3. Internal 232kΩ to VCC and 180kΩ to VEE.
12
D3
Inverting Differential Input 3. Internal 180kΩ to VCC and 180kΩ to VEE.
13
D4
Noninverting Differential Input 4. Internal 232kΩ to VCC and 180kΩ to VEE.
14
D4
Inverting Differential Input 4. Internal 180kΩ to VCC and 180kΩ to VEE.
15
D5
Noninverting Differential Input 5. Internal 232kΩ to VCC and 180kΩ to VEE.
16
D5
Inverting Differential Input 5. Internal 180kΩ to VCC and 180kΩ to VEE.
17, 32
VEE
Negative Supply Input
18
D6
Noninverting Differential Input 6. Internal 232kΩ to VCC and 180kΩ to VEE.
19
D6
Inverting Differential Input 6. Internal 180kΩ to VCC and 180kΩ to VEE.
_______________________________________________________________________________________
5
MAX9389
Typical Operating Characteristics (continued)
(VCC - VEE = 3.3V, VIHD = VCC - 1V, VILD = VCC - 1.5V, outputs loaded with 50Ω ±1% to VCC - 2V, fIN = 622MHz, input duty cycle = 50%,
input transition time = 125ps (20% to 80%), unless otherwise noted.)
Differential 8:1 ECL/PECL Multiplexer with
Dual Output Buffers
MAX9389
Pin Description (continued)
PIN
NAME
20
D7
Noninverting Differential Input 7. Internal 232kΩ to VCC and 180kΩ to VEE.
FUNCTION
21
D7
Inverting Differential Input 7. Internal 180kΩ to VCC and 180kΩ to VEE.
23
SEL0
Select Logic Input 0. Internal 165kΩ pulldown to VEE.
24
SEL1
Select Logic Input 1. Internal 165kΩ pulldown to VEE.
25
SEL2
27
Q1
Inverting Output 1. Typically terminate with 50Ω resistor to VCC - 2V.
28
Q1
Noninverting Output 1. Typically terminate with 50Ω resistor to VCC - 2V.
Select Logic Input 2. Internal 165kΩ pulldown to VEE.
30
Q0
Inverting Output 0. Typically terminate with 50Ω resistor to VCC - 2V.
31
Q0
Noninverting Output 0. Typically terminate with 50Ω resistor to VCC - 2V.
—
EP
Exposed Pad (QFN Package Only). Connect to VEE.
VIHD
D_
VIHD - VILD
VCC
VCC
VIHD (MAX)
tPLHD
VIHD - VILD
VILD (MAX)
VILD
D_
VIH
Q_
VIL
Q_
tPHLD
VOH
VBB
VOH - VOL
VIHD (MIN)
VOL
VIHD - VILD
VILD (MIN)
VEE
DIFFERENTIAL INPUT VOLTAGE DEFINITION
80%
VEE
SINGLE-ENDED INPUT VOLTAGE DEFINITION
80%
VOH - VOL
DIFFERENTIAL OUTPUT
WAVEFORM
0V (DIFFERENTIAL)
VOH - VOL
20%
20%
Q_ - Q_
tR
tF
Figure 2. Differential Input-to-Output Propagation Delay Timing
Diagram
Figure 1. Input Definitions
VIHD
D_, D1
VIH
D_ WHEN D_ = VBB
VBB
VIHD - VILD
VILD
D_, D1
OR
VIH
VBB
VIL
D_ WHEN D_ = VBB
tPLH1
tPHL1
VOH
Q_
Figure 3. Single-Ended Input-to-Output Propagation Delay
Timing Diagram
6
VIL
tPLH2
tPHL2
VOH
Q_
VOH - VOL
Q_
VBB
SEL_ = VIL OR OPEN
SELO
VOH - VOL
VOL
Q_
VOL
Figure 4. Select Input (SEL0) to Output (Q_, Q_) Delay Timing
Diagram
_______________________________________________________________________________________
Differential 8:1 ECL/PECL Multiplexer with
Dual Output Buffers
MAX9389
D0
D0
Q0
Q0
Q0
Q0
tPLHD*
tPHLD*
tPLHD**
tPHLD**
D1–D7
Q1
D1–D7
Q1
Q0
tSKOO
tSKOO
Q0
tSKIO = | tPLHD* - tPLHD** | OR | tPHLD* - tPHLD** |
Figure 5. Output-to-Output Skew (tSKOO) Definition
Detailed Description
The MAX9389 is a fully differential, high-speed, low-jitter
8-to-1 ECL/PECL mux with dual output buffers. The
device is designed for clock and data distribution applications, and features extremely low propagation delay
(310ps typ) and output-to-output skew (30ps max).
Three single-ended select inputs, SEL0, SEL1, and
SEL2, control the mux function (see Table 1). The mux
select inputs are compatible with ECL/PECL logic, and
are internally referenced to the on-chip reference output
(VBB1, VBB2), nominally VCC - 1.425V. The select inputs
accept signals between VCC and VEE. Internal 165kΩ
pulldowns to VEE ensure a low default condition if the
select inputs are left open. Leaving SEL0, SEL1, and
SEL2 open selects the D0, D0 inputs by default.
The differential inputs D_, D_ can be configured to
accept a single-ended signal when the unused complementary input is connected to the on-chip reference
voltage (VBB1, VBB2). Voltage reference outputs VBB1
and VBB2 provide the reference voltage needed for single-ended operations. A single-ended input of at least
VBB_ ±100mV or a differential input of at least 100mV
switches the outputs to the VOH and VOL levels specified in the DC Electrical Characteristics table. The maximum magnitude of the differential input from D_ to D_ is
±3.0V. This limit also applies to the difference between a
single-ended input and any reference voltage input.
Figure 6. Input-to-Output Skew (tSKIO) Definition
Table 1. Mux Select Input Truth Table
DATA
OUTPUT
SEL0
SEL1
SEL2
D0*
L or open
L or open
L or open
D1
H
L or open
L or open
D2
L or open
H
L or open
D3
H
H
L or open
D4
L or open
L or open
H
D5
H
L or open
H
D6
L or open
H
H
D7
H
H
H
*Default output when SEL0, SEL1, and SEL2 are left open.
Single-Ended Operation
The recommended supply voltage for single-ended
operation is 3.0V to 3.8V. The differential inputs (D_,
D_) can be configured to accept single-ended inputs
when operating at supply voltages greater than 2.725V.
In single-ended mode operation, the unused complementary input needs to be connected to the on-chip
reference voltage, VBB1 or VBB2, as a reference. For
example, the differential D_, D_ inputs are converted to
a noninverting, single-ended input by connecting VBB1
or VBB2 to D_ and connecting the single-ended input to
D_. Similarly, an inverting input is obtained by connecting V BB1 or V BB2 to D_ and connecting the singleended input to D_. The single-ended input can be
driven to V CC or V EE or with a single-ended
LVPECL/LVECL signal.
_______________________________________________________________________________________
7
Q0
Q0
VCC
Q1
Q1
VCC
SEL2
30
29
28
27
26
25
TOP VIEW
VEE
Output Termination
Terminate each output with a 50Ω to VCC - 2V or use an
equivalent Thevenin termination. Terminate each Q_
and Q_ output with identical termination for minimal distortion. When a single-ended signal is taken from the
differential output, terminate both Q_ and Q_.
Pin Configurations (continued)
31
Applications Information
Traces
Circuit board trace layout is very important to maintain the
signal integrity of high-speed differential signals.
Maintaining integrity is accomplished in part by reducing
signal reflections and skew, and increasing commonmode noise immunity.
Signal reflections are caused by discontinuities in the
50Ω characteristic impedance of the traces. Avoid
discontinuities by maintaining the distance between
differential traces, not using sharp corners or using
vias. Maintaining distance between the traces also
increases common-mode noise immunity. Reducing
signal skew is accomplished by matching the electrical
length of the differential traces.
32
In single-ended operation, ensure that the supply voltage (VCC -VEE) is greater than 2.725V. The input high
minimum level must be at least (VEE + 1.2V) or higher
for proper operation. The reference voltage VBB must
be at least (VEE + 1.2V) because it becomes the highlevel input when a single-ended input swings below it.
The minimum VBB output for the MAX9389 is (VCC 1.525V). Substituting the minimum VBB output for (VBB
= VEE + 1.2V) results in a minimum supply (VCC - VEE)
of 2.725V. Rounding up to standard supplies gives the
recommended single-ended operating supply ranges
(VCC - VEE) of 3.0V to 5.5V.
When using the VBB reference output, bypass it with a
0.01µF ceramic capacitor to VCC. If VBB is not being
used, leave it unconnected. The VBB reference can
source or sink a total of 0.5mA (shared between VBB1
and VBB2), which is sufficient to drive eight inputs.
VCC
1
24
SEL1
VBB2
2
23
SEL0
Ensure that the output current does not exceed the current limits specified in the Absolute Maximum Ratings
table. Under all operating conditions, the device’s total
thermal limits should not be exceeded.
VBB1
3
22
VCC
D0
4
21
D7
D0
5
20
D7
D1
6
19
D6
Supply Bypassing
D1
7
18
D6
Bypass each VCC to VEE with high-frequency surfacemount ceramic 0.1µF and 0.01µF capacitors. For PECL,
bypass each VCC to VEE. For ECL, bypass each VEE to
VCC. Place the capacitors as close to the device as possible with the 0.01µF capacitor closest to the device pins.
Use multiple vias when connecting the bypass capacitors
to ground. When using the VBB1 or VBB2 reference outputs, bypass each one with a 0.01µF ceramic capacitor
to VCC. If the VBB1 or VBB2 reference outputs are not
used, they can be left open.
VCC
8
17
VEE
14
15
16
D4
D5
D5
12
D3
13
11
D3
D4
9
10
D2
MAX9389
D2
MAX9389
Differential 8:1 ECL/PECL Multiplexer with
Dual Output Buffers
THIN QFN
NOTE: VEE IS CONNECTED
TO THE UNDERSIDE
METAL SLUG.
Chip Information
TRANSISTOR COUNT: 716
PROCESS: Bipolar
8
_______________________________________________________________________________________
Differential 8:1 ECL/PECL Multiplexer with
Dual Output Buffers
32L TQFP, 5x5x01.0.EPS
_______________________________________________________________________________________
9
MAX9389
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)
D2
0.15 C A
D
b
CL
0.10 M C A B
D2/2
D/2
PIN # 1
I.D.
QFN THIN.EPS
MAX9389
Differential 8:1 ECL/PECL Multiplexer with
Dual Output Buffers
k
0.15 C B
PIN # 1 I.D.
0.35x45
E/2
E2/2
CL
(NE-1) X e
E
E2
k
L
DETAIL A
e
(ND-1) X e
CL
CL
L
L
e
e
0.10 C
A
C
0.08 C
A1 A3
PROPRIETARY INFORMATION
TITLE:
PACKAGE OUTLINE
16, 20, 28, 32L, QFN THIN, 5x5x0.8 mm
APPROVAL
COMMON DIMENSIONS
DOCUMENT CONTROL NO.
REV.
21-0140
C
1
2
EXPOSED PAD VARIATIONS
NOTES:
1. DIMENSIONING & TOLERANCING CONFORM TO ASME Y14.5M-1994.
2. ALL DIMENSIONS ARE IN MILLIMETERS. ANGLES ARE IN DEGREES.
3. N IS THE TOTAL NUMBER OF TERMINALS.
4. THE TERMINAL #1 IDENTIFIER AND TERMINAL NUMBERING CONVENTION SHALL CONFORM TO JESD 95-1
SPP-012. DETAILS OF TERMINAL #1 IDENTIFIER ARE OPTIONAL, BUT MUST BE LOCATED WITHIN THE
ZONE INDICATED. THE TERMINAL #1 IDENTIFIER MAY BE EITHER A MOLD OR MARKED FEATURE.
5. DIMENSION b APPLIES TO METALLIZED TERMINAL AND IS MEASURED BETWEEN 0.25 mm AND 0.30 mm
FROM TERMINAL TIP.
6. ND AND NE REFER TO THE NUMBER OF TERMINALS ON EACH D AND E SIDE RESPECTIVELY.
7. DEPOPULATION IS POSSIBLE IN A SYMMETRICAL FASHION.
8. COPLANARITY APPLIES TO THE EXPOSED HEAT SINK SLUG AS WELL AS THE TERMINALS.
9. DRAWING CONFORMS TO JEDEC MO220.
10. WARPAGE SHALL NOT EXCEED 0.10 mm.
PROPRIETARY INFORMATION
TITLE:
PACKAGE OUTLINE
16, 20, 28, 32L, QFN THIN, 5x5x0.8 mm
APPROVAL
DOCUMENT CONTROL NO.
REV.
21-0140
C
2
2
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
10 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2003 Maxim Integrated Products
Printed USA
is a registered trademark of Maxim Integrated Products.
This datasheet has been download from:
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