19-2220; Rev 1; 11/04 KIT ATION EVALU LE B A IL A AV 1:5 Differential LVPECL/LVECL/HSTL Clock and Data Driver The MAX9315 low-skew, 1-to-5 differential driver is designed for clock and data distribution. This device allows selection between two inputs. The selected input is reproduced at five differential outputs. The differential inputs can be adapted to accept a single-ended input by connecting the on-chip VBB supply to one input as a reference voltage. The MAX9315 features low output-to-output skew (20ps), making it ideal for clock and data distribution across a backplane or a board. For interfacing to differential HSTL and LVPECL signals, this device operates over a +2.375V to +3.8V supply range, allowing highperformance clock or data distribution in systems with a nominal +2.5V or +3.3V supply. For differential LVECL operation, this device operates with a -2.375V to -3.8V supply. The MAX9315 is offered in a space-saving 20-pin TSSOP package. Features ♦ +2.375V to +3.8V Supply for Differential HSTL/LVPECL Operation ♦ -2.375V to -3.8V Supply for Differential LVECL Operation ♦ Two Selectable Differential Inputs ♦ Synchronous Output Enable/Disable ♦ 20ps Output-to-Output Skew ♦ 360ps Propagation Delay ♦ Guaranteed 400mV Differential Output at 1.5GHz ♦ On-Chip Reference for Single-Ended Inputs ♦ Input Biased Low when Left Open ♦ Pin Compatible with MC100LVEP14 Applications Precision Clock Distribution Ordering Information PART Low-Jitter Data Repeater MAX9315EUP TEMP RANGE PIN-PACKAGE -40°C to +85°C 20 TSSOP Data and Clock Driver and Buffer Central Office Backplane Clock Distribution DSLAM Backplane Pin Configuration Base Station ATE Typical Application Circuit MAX9315 TOP VIEW 20 VCC QO 1 Q0 2 RECEIVER MAX9315 ZO = 50Ω Q_ ZO = 50Ω Q_ 50Ω 50Ω VTT = VCC - 2.0V Q D 19 EN Q1 3 18 VCC Q1 4 17 CLK1 Q2 5 16 CLK1 Q2 6 15 VBB Q3 7 14 CLK0 Q3 8 13 CLK0 Q4 9 12 SEL Q4 10 11 VEE TSSOP Functional Diagram appears at end of data sheet. ________________________________________________________________ Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. 1 MAX9315 General Description MAX9315 1:5 Differential LVPECL/LVECL/HSTL Clock and Data Driver ABSOLUTE MAXIMUM RATINGS VCC - VEE...............................................................................4.1V Inputs (CLK_, CLK_, SEL, EN) to VEE ...........................................(VEE - 0.3V) to (VCC + 0.3V) CLK_ to CLK_ ....................................................................±3.0V Continuous Output Current .................................................50mA Surge Output Current........................................................100mA VBB Sink/Source Current ...............................................±0.65mA Continuous Power Dissipation (TA = +70°C) Single-Layer PC Board 20-Pin TSSOP (derate 7.69mW/°C above +70°C) .......615mW Multilayer PC Board 20-Pin TSSOP (derate 10.9mW/°C above +70°C) .......879mW Junction-to-Ambient Thermal Resistance in Still Air Single-Layer PC Board 20-Pin TSSOP .........................................................+130°C/W Multilayer PC Board 20-Pin TSSOP ...........................................................+91°C/W Junction-to-Ambient Thermal Resistance with 500LFPM Airflow Single-Layer PC Board 20-Pin TSSOP ..........................................................+9.6°C/W Junction-to-Case Thermal Resistance 20-Pin TSSOP ............................................................+20°C/W Operating Temperature Range ...........................-40°C to +85°C Junction Temperature ......................................................+150°C Storage Temperature Range .............................-65°C to +150°C ESD Protection Human Body Model (Inputs and Outputs) .......................≥2kV Soldering Temperature (10s) ...........................................+300°C Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. DC ELECTRICAL CHARACTERISTICS (VCC - VEE = 2.375V to 3.8V, outputs loaded with 50Ω ±1% to VCC - 2V, SEL = high or low, EN = low, unless otherwise noted. Typical values are at VCC - VEE = +3.3V, VIHD = VCC - 1V, VILD = VCC - 1.5V.) (Notes 1, 2, 3) PARAMETER SYMBOL CONDITIONS -40°C MIN TYP +25°C MAX MIN TYP +85°C MAX MIN TYP MAX UNITS SINGLE-ENDED INPUTS (SEL, EN) Input High Voltage VIH VCC 1.225 VCC VCC 1.225 VCC VCC 1.225 VCC V Input Low Voltage VIL VEE VCC 1.625 VEE VCC 1.625 VEE VCC 1.625 V Input Current IIN -500 500 -500 500 -500 500 µA VIH(MAX), VIL(MIN) DIFFERENTIAL INPUTS (CLK_, CLK_) 2 Single-Ended Input High Voltage (Note 4) VIH VBB connected to CLK_, Figure 1 VCC 1.225 VCC VCC 1.225 VCC VCC 1.225 VCC V Single-Ended Input Low Voltage (Note 4) VIL VBB connected to CLK_, Figure 1 VEE VCC 1.625 VEE VCC 1.625 VEE VCC 1.625 V High Voltage of Differential Input VIHD VEE + 1.2 VCC VEE + 1.2 VCC VEE + 1.2 VCC V Low Voltage of Differential Input VILD VEE VCC 0.1 VEE VCC 0.1 VEE VCC 0.1 V _______________________________________________________________________________________ 1:5 Differential LVPECL/LVECL/HSTL Clock and Data Driver (VCC - VEE = 2.375V to 3.8V, outputs loaded with 50Ω ±1% to VCC - 2V, SEL = high or low, EN = low, unless otherwise noted. Typical values are at VCC - VEE = +3.3V, VIHD = VCC - 1V, VILD = VCC - 1.5V.) (Notes 1, 2, 3) PARAMETER SYMBOL Differential Input Voltage VIHD VILD Input Current IIN CONDITIONS -40°C MIN TYP +25°C MAX MIN TYP +85°C MAX MIN TYP MAX UNITS For (VCC - VEE) < +3.0V 0.1 VCC VEE 0.1 VCC VEE 0.1 VCC VEE For (VCC - VEE) ≥ +3.0V 0.1 3.0 0.1 3.0 0.1 3.0 VIH, VIL, VIHD, VILD -150 150 -150 150 -150 150 µA V OUTPUTS (Q_, Q_) Single-Ended Output High Voltage VOH Figure 1 VCC 1.145 VCC - VCC 0.865 1.145 VCC - VCC 0.865 1.145 VCC 0.865 V Single-Ended Output Low Voltage VOL Figure 1 VCC 1.945 VCC - VCC 1.695 1.945 VCC - VCC 1.695 1.945 VCC 1.695 V VOH VOL Figure 1 550 910 mV VCC 1.325 V 65 mA Differential Output Voltage 910 550 910 550 REFERENCE Reference Voltage Output (Note 5) VBB IBB = ±0.5mA VCC 1.525 VCC - VCC 1.325 1.525 VCC - VCC 1.325 1.525 SUPPLY Supply Current (Note 6) IEE 41 48 45 55 49 _______________________________________________________________________________________ 3 MAX9315 DC ELECTRICAL CHARACTERISTICS (continued) MAX9315 1:5 Differential LVPECL/LVECL/HSTL Clock and Data Driver AC ELECTRICAL CHARACTERISTICS (VCC - VEE = 2.375V to 3.8V, outputs loaded with 50Ω ±1% to VCC - 2V, input frequency = 1.5GHz, input transition time = 125ps (20% to 80%), SEL = high or low, EN = low, VIHD = VEE + 1.2V to VCC, VILD = VEE to VCC - 0.15V, VIHD - VILD = 0.15V to the smaller of 3V or VCC - VEE, unless otherwise noted. Typical values are at VCC - VEE = +3.3V, VIHD = VCC - 1V, VILD = VCC - 1.5V.) (Notes 1, 7) -40°C PARAMETER SYMBOL Differential Inputto-Output Delay tPLHD, tPHLD Output-to-Output Skew (Note 8) tSKOO Part-to-Part Skew (Note 9) tSKPP CONDITIONS Figure 2 MIN TYP 290 5 +25°C MAX MIN 400 310 30 TYP 20 110 +85°C MAX MIN 440 300 40 TYP 20 130 UNITS MAX ps 520 ps 50 ps 220 ps Added Random Jitter (Note 10) tRJ fIN = 1.5GHz clock 0.8 1.2 0.8 1.2 0.8 1.2 ps (RMS) Added Deterministic Jitter (Note 10) tDJ 1.5Gbps 2E23-1 PRBS pattern 50 70 50 70 50 70 ps (p-p) Switching Frequency fMAX (VOH - VOL) ≥ 400mV, Figure 2 1.5 Output Rise/Fall Time (20% to 80%) tR, tF Figure 2 80 1.5 120 90 1.5 130 90 GHz 145 ps Note 1: Measurements are made with the device in thermal equilibrium. Note 2: Current into a pin is defined as positive. Current out of a pin is defined as negative. Note 3: DC parameters production tested at TA = +25°C and guaranteed by design over the full operating temperature range. Note 4: Single-ended input operation using VBB is limited to VCC - VEE = 3.0V to 3.8V. Note 5: Use VBB only for inputs that are on the same device as the VBB reference. Note 6: All pins open except VCC and VEE. Note 7: Guaranteed by design and characterization. Limits are set at ±6 sigma. Note 8: Measured between outputs of the same part at the signal crossing points for a same-edge transition. Note 9: Measured between outputs of different parts at the signal crossing points under identical conditions for a same-edge transition. Note 10: Device jitter added to the input signal. 4 _______________________________________________________________________________________ 1:5 Differential LVPECL/LVECL/HSTL Clock and Data Driver DIFFERENTIAL OUTPUT VOLTAGE (VOH - VOL) vs. FREQUENCY 46 45 44 43 42 41 40 TRANSITION TIME vs. TEMPERATURE MAX9315 toc02 140 800 700 130 TRANSITION TIME (ps) 47 600 500 400 300 10 35 60 tR 110 100 tF 90 100 85 80 0.5 0 TEMPERATURE (°C) 1.0 1.5 2.0 2.5 3.0 -15 -40 FREQUENCY (GHz) PROPAGATION DELAY vs. HIGH VOLTAGE OF DIFFERENTIAL INPUT (VIHD) 380 PROPAGATION DELAY (ps) 364 358 352 346 35 60 85 PROPAGATION DELAY vs. TEMPERATURE 390 MAX9315 toc04 370 10 TEMPERATURE (°C) MAX9315 toc05 -15 120 200 0 -40 PROPAGATION DELAY (ps) SUPPLY CURRENT (mA) 48 ALL PINS ARE OPEN EXCEPT VCC AND VEE 900 DIFFERENTIAL OUTPUT VOLTAGE (mV) 49 MAX9315 toc01 50 MAX9315 toc03 SUPPLY CURRENT vs. TEMPERATURE 370 360 350 340 340 330 1.2 1.5 1.8 2.1 2.4 VIHD (V) 2.7 3.0 3.3 -40 -15 10 35 60 85 TEMPERATURE (°C) _______________________________________________________________________________________ 5 MAX9315 Typical Operating Characteristics (VCC = +3.3V, VEE = 0, VIHD = VCC - 1V, VILD = VCC - 1.15V, input transition time = 125ps (20% to 80%), fIN = 2GHz, outputs loaded with 50Ω to VCC - 2V, TA = +25°C, unless otherwise noted.) 1:5 Differential LVPECL/LVECL/HSTL Clock and Data Driver MAX9315 Pin Description PIN NAME 1 Q0 Noninverting Q0 Output. Typically terminate with 50Ω resistor to VCC - 2V. FUNCTION 2 Q0 Inverting Q0 Output. Typically terminate with 50Ω resistor to VCC - 2V. 3 Q1 Noninverting Q1 Output. Typically terminate with 50Ω resistor to VCC - 2V. 4 Q1 Inverting Q1 Output. Typically terminate with 50Ω resistor to VCC - 2V. 5 Q2 Noninverting Q2 Output. Typically terminate with 50Ω resistor to VCC - 2V. 6 Q2 Inverting Q2 Output. Typically terminate with 50Ω resistor to VCC - 2V. 7 Q3 Noninverting Q3 Output. Typically terminate with 50Ω resistor to VCC - 2V. 8 Q3 Inverting Q3 Output. Typically terminate with 50Ω resistor to VCC - 2V. 9 Q4 Noninverting Q4 Output. Typically terminate with 50Ω resistor to VCC - 2V. 10 Q4 Inverting Q4 Output. Typically terminate with 50Ω resistor to VCC - 2V. 11 VEE Negative Supply Voltage 12 SEL Clock Select Input (Single Ended). Drive low to select the CLK0, CLK0 input. Drive high to select the CLK1, CLK1 input. The SEL threshold is equal to VBB. 13 CLK0 Noninverting Differential Clock Input 0. Internal 75kΩ pulldown to VEE. 14 CLK0 Inverting Differential Clock Input 0. Internal 75kΩ pullup to VCC and 75kΩ pulldown to VEE. 15 VBB 16 CLK1 Noninverting Differential Clock Input 1. Internal 75kΩ pulldown to VEE. 17 CLK1 Inverting Differential Clock Input 1. Internal 75kΩ pullup to VCC and 75kΩ pulldown to VEE. 18, 20 VCC Positive Supply Voltage. Bypass VCC to VEE with 0.1µF and 0.01µF ceramic capacitors. Place the capacitors as close to the device as possible with the smaller value capacitor closest to the device. 19 EN Output Enable Input. Outputs are synchronously enabled on the falling edge of the selected clock input when EN is low. Outputs are synchronously driven low on the falling edge of the selected clock input when EN is high. Reference Output Voltage. Connect to the inverting or noninverting clock input to provide a reference for single-ended operation. When used, bypass with a 0.01µF ceramic capacitor to VCC; otherwise, leave open. Detailed Description The MAX9315 is a low-skew, 1-to-5 differential driver designed for clock or data distribution. A 2-to-1 MUX selects one of the two differential clock inputs, CLK0, CLK0 or CLK1, CLK1. The MUX is switched by the single-ended SEL input. A logic low selects the CLK0, CLK0 input and a logic high selects the CLK1, CLK1 input. The SEL logic threshold is set by the internal voltage reference VBB. SEL can be driven to VCC and VEE or by a single-ended LVPECL/LVECL signal. The selected input is reproduced at five differential outputs. Synchronous Enable The MAX9315 is synchronously enabled and disabled with outputs in the low state to eliminate shortened clock pulses. EN is connected to the input of an edgetriggered D flip-flop. After power-up, drive EN low and 6 toggle the selected clock input to enable the outputs. The outputs are enabled on the falling edge of the selected clock input after EN goes low. The outputs are set to a low state on the falling edge of the selected clock input after EN goes high. The threshold for EN is equal to VBB. Supply For interfacing to differential HSTL and LVPECL signals, the V CC range is from +2.375V to +3.8V (with VEE grounded), allowing high-performance clock or data distribution in systems with a nominal +2.5V or +3.3V supply. For interfacing to differential LVECL, the VEE range is -2.375V to -3.8V (with VCC grounded). Output levels are referenced to V CC and are considered LVPECL or LVECL, depending on the level of the VCC supply. With VCC connected to a positive supply and _______________________________________________________________________________________ 1:5 Differential LVPECL/LVECL/HSTL Clock and Data Driver Input Bias Resistors When the inputs are open, the internal bias resistors set the inputs to low state. The inverting inputs (CLK0 and CLK1) are each biased with a 75kΩ pullup to VCC and a 75kΩ pulldown to VEE. The noninverting inputs (CLK0 and CLK1) are each biased with a 75kΩ pulldown to VEE. Differential Clock Input Limits The maximum magnitude of the differential signal applied to the clock input is 3.0V or VCC - VEE, whichever is less. This limit also applies to the difference between any reference voltage input and a single-ended input. Specifications for the high and low voltages of a differential input (VIHD and VILD) and the differential input voltage (VIHD - VILD) apply simultaneously. Single-Ended Clock Input and VBB The differential clock inputs can be configured to accept single-ended inputs. This is accomplished by connecting the on-chip reference voltage, VBB, to the inverting or noninverting input of a differential input as a reference. For example, the differential CLK0, CLK0 input is converted to a noninverting, single-ended input by connecting VBB to CLK0 and connecting the singleended input signal to CLK0. Similarly, an inverting configuration is obtained by connecting VBB to CLK0 and connecting the single-ended input to CLK0. With a differential input configured as single ended (using VBB), the single-ended input can be driven to VCC and VEE or with a single-ended LVPECL/LVECL signal. Note that single-ended input must be at least VBB ±100mV or a differential input of at least 100mV to switch the outputs to the VOH and VOL levels specified in the DC Electrical Characteristics table. If VBB is used, the supply must be in the VCC - VEE = +2.725V to +3.8V range because one of the inputs must be VEE + 1.2V or higher for proper input stage operation. VBB must be at least VEE + 1.2V because it becomes the high-level input when the other (singleended) input swings below it. Therefore, minimum VBB = V EE + 1.2V. The minimum V BB output of the MAX9315 is VCC - 1.525V. Substituting the minimum VBB output into VBB = VEE + 1.2V results in a minimum supply of +2.725V. Rounding up to standard supplies gives the single-ended operating supply range of VCC VEE = +3.0V to +3.8V. When using the VBB reference output, bypass it with a 0.01µF ceramic capacitor to VCC. If the VBB reference is not used, leave it open. The V BB reference can source or sink 0.5mA, which is sufficient to drive two inputs. Use VBB only for inputs that are on the same device as the VBB reference. Applications Information Supply Bypassing Bypass VCC to VEE with high-frequency surface-mount ceramic 0.1µF and 0.01µF capacitors in parallel as close to the device as possible, with the 0.01µF capacitor closest to the device. Use multiple parallel vias to minimize parasitic inductance. When using the VBB reference output, bypass it with a 0.01µF ceramic capacitor to VCC (if the VBB reference is not used, it can be left open). Controlled-Impedance Traces Input and output trace characteristics affect the performance of the MAX9315. Connect high-frequency input and output signals with 50Ω characteristic impedance traces. Minimize the number of vias to prevent impedance discontinuities. Reduce reflections by maintaining the 50Ω characteristic impedance through cables and connectors. Reduce skew within a differential pair by matching the electrical length of the traces. Output Termination Terminate outputs with 50Ω to V CC - 2V or use an equivalent Thevenin termination. When a single-ended signal is taken from a differential output, terminate both outputs. For example, if Q0 is used as a single-ended output, terminate both Q0 and Q0. Chip Information TRANSISTOR COUNT: 616 PROCESS: Bipolar _______________________________________________________________________________________ 7 MAX9315 VEE connected to ground, the outputs are LVPECL. The outputs are LVECL when VCC is connected to ground and VEE is connected to a negative supply. MAX9315 1:5 Differential LVPECL/LVECL/HSTL Clock and Data Driver CLK VIH CLK VBB (CLK IS CONNECTED TO VBB) VIL VOH Q_ VOH - VOL VOL Q_ Figure 1. MAX9315 Switching Characteristics with Single-Ended Input CLK VIHD VIHD - VILD CLK VILD tPLHD tPHLD Q_ VOH VOH - VOL Q_ VOL 80% 80% 0 (DIFFERENTIAL) 0 (DIFFERENTIAL) 20% 20% Q_ - Q_ tR tF Figure 2. MAX9315 Timing Diagram 8 _______________________________________________________________________________________ 1:5 Differential LVPECL/LVECL/HSTL Clock and Data Driver MAX9315 EN CLK CLK tS tH tS tH tPLHD Q_ Q_ OUTPUTS ARE LOW OUTPUTS STAY LOW Figure 3. MAX9315 EN Timing Diagram _______________________________________________________________________________________ 9 1:5 Differential LVPECL/LVECL/HSTL Clock and Data Driver MAX9315 Functional Diagram VCC Q0 75kΩ Q0 CLK0 Q1 CLK0 Q1 75kΩ VEE 75kΩ Q2 VEE 0 VCC Q2 Q3 1 75kΩ CLK1 Q3 CLK1 Q4 75kΩ 75kΩ Q4 VEE VEE SEL Q EN D VBB VCC 10 MAX9315 ______________________________________________________________________________________ 1:5 Differential LVPECL/LVECL/HSTL Clock and Data Driver TSSOP4.40mm.EPS Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 11 © 2004 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products. MAX9315 Package Information (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.)