19-2511; Rev 1; 7/02 2:8 Differential LVPECL/LVECL/HSTL Clock and Data Driver Features ♦ 50ps (max) Output-to-Output Skew ♦ 1.5psRMS (max) Random Jitter ♦ Guaranteed 300mV Differential Output at 700MHz ♦ +2.375V to +3.8V Supplies for Differential HSTL/LVPECL ♦ -2.375V to -3.8V Supplies for Differential LVECL ♦ Two Selectable Differential Inputs The differential inputs can be configured to accept a single-ended signal when the unused complementary input is connected to the on-chip reference output voltage VBB. All inputs have internal pulldown resistors to V EE. The internal pulldowns and a fail-safe circuit ensure differential low default outputs when the inputs are left open or at VEE. The MAX9325 operates over a 2.375V to 3.8V supply range for interfacing to differential HSTL and LVPECL signals. This allows high-performance clock or data distribution in systems with a nominal +2.5V or +3.3V supply. For LVECL operation, the device operates with a -2.375V to -3.8V supply. ♦ On-Chip Reference for Single-Ended Inputs ♦ Outputs Low for Inputs Open or at VEE ♦ Pin Compatible with MC100LVE310 Ordering Information PART The MAX9325 is offered in 28-lead PLCC and spacesaving 28-lead QFN packages. The MAX9325 is specified for operation from -40°C to +85°C. TEMP RANGE PIN-PACKAGE MAX9325EQI -40°C to +85°C 28 PLCC MAX9325ETI* -40°C to +85°C 28 QFN 5mm x 5mm *Future product—contact factory for availability. Applications Functional Diagram appears at end of data sheet. Precision Clock Distribution Low-Jitter Data Repeaters INPUT SELECT TRUTH TABLE VEE 26 18 Q3 CLK_SEL 27 17 Q3 VEE 1 21 Q3 CLKO 28 16 Q4 CLK_SEL 2 20 Q3 CLKO 3 19 Q4 1 CLKO 2 14 Q4 VCC 4 18 VCC VBB 3 13 Q5 CLKO 5 17 Q4 CLK1 4 12 Q5 VBB 6 16 Q5 CLK1 7 15 Q5 11 12 13 14 Q7 Q6 Q6 10 Q7 VCC 9 PLCC 8 11 N.C. Q7 10 Q6 N.C. 9 Q6 CLK1 8 Q7 7 VCC 6 MAX9325 * 5 VCC CLK1 15 INPUT CLOCK L CLK0, CLK0 SELECTED H CLK1, CLK1 SELECTED * VCC MAX9325 CLK_SEL * Q2 Q2 22 23 VCC Q1 Q1 24 25 * 26 Q0 19 Q0 20 27 Q2 23 22 21 28 Q2 VCC Q1 25 24 Q1 Q0 TOP VIEW Q0 Pin Configurations QFN *CORNER PINS AND EXPOSED PAD ARE CONNECTED TO VEE. ________________________________________________________________ Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. 1 MAX9325 General Description The MAX9325 low-skew, 2:8 differential driver features extremely low output-to-output skew (50ps max) and part-to-part skew (225ps max). These features make the device ideal for clock and data distribution across a backplane or board. The device selects one of the two differential HSTL or LVECL/LVPECL inputs and repeats them at eight differential outputs. Outputs are compatible with LVECL and LVPECL, and can directly drive 50Ω terminated transmission lines. MAX9325 2:8 Differential LVPECL/LVECL/HSTL Clock and Data Driver ABSOLUTE MAXIMUM RATINGS VCC - VEE ...............................................................-0.3V to +4.1V Inputs (CLK_, CLK_, CLK_SEL) to VEE ......-0.3V to (VCC + 0.3V) CLK_ to CLK_ .....................................................................±3.0V Continuous Output Current .................................................50mA Surge Output Current........................................................100mA VBB Sink/Source Current................................................±0.65mA Continuous Power Dissipation (TA = +70°C) 28-Lead PLCC (derate 10.5mW/°C above +70°C) .....842mW θJA in Still Air .............................................................+95°C/W θJC .............................................................................+25°C/W 28-Lead QFN (derate 20.8mW/°C above +70°C) ....1667mW θJA in Still Air ............................................................+48°C/W θJC ..............................................................................+2°C/W Operating Temperature Range ...........................-40°C to +85°C Junction Temperature ......................................................+150°C Storage Temperature Range .............................-65°C to +150°C ESD Protection Human Body Model (CLK_, CLK_, Q_, Q_)....................≥2kV Soldering Temperature (10s) ...........................................+300°C Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. DC ELECTRICAL CHARACTERISTICS ((VCC - VEE) = 2.375V to 3.8V, RL = 50Ω ±1% to VCC - 2V. Typical values are at (VCC - VEE) = 3.3V, VIH = (VCC - 1V), VIL = (VCC - 1.5V).) (Notes 1–4) PARAMETER SYMBOL CONDITIONS -40°C MIN TYP +25°C MAX MIN TYP +85°C MAX MIN TYP MAX UNITS SINGLE-ENDED INPUT (CLK_SEL) Single-Ended Input High Voltage VIH Figure 1 VCC - 1.165 VCC VCC - 1.165 Single-Ended Input Low Voltage VIL Figure 1 VEE VCC - 1.475 VEE VCC - 1.475 Input Current IIN VIH, VIL -10.0 +150 -10.0 VCC VCC - 1.165 VCC V VEE VCC - 1.475 V +150 -10.0 +150 µA DIFFERENTIAL INPUT (CLK_, CLK_) Single-Ended Input High Voltage VIH Figure 1 VCC - 1.165 VCC VCC - 1.165 VCC VCC - 1.165 VCC V Single-Ended Input Low Voltage VIL Figure 1 VEE VCC - 1.475 VEE VCC - 1.475 VEE VCC - 1.475 V VIHD Figure 1 VEE + 1.2 VCC VEE + 1.2 VCC VEE + 1.2 VCC V Differential Input High Voltage 2 _______________________________________________________________________________________ 2:8 Differential LVPECL/LVECL/HSTL Clock and Data Driver ((VCC - VEE) = 2.375V to 3.8V, RL = 50Ω ±1% to VCC - 2V. Typical values are at (VCC - VEE) = 3.3V, VIH = (VCC - 1V), VIL = (VCC - 1.5V).) (Notes 1–4) PARAMETER SYMBOL Differential Input Low Voltage VILD Differential Input Voltage VIHD VILD Input Current IIN CONDITIONS -40°C MAX MIN VEE VCC - 0.095 (VCC - VEE) < 3.0V, Figure 1 0.095 (VCC - VEE) ≥ 3.0V, Figure 1 VIH, VIL, VIHD, VILD Figure 1 MIN TYP +25°C TYP +85°C MAX MIN TYP MAX VEE VCC - 0.095 VEE VCC - 0.095 VCC - VEE 0.095 VCC - VEE 0.095 VCC - VEE 0.095 3.0 0.095 3.0 0.095 3.0 -10.0 +150.0 -10.0 +150.0 -10.0 +150.0 UNITS V V µA OUTPUT (Q_, Q_) Single-Ended Output High Voltage VOH Figure 2 VCC VCC VCC VCC VCC VCC VCC VCC VCC - 1.085 - 0.977 - 0.880 - 1.025 - 0.949 - 0.88 - 1.025 - 0.929 - 0.88 V Single-Ended Output Low Voltage VOL Figure 2 VCC VCC VCC VCC VCC VCC VCC VCC VCC - 1.810 - 1.695 - 1.620 - 1.810 - 1.697 - 1.62 - 1.810 - 1.698 - 1.62 V Differential Output Voltage VOH - VOL Figure 2 535 718 595 749 595 769 mV REFERENCE VOLTAGE OUTPUT (VBB) Reference Voltage Output VBB IBB = ±0.5mA (Note 5) IEE (Note 6) VCC VCC - 1.38 - 1.318 VCC - 1.26 VCC VCC VCC - 1.38 - 1.325 - 1.26 VCC VCC VCC - 1.38 - 1.328 - 1.26 V 50 39 42 mA SUPPLY Supply Current 35 55 65 _______________________________________________________________________________________ 3 MAX9325 DC ELECTRICAL CHARACTERISTICS (continued) MAX9325 2:8 Differential LVPECL/LVECL/HSTL Clock and Data Driver AC ELECTRICAL CHARACTERISTICS ((VCC - VEE) = 2.375V to 3.8V, RL = 50Ω ±1% to VCC - 2V, fIN ≤ 500MHz, input transition time = 125ps (20% to 80%). Typical values are at (VCC - VEE) = 3.3V, VIH = (VCC - 1V), VIL = (VCC - 1.5V).) (Note 7) PARAMETER SYMBOL Differential Input-to-Output Delay tPLHD tPHLD Single-Ended Input-to-Output Delay tPLH tPHL CONDITIONS -40°C MIN TYP +25°C MAX MIN TYP +85°C MAX MIN TYP MAX UNITS Figure 2 475 650 460 710 490 740 ps Figure 3 (Note 8) 440 780 430 790 450 800 ps Output-toOutput Skew tSKOO (Note 9) 50 50 50 ps Part-to-Part Skew tSKPP Differential input (Note 10) 160 190 225 ps Added Random Jitter tRJ fIN = 0.5GHz clock pattern (Note 11) 1.5 1.5 1.5 psRMS Added Deterministic Jitter tDJ fIN = 1.0Gbps, 2E23 - 1 PRBS pattern (Note 11) 100 100 100 psP-P Switching Frequency fMAX VOH - VOL ≥ 300mV clock pattern 700 Output Rise/Fall Time (20% to 80%) tR, tF Figure 2 140 Note 1: Note 2: Note 3: Note 4: Note 5: Note 6: Note 7: Note 8: Note 9: Note 10: Note 11: 4 1000 700 440 140 1000 700 440 1000 140 MHz 440 ps Measurements are made with the device in thermal equilibrium. Current into a pin is defined as positive. Current out of a pin is defined as negative. DC parameters production tested at TA = +25°C and guaranteed by design over the full operating temperature range. Single-ended input operation using VBB is limited to (VCC - VEE) = 3.0V to 3.8V. Use VBB only for inputs that are on the same device as the VBB reference. All pins open except VCC and VEE. Guaranteed by design and characterization. Limits are set at ±6 sigma. Measured from the 50% point of the input signal with the 50% point equal to VBB, to the 50% point of the output signal. Measured between outputs of the same part at the signal crossing points for a same-edge transition. Differential input signal. Measured between outputs of different parts under identical condition for same-edge transition. Device jitter added to the input signal. Differential input signal. _______________________________________________________________________________________ 2:8 Differential LVPECL/LVECL/HSTL Clock and Data Driver OUTPUT AMPLITUDE (VOH - VOL) vs. FREQUENCY 40 35 30 TRANSITION TIME vs. TEMPERATURE MAX9325 toc02 350 800 325 TRANSITION TIME (ps) OUTPUT VOLTAGE HIGH (V) 45 700 600 tR 275 250 400 20 -15 10 35 60 0 85 200 400 600 800 1000 1200 1400 -40 -15 FREQUENCY (MHz) TEMPERATURE (°C) PROPAGATION DELAY vs. DIFFERENTIAL INPUT HIGH VOLTAGE (VIHD) tPLH 500 tPHL 400 60 85 PROPAGATION DELAY vs. TEMPERATURE 750 PROPAGATION DELAY (ps) 600 35 MAX9325 toc05 700 10 TEMPERATURE (°C) MAX9325 toc04 -40 tF 300 500 25 PROPAGATION DELAY (ps) SUPPLY CURRENT (mA) 900 MAX9325 toc01 50 MAX9325 toc03 SUPPLY CURRENT (IEE) vs. TEMPERATURE 650 tPLHD 550 tPHLD 300 450 0.6 0.8 1.0 1.2 1.4 1.6 1.8 DIFFERENTIAL INPUT HIGH VOLTAGE (V) 2.0 -40 -15 10 35 60 85 TEMPERATURE (°C) _______________________________________________________________________________________ 5 MAX9325 Typical Operating Characteristics (Typical values are at (VCC - VEE) = 3.3V, VIH = (VCC - 1V), VIL = (VCC - 1.5V), RL = 50Ω ±1% to VCC - 2V, fIN = 500MHz, input transition time = 125ps (20% to 80%).) 2:8 Differential LVPECL/LVECL/HSTL Clock and Data Driver MAX9325 Pin Description PIN 6 NAME FUNCTION PLCC QFN 1, 8, 15, 22 4, 11, 18, 25 VCC 2 5 CLK0 3 6 VBB 4 7 CLK1 Noninverting Differential Clock Input 1. Internal 105kΩ pulldown to VEE. 5 8 CLK1 Inverting Differential Clock Input 1. Internal 105kΩ pulldown to VEE. 6 9 N.C. 7 10 Q7 Inverting Q7 Output. Typically terminate with 50Ω resistor to VCC - 2V. Noninverting Q7 Output. Typically terminate with 50Ω resistor to VCC - 2V. Positive Supply Voltage. Bypass each VCC to VEE with 0.1µF and 0.01µF ceramic capacitors. Place the capacitors as close to the device as possible, with the smaller value capacitor closest to the device. Inverting Differential Clock Input 0. Internal 105kΩ pulldown to VEE. Reference Output Voltage. Connect to the inverting or noninverting clock input to provide a reference for single-ended operation. When used, bypass VBB to VCC with a 0.01µF ceramic capacitor. Otherwise leave open. Not Connected 9 12 Q7 10 13 Q6 Inverting Q6 Output. Typically terminate with 50Ω resistor to VCC - 2V. 11 14 Q6 Noninverting Q6 Output. Typically terminate with 50Ω resistor to VCC - 2V. 12 15 Q5 Inverting Q5 Output. Typically terminate with 50Ω resistor to VCC - 2V. 13 16 Q5 Noninverting Q5 Output. Typically terminate with 50Ω resistor to VCC - 2V. 14 17 Q4 Inverting Q4 Output. Typically terminate with 50Ω resistor to VCC - 2V. 16 19 Q4 Noninverting Q4 Output. Typically terminate with 50Ω resistor to VCC - 2V. 17 20 Q3 Inverting Q3 Output. Typically terminate with 50Ω resistor to VCC - 2V. 18 21 Q3 Noninverting Q3 Output. Typically terminate with 50Ω resistor to VCC - 2V. 19 22 Q2 Inverting Q2 Output. Typically terminate with 50Ω resistor to VCC - 2V. 20 23 Q2 Noninverting Q2 Output. Typically terminate with 50Ω resistor to VCC - 2V. 21 24 Q1 Inverting Q1 Output. Typically terminate with 50Ω resistor to VCC - 2V. 23 26 Q1 Noninverting Q1 Output. Typically terminate with 50Ω resistor to VCC - 2V. 24 27 Q0 Inverting Q0 Output. Typically terminate with 50Ω resistor to VCC - 2V. 25 28 Q0 Noninverting Q0 Output. Typically terminate with 50Ω resistor to VCC - 2V. 26 1 VEE Negative Supply Voltage 27 2 CLK_SEL 28 3 CLK0 Exposed Exposed Pad — Clock Select Input. When driven low, the CLK0 input is selected. Drive high to select the CLK1 Input. The CLK_SEL threshold is equal to VBB. Internal 75kΩ pulldown to VEE. Noninverting Differential Clock Input 0. Internal 105kΩ pulldown to VEE. Internally Connected to VEE _______________________________________________________________________________________ 2:8 Differential LVPECL/LVECL/HSTL Clock and Data Driver VIHD (MAX) MAX9325 VCC VCC VIHD - VILD VIH VILD (MAX) VBB VIL VIHD (MIN) VIHD - VILD VILD (MIN) VEE VEE DIFFERENTIAL INPUT VOLTAGE DEFINITION SINGLE-ENDED INPUT VOLTAGE DEFINITION Figure 1. Input Voltage Definitions CLK VIHD VIHD - VILD VILD CLK tPHLD tPLHD Q_ VOH VOH - VOL Q_ VOL 80% 80% VOH - VOL 0V (DIFFERENTIAL) VOH - VOL DIFFERENTIAL OUTPUT WAVEFORM 20% 20% Q_ - Q_ tR tF Figure 2. Differential Input (CLK_, CLK_) to Output (Q_, Q_) Delay Timing Diagram _______________________________________________________________________________________ 7 MAX9325 2:8 Differential LVPECL/LVECL/HSTL Clock and Data Driver CLK_ WHEN CLK_ = VBB VIH VBB VBB VIL OR VIH VBB VBB CLK_ WHEN CLK_ = VBB VIL tPLH tPHL VOH Q_ VOH - VOL VOL Q_ Figure 3. Single-Ended Input (CLK_, CLK_) to Output (Q_, Q_) Delay Timing Diagram Detailed Description The MAX9325 low-skew, 2:8 differential driver features extremely low output-to-output skew (50ps max) and part-to-part skew (225ps max). These features make the device ideal for clock and data distribution across a backplane or board. The device selects one of the two differential HSTL or LVECL/LVPECL inputs, and repeats them at eight differential outputs. Outputs are compatible with LVECL and LVPECL, and can directly drive 50Ω terminated transmission lines. A 2:1 mux selects between the two differential inputs, CLK0, CLK0 and CLK1, CLK1. The 2:1 mux is switched by the single-ended CLK_SEL input. A logic low selects the CLK0, CLK0 input. A logic high selects the CLK1, CLK1 input. The logic threshold for CLK_SEL is set by an internal VBB voltage reference. The selected input is reproduced at eight differential outputs at speeds up to 700MHz. The differential inputs can be configured to accept a single-ended signal when the unused complementary input is connected to the on-chip reference output voltage (VBB). A single-ended input of at least VBB ±95mV or a differential input of at least 95mV switches the outputs to the VOH and VOL levels specified in the DC Electrical Characteristics. The maximum magnitude of the differential input from CLK_ to CLK_ is ±3.0V or 8 ±(VCC - VEE), whichever is less. This limit also applies to the difference between a single-ended input and any reference voltage input. The single-ended CLK_SEL input has a 75kΩ pulldown to VEE that selects the default input, CLK0, CLK0, when CLK_SEL is left open or at VEE. All the differential inputs have 105kΩ pulldowns to VEE. Internal pulldowns and a fail-safe circuit ensure differential low default outputs when the inputs are left open or at VEE. Specifications for the high and low voltages of a differential input (VIHD and VILD) and the differential input voltage (VIHD - VILD) apply simultaneously. For interfacing to differential HSTL and LVPECL signals, these devices operate over a +2.375V to +3.8V supply range, allowing high-performance clock or data distribution in systems with a nominal +2.5V or +3.3V supply. For differential LVECL operation, these devices operate from a -2.375V to -3.8V supply. Single-Ended Operation CLK_SEL is a single-ended input with the input threshold internally set to VBB, and can be driven to VCC or VEE or by a single-ended LVPECL/LVECL signal. The CLK_, CLK_ are differential inputs but can be configured to accept single-ended inputs when operating at supply voltages greater than 2.58V. The recommended supply voltage for single-ended operation is 3.0V to 3.8V. A dif- _______________________________________________________________________________________ 2:8 Differential LVPECL/LVECL/HSTL Clock and Data Driver When using the VBB reference output, bypass it with a 0.01µF ceramic capacitor to VCC. If not used, leave it open. The VBB reference can source or sink 0.5mA, which is sufficient to drive two inputs. Traces Circuit board trace layout is very important to maintain the signal integrity of high-speed differential signals. Maintaining integrity is accomplished in part by reducing signal reflections and skew, and increasing common-mode noise immunity. Signal reflections are caused by discontinuities in the 50Ω characteristic impedance of the traces. Avoid discontinuities by maintaining the distance between differential traces, not using sharp corners or using vias. Maintaining distance between the traces also increases common-mode noise immunity. Reducing signal skew is accomplished by matching the electrical length of the differential traces. Exposed-Pad Package The 28-lead QFN package (MAX9325EGI) has the exposed paddle on the bottom of the package that provides the primary heat removal path from the IC to the PC board, as well as excellent electrical grounding to the PC board. The MAX9325EGI’s exposed pad is internally connected to V EE . Do not connect the exposed pad to a separate circuit ground plane unless VEE and the circuit ground are the same. Chip Information TRANSISTOR COUNT: 1030 PROCESS: Bipolar Functional Diagram Applications Information Q0 Output Termination Terminate the outputs through 50Ω to (VCC - 2V) or use equivalent Thevenin terminations. Terminate each Q and Q output with identical termination on each for low output distortion. When a single-ended signal is taken from the differential output, terminate both Q_ and Q_. Q0 MAX9325 CLK0 Q1 CLK0 Q1 Q2 105kΩ Q2 Ensure that output currents do not exceed the current limits as specified in the Absolute Maximum Ratings table. Under all operating conditions, the device’s total thermal limits should be observed. CLK1 Q4 Supply Bypassing CLK1 Q4 Bypass each VCC to VEE with high-frequency surfacemount ceramic 0.1µF and 0.01µF capacitors. Place the capacitors as close to the device as possible with the 0.01µF capacitor closest to the device pins. Use multiple vias when connecting the bypass capacitors to ground. When using the VBB reference output, bypass it with a 0.01µF ceramic capacitor to VCC. If the VBB reference is not used, it can be left open. VEE 105kΩ 0 Q3 1 Q3 Q5 Q5 VEE CLK_SEL Q6 Q6 75kΩ Q7 VEE Q7 _______________________________________________________________________________________ 9 MAX9325 ferential input is configured for single-ended operation by connecting the on-chip reference voltage, VBB, to an unused complementary input as a reference. For example, the differential CLK0, CLK0 input is converted to a noninverting, single-ended input by connecting VBB to CLK0 and connecting the single-ended input to CLK0. Similarly, an inverting input is obtained by connecting VBB to CLK0 and connecting the single-ended input to CLK0. With a differential input configured as singleended (using VBB), the single-ended input can be driven to VCC or VEE or with a single-ended LVPECL/LVECL signal. When configuring a differential input as a single-ended input, a user must ensure that the supply voltage (VCC VEE) is greater than 2.58V. This is because the input high minimum level must be at (VEE + 1.2V) or higher for proper operation. The reference voltage VBB must be at least (VEE + 1.2V) or higher for the same reason because it becomes the high-level input when the other single-ended input swings below it. The minimum VBB output for the MAX9325 is (VCC - 1.38V). Substituting the minimum VBB output for (VBB = VEE + 1.2V) results in a minimum supply (VCC - VEE) of 2.58V. Rounding up to standard supplies gives the single-ended operating supply ranges (V CC - V EE ) of 3.0V to 3.8V for the MAX9325. Package Information (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.) PLCC.EPS MAX9325 2:8 Differential LVPECL/LVECL/HSTL Clock and Data Driver 10 ______________________________________________________________________________________ 2:8 Differential LVPECL/LVECL/HSTL Clock and Data Driver 32L QFN.EPS Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 11 © 2002 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products. MAX9325 Package Information (continued) (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.)