PERICOM PI2EQX3201ZFE

PI2EQX3201
3.2Gbps 2 Differential Channel Serial Re-driver
with built-in Equalization and De-emphasis
Features
Description
•
Two 3.2Gbps differential signal
•
Adjustable Transmiter De-Emphasis & Amplitude
•
Adjustable Receiver Equalization
•
One Spread Spectrum Reference Clock Buffer Output
•
100Ω Differential CML I/O’s
•
Low Power (100mW per Channel)
•
Stand-by Mode – Power Down State
•
VCC Operating Range: 1.8V ±0.1V
•
Built in Clock Buffer
•
Packaging (Pb-free & Green):
— 36-pad TQFN (ZF36)
Pericom Semiconductor’s PI2EQX3201 is a low power, signal
re-driver. The device provides programmable equalization,
amplification, and de-emphasis by using 4 select bits, SEL[0:3],
to optimize performance over a variety of physical mediums by
reducing Inter-symbol interference. PI2EQX3201 supports two
100 Differential CML data I/O’s between the Protocol ASIC to
a switch fabric, across a backplane, or extends the signals across
other distant data pathways on the user’s platform.
The integrated equalization circuitry provides flexibility with
signal integrity of the signal before the re-driver. Whereas the
integrated de-emphasis circuitry provides flexibility with signal
integrity of the signal after the re-driver.
In addition to providing signal re-conditioning, Pericom’s
PI2EQX3201 also provides power management Stand-by mode
operated by a Bus Enable pin.
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SEL2_A
SEL3_A
EN_A
EN_B
35
34
33
32
31
30
29
1
28
VDD
AI+
2
27
A0+
AI-
3
26
A0-
GND
4
25
GND
AVDD
5
24
AGND
VDD
6
23
VDD
B0+
7
22
BI+
B0-
8
21
BI-
GND
9
20
GND
VDD
10
19
IREF
GND
11
12
13
14
15
16
17
18
CLKIN-
SEL0_B
SEL1_B
SEL2_B
SEL3_B
OUT+
OUT-
1
36
VDD
CLKIN+
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SEL1_A
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SEL0_A
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NC
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NC
Pin Description
Block Diagram
PS8818
02/28/06
PI2EQX3201
3.2Gbps 2 Differential Channel Serial Re-driver
with built-in Equalization and De-emphasis
Pin Description
Pin #
1, 6, 10, 23, 28
2
3
4, 9, 20, 25
22
21
33, 34
13, 14
32
15
31
16
Pin Name
VDD
AI+
AIGND
BI+
BISEL[0:1]_A
SEL[0:1]_B
SEL[2]_A
SEL[2]_B
SEL[3]_A
SEL[3]_B
I/O
PWR
I
I
PWR
I
I
I
I
I
I
I
I
27
AO+
O
26
AO-
O
7
BO+
O
8
BO-
O
30, 29
EN_[A,B]
I
12
11
17, 18
5
24
19
35, 36
CLKINCLKIN+
OUT+, OUTAVDD
AGND
IREF
NC
I
I
O
PWR
PWR
O
N/A
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Description
1.8V Supply Voltage
Positive CML Input Channel A with internal 50Ω pull down
Negative CML Input Channel A with internal 50Ω pull down
Supply Ground
Positive CML Input Channel B with internal 50Ω pull down
Negative CML Input Channel B with internal 50Ω pull down
Selection pins for equalizer (see Amplifier Configuration Table)
w/ 50KΩ internal pull up
Selection pins for amplifier (see Amplifier Configuration Table)
w/ 50KΩ internal pull up
Selection pins for De-Emphasis (See De-Emphasis Configuration Table)
w/ 50KΩ internal pull up
Positive CML Output Channel A internal 50Ω pull up during normal operation and
2KΩ pull up otherwise.
Negative CML Output Channel A with internal 50Ω pull up during normal operation and 2KΩ pull up otherwise.
Positive CML Output Channel B with internal 50Ω pull up during normal operation
and 2KΩ pull up otherwise.
Negative CMLOutput Channel B with internal 50Ω pull up during normal operation and 2KΩ pull up otherwise.
EN_[A:B] is the enable pin. A LVCMOS high provides normal operation. A LVCMOS low selects a low power down mode.
Differential Input Reference Clock
Differential Reference Clock Output
1.8V Analog supply voltage
Analog ground
External 475Ω resistor connection to set the differential output current
No connect pins. For normal operation, leave pins floating
2
PS8818
02/28/06
PI2EQX3201
3.2Gbps 2 Differential Channel Serial Re-driver
with built-in Equalization and De-emphasis
Maximum Ratings
(Above which useful life may be impaired. For user guidelines, not tested.)
Storage Temperature........................................................ –65°C to +150°C
Supply Voltage to Ground Potential ................................... –0.5V to +2.5V
DC SIG Voltage.......................................................... –0.5V to VCC +0.5V
Current Output ................................................................-25mA to +25mA
Power Dissipation Continous ......................................................... 500mW
Operating Temperature.............................................................. 0 to +70°C
Output Swing Control
SEL2_[A:B]
0
1
Note:
Stresses greater than those listed under MAXIMUM RATINGS may cause permanent damage to the device. This is
a stress rating only and functional operation of the device
at these or any other conditions above those indicated in
the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect reliability.
Output De-emphasis Adjustment
Swing
1x
1.2x
SEL3_[A:B]
0
1
De-emphasis
0dB
-3.5dB
Equalizer Selection
SEL0_[A:B]
0
0
1
1
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SEL1_[A:B]
0
1
0
1
Compliance Channel
no equalization
[0:2.5dB] @ 1.6 GHz
[2.5:4.5dB] @ 1.6 GHz
[4.5:6.5dB] @ 1.6 GHz
3
PS8818
02/28/06
PI2EQX3201
3.2Gbps 2 Differential Channel Serial Re-driver
with built-in Equalization and De-emphasis
AC/DC Electrical Characteristics (VDD = 1.8 ±0.1V)
Symbol
Ps
Parameter
Supply Power
Latency
CML Receiver Input
RLRX
Return Loss
Differential Input Peak-toVRX-DIFFP-P
peak Voltage
AC Peak Common Mode
VRX-CM-ACP
Input Voltage
DC Differential Input
ZRX-DIFF-DC
Impedance
ZRX-DC
DC Input Impedance
Conditions
EN = LVCMOS Low
EN = LVCMOS High
From input to output
Min.
50 MHz to 1.25 GHz
Typ.
Max.
0.1
0.3
Units
W
2.0
ns
12
dB
0.175
1.200
V
150
mV
80
100
120
40
50
60
Ω
Equalization
JRS
Residual Jitter(1,2)
JRM
Random Jitter(1,2)
Total Jitter
Deterministic jitter
0.3
0.2
1.5
Ulp-p
psrms
Notes
1. K28.7 pattern is applied differentially at point A as shown in Figure 1.
2. Total jitter does not include the signal source jitter. Total jitter (TJ) = (14.1 × RJ + DJ) where RJ is random RMS jitter and DJ is maximum
deterministic jitter. Signal source is a K28.5 ± pattern (00 1111 1010 11 0000 0101) for the deterministic jitter test and K28.7 (0011111000) or
equivalent for random jitter test. Residual jitter is that which remains after equalizing media-induced losses of the environment of Figure 1 or
its equivalent. The deterministic jitter at point B must be from media-induced loss, and not from clock source modulation. JItter is measured at
0V at point C of Figure 1.
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Figure 1. Test Condition Referenced in the Electrical Characteristic Table
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PS8818
02/28/06
PI2EQX3201
3.2Gbps 2 Differential Channel Serial Re-driver
with built-in Equalization and De-emphasis
AC/DC Electrical Characteristics (TA = 0 to 70˚C)
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Units
900
mVp-p
150
ps
CML Transmitter Output (100Ω differential)
VDIFFP
Output Voltage Swing
Differential Swing
| VTX-D+ - VTX-D- |
VTX-C
Common-Mode Voltage
| VTX-D+ + VTX-D- | / 2
tF, tR
Transition Time
20% to 80% (1)
ZOUT
Output resistance
Single ended
ZTX-DIFF-DC
400
VCC0.3
40
50
60
Ω
DC Differential TX Impedance
80
100
120
Ω
CTX
AC Coupling Capacitor
75
200
nF
VTX-DIFFP-P
Differential Peak-to-peak Ouput
Voltage
0.8
1.8
V
VTX-DIFFP-P = 2 * | VTX-D+ - VTX-D- |
LVCMOS Control Pins
0.65 ×
VDD
VIH
Input High Voltage
VIL
Input Low Voltage
0.35 ×
VDD
IIH
Input High Current
250
IIL
Input Low Current
500
V
µA
Note:
1. Using K28.7 (0011111000) pattern)
06-0086
5
PS8818
02/28/06
PI2EQX3201
3.2Gbps 2 Differential Channel Serial Re-driver
with built-in Equalization and De-emphasis
AC Switching Characteristics for Clock Buffer (VDD = 1.8 ±0.1V, AVDD = 1.8 ±0.1V) (3)
Symbol
Trise / Tfall
Parameters
Rise and Fall Time (measured between 0.175V to 0.525V)
(1)
Min
Max.
125
525
ΔTrise /
ΔTfall
Rise and Fall Time Variation
VHIGH
Voltage High including overshoot
660
VLOW
Voltage Low including undershoot
-200
Absolute crossing point voltages
200
VCROSS
ΔVCROSS
TDC
75
Total Variation of Vcross over all edges
Duty Cycle (input duty cycle = 50%)
Units
1
ps
900
550
45
55
1
1
mV
250
(2)
Notes
1
1
1
%
2
Notes:
1. Measurement taken from Single Ended waveform.
2. Measurement taken from Differential waveform.
3. Test configuration is RS = 33.2Ω, Rp = 49.9Ω, and 2pF.
Configuration Test Load Board Termination
Rs
33Ω
5%
CLKBUF
Clock
TLA
Rs
33Ω
5%
Clock#
TLB
Rp
49.9Ω
1%
475Ω
1%
Rp
49.9Ω
1%
2pF
5%
2pF
5%
Figure 2. Configuration test load board termination
Note:
• TLA and TLB are 3” transmission lines.
06-0086
6
PS8818
02/28/06
PI2EQX3201
3.2Gbps 2 Differential Channel Serial Re-driver
with built-in Equalization and De-emphasis
Packaging Mechanical: 36-pad TQFN (ZF36)
6.00±0.10
3.50 REF.
5.00±0.10
4.50 REF.
Pin #1 Corner
Pin #1 Corner
0.20 REF.
0.50 TYP. (36x)
Ordering Information
Ordering Number
Package Code
Package Description
PI2EQX3201ZFE
ZF
Pb-Free and Green 36-pad TQFN
Notes:
• Thermal characteristics can be found on the company web site at www.pericom.com/packaging/
• E = Pb-free and Green
• X suffix = Tape/Reel
Pericom Semiconductor Corporation • 1-800-435-2336 • www.pericom.com
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PS8818
02/28/06