Datasheet

PI3EQX4951ST
3.3V, 1-port, SATA2 i/m ReDriver™ with Analog/Digital Configuration
Features
Description
ÎÎSATA2 i, m; external SATA2
Pericom Semiconductor’s PI3EQX4951ST is a low power, signal
ReDriver™. The device provides programmable equalization, to
optimize performance over a variety of physical mediums by
reducing Inter-Symbol Interference. PI3EQX4951ST supports
two 100-Ohm Differential CML data I/O’s between the Protocol
ASIC to a switch fabric, across a backplane, or to extend the signals across other distant data pathways on the user’s platform.
ÎÎTwo 3.0Gbps differential signal pairs
ÎÎIndependent Digital Output Emphasis Control
ÎÎ100-Ohm Differential CML I/O’s
ÎÎInput signal level detect and squelch for each channel
ÎÎOOB Support
The integrated equalization circuitry provides flexibility with
signal integrity of the signal before the ReDriver.
ÎÎEnhanced Mode Features:
àà Adjustable Receiver Equalization
àà Independent Analog Output Emphasis Control
ÎÎHigh impedance I/O termination in standby mode
A low-level input signal detection and output squelch function is
provided for each channel. Each channel operates fully independently. When the channels are enabled (EN=1) and operating,
that channels input signal level (on xI+/-) determines whether
the output is active. If the input signal level of the channel falls
below the active threshold level (Vth-) then the outputs are
driven to the common mode voltage.
ÎÎLow Power Operation: 300mW typical
ÎÎAuto-Slumber Mode: 33mW typical
ÎÎPower down Stand-by Mode: 0.1mW
ÎÎSupply Voltage: 3.3V ±10%
In addition to signal conditioning, when EN = 0, the device
enters a low power standby mode.
20-TQFN (4x4mm)
GND
Signal Detection
GND
VDD
Standard Mode (MODE = 0)
NC
Pin Diagram (Top Side View)
Block Diagram
MODE
ÎÎPackaging:
20 19 18 17 16
AO+
NC
2
3
14
13
NC
BO-
4
BO+
5
BIBI+
8 9 10
Enhanced Mode (MODE = 1)
VDD
A_EM
A_EQ
MODE
NC
- Repeated 2 times -
Control
Circuit
12
11
AO-
A_EM
VDD
xO-
Power
Management
6 7
Limiting
Amp
xl-
EN
GND
NC
Equalizer
xO+
15
AI-
B_EM
CML
xl+
1
EN
CML
AI+
x_EQ
x_EM
AI+
1
AI-
2
3
NC
BO-
GND
6 7 8 9 10
15
14
AO+
AONC
13
12
BI-
11
BI+
NC
EN
B_EQ
B_EM
VDD
BO+
4
5
20 19 18 17 16
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PS9072A
03/23/10
PI3EQX4951ST
3.3V, 1-Port, SATA2 i/m ReDriver™with Analog/Digital Configuration
Pin Description
Standard Enhanced
Mode Pin Mode Pin
#
#
Pin
Name
Type
Description
Output emphasis adjustment for channel A.
When in Standard Mode (MODE= 0) digital control is enabled, and a 150KOhm pull-up resistor is enabled on A_EM.
9
19
A_EM
Input
When in Enhanced Mode (MODE= 1) analog resistive adjustment of emphasis is
enabled.
Refer to Configuration Tables and System Implementation diagrams for design
guidelines.
—
18
A_EQ
Input
Channel A Equalization adjustment is active only in Enhanced Mode
(MODE = 1). With internal 150K-Ohm pull-up to VDD. Refer to Enhanced
Mode Configuration Table and System Implementation diagram for design
guidelines.
1
2
1
2
AI+
AI-
Input
CML input forward channel A with internal 50-Ohm pull-up resistors connected to VBIAS (100-Ohm differential).
15
14
15
14
AO+
AO-
Output
CML output channel A with internal 50-Ohm pull-up resistors connected to
VBIAS (100-Ohm differential).
Output emphasis adjustment for channel B.
When in Standard Mode (MODE= 0) digital control is enabled, and a 100-Ohm
pull-up resistor is enabled on A_EM.
8
9
B_EM
Input
When in Enhanced Mode (MODE= 1) analog resistive adjustment of
emphasis is enabled.
Refer to Configuration Tables and System Implementation diagrams for design
guidelines.
—
8
B_EQ
Input
Channel A Equalization adjustment, is active only in Enhanced Mode
(MODE = 1). With internal 150K-Ohm pull-up to VDD. Refer to Enhanced
Mode Configuration Table and System Implementation diagram for design
guidelines.
11
12
11
12
BI+
BI-
Input
CML input return channel B with internal 50-Ohm pull-up, resistor connected
to VBIAS (100-Ohm differential).
5
4
5
4
BO+
BO-
Output
Positive CML output channel B with internal 50-Ohm pull-up resistor connected to VBIAS (100-Ohm differential).
7
7
EN
Input
Chip Enable "High" provides normal operation. "Low" for power down mode.
With internal 150K-Ohm pull-up resistor.
18, 19,
Center Pad
Center Pad
GND
GND
Supply ground.
10, 20
10, 20
VDD
Power
3.3V supply voltage ± 10%
17
17
MODE
Input
MODE selects Enhanced Mode operation and pin function when high. When
MODE is low, Standard Mode operation is selected. With 150K-Ohm pull-up
resistor to VDD. See Configuration tables for use information.
3, 6, 13, 16
3, 6, 13, 16
NC
—
No internal connection
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PS9072A
03/23/10
PI3EQX4951ST
3.3V, 1-Port, SATA2 i/m ReDriver™with Analog/Digital Configuration
Configuration Table (Standard Mode)
A_EM (1)
Output B
Emphasis
Output A
EN
MODE
B_EM(1)
0
X
X
X
Disable
Disable
1
0
0
0
0dB
0dB
1
0
0
1
0dB
3.0dB
1
0
1
0
3.0dB
0dB
1
0
1
1
3.0dB
3.0dB
Emphasis
Note:
1. Refer to Standard Mode Implementation Diagram
2. In Standard Mode, input equalization is fixed at 2.5dB @1.5GHz (3.0Gbps)
Configuration Table (Enhanced Mode)
Output X
Emphasis
Function
EN
MODE x_EQ
Input X
x_EM
Equalization
0
X
X
n/a
X
n/a
Chip Power Down
1
1
0
2.5dB
1.1K to 15K
resistor
Resistor Controlled, 6dB to 0dB
(1)
Low input equalization
1
1
1
6.5dB
1.1K to 15K
resistor
Resistor Controlled, 6dB to 0dB
(1)
High input equalization
Note:
1. Refer to Enhanced Mode Implementation Diagram
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PS9072A
03/23/10
PI3EQX4951ST
3.3V, 1-Port, SATA2 i/m ReDriver™with Analog/Digital Configuration
Maximum Ratings
(Above which useful life may be impaired. For user guidelines, not tested.)
Storage Temperature.................................................................–65°C to +150°C
Supply Voltage to Ground Potential.........................................–0.5V to +4.6V
DC SIG Voltage..................................................................–0.5V to VDD +0.5V
Current Output ...................................................................... -25mA to +25mA
Power Dissipation Continuous.............................................................. 500mW
Note:
Stresses greater than those listed under MAXIMUM RATINGS may cause permanent damage to the device. This is
a stress rating only and functional operation of the device
at these or any other conditions above those indicated in
the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for
extended periods may affect reliability.
Operating Temperature......................................................................0 to +70°C
ESD, Human Body Model......................................................-8kV to +8kV
AC/DC Electrical Characteristics
Symbol
Parameter
VDD
Power Supply Voltage
PSTANDBY
Supply Power, Standby
PSLUMBER
Supply Power, Slumber
Conditions
Min.
Typ.
3.0
EN = 0
Max.
Units
3.6
V
0.10
33
EN = 1
PACTIVE
Supply Power, Active
IDD-STANDBY
Supply Current Standby
IDD-SLUMBER
Supply Current Slumber
IDD-ACTIVE
Supply Current Active
EN = 1, VRX-DIFFp-p ≥ VTH-SD
tPD
Latency
From input to output
54
mW
350
DIFFP-P ≥ V TH-SD
EN = 0
0.030
15
mA
95
1.5
ns
CML Receiver Input
ZRX-DC
DC Input Impedance
40
50
60
ZRX-DIFF-DC
DC Differential Input
Impedance
80
100
120
VRX-DIFFp-p
Differential Input Peak-topeak Voltage
0.2
VRX-CM-ACP
AC Peak Common Mode
Input Voltage
VTH-SD
Signal detect Threshold
RLdd11_RX
RX differential mode return
loss
EN = 1
50
75MHz-300MHz
18
300MHz-600MHz
14
600MHz-1.2GHz
10
1.2GHz-2.4GHz
8
2.4GHz-3.0GHz
3
3.0 GHz-5.0GHz
1
Ohm
0.7
V
150
mV
200(2)
mVppd
dB
(continued)
Note:
1. Typical values are at V DD = 3.3V, TA = 25°C ambient and maximum loading.
2. Using Compliance test at 1.5Gbps and 3Gbps. Also using OOB (OOB is formed by ALIGNp primitive or D24.3) test patterns at 1.5Gbps. The ALIGN primitive
(K28.5+D10.2+D27.3 = 0011111010+0101010101+0010011100). The D24.3 = 00110011001100110011
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PS9072A
03/23/10
PI3EQX4951ST
3.3V, 1-Port, SATA2 i/m ReDriver™with Analog/Digital Configuration
AC/DC Electrical Characteristics (continued)
Symbol
RLcc11_RX
RLdc11_RX
Parameter
RX common mode return loss
RX impedance balance
Conditions
Min.
150MHz – 300MHz
5
300MHZ – 600MHz
5
600MHz – 1.2GHz
2
1.2GHz – 2.4GHz
2
2.4GHz – 3.0GHz
1
3.0GHz – 5.0GHz
1
150MHz – 300MHz
30
300MHz – 600MHz
30
600MHz – 1.2GHz
20
1.2GHz – 2.4GHz
10
2.4GHz – 3.0GHz
4
3.0GHz – 5.0GHz
4
Typ.
Max.
Units
dB
dB
Equalization
TJ
Total Jitter
Measured at 3Gbps/500
0.37
UI
DJ
Deterministic Jitter
Measured at 3Gbps/500
0.19
UI
120
Ohm
CML Transmitter Output (100Ω differential)1
ZTX-DIFF-DC
DC Differential TX Impedance
VTX-DIFFp-p
Differential Peak-to-peak
Output Voltage
VTX-DIFFp-p = 2 * | VTX-D+ VTX-D- |
450
600
mV
VTX-C
Common-Mode Voltage
| VTX-D+ + VTX-D-|/2
1
1.5
V
tF, tR
Transition Time
20% to 80%(1)
50
150
ps
tF-tR
Mis-match Transition Time
3G only; HFTP, MFTP
20
%
Vamp_bal
TX amplitude imbalance
3G only; HFTP, MFTP
10
%
Tskew
TX differential skew
1.5G and 3G; HFTP, MFTP
20
ps
Vcm_ac
TX AC common mode voltage
3G only; MFTP
50
mVpp
VcmOOB
OOB common mode delta
voltage
50
mV
VdiffOOB
OOB differential delta voltage
25
mV
6
dB
80
100
VTX-Pre-Ratio-max Max TX Pre-emphasis Level
(continued)
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PS9072A
03/23/10
PI3EQX4951ST
3.3V, 1-Port, SATA2 i/m ReDriver™with Analog/Digital Configuration
AC/DC Electrical Characteristics (continued)
Symbol
RLdd11_TX
RLcc11_TX
RLdc11_TX
Parameter
TX differential mode return
loss
TX common mode return loss
TX impedance balance
Conditions
Min.
150MHz – 300MHz
14
300MHz – 600MHz
8
600MHz – 1.2GHz
6
1.2GHz – 2.4GHz
6
2.4GHz – 3.0GHz
3
3.0 GHz – 5.0GHz
1
150MHz – 300MHz
5
300MHz – 600MHz
5
600MHz – 1.2GHz
2
1.2GHz – 2.4GHz
2
2.4GHz – 3.0GHz
1
3.0 GHz – 5.0GHz
1
150MHz – 300MHz
30
300MHz – 600MHz
20
600MHz – 1.2GHz
10
1.2GHz – 2.4GHz
10
2.4GHz – 3.0GHz
4
3.0 GHz – 5.0GHz
4
Typ.
Max.
Units
dB
dB
dB
LVCMOS Control Pins
0.65 ×
VDD
VIH
Input High Voltage
VIL
Input Low Voltage
0.35 ×
VDD
IIH
Input High Current
100
IIL
Input Low Current
100
V
µA
Note:
1. Recommended output coupling capacitor is 4.7nF to 12nF (on each output)
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PS9072A
03/23/10
PI3EQX4951ST
3.3V, 1-Port, SATA2 i/m ReDriver™with Analog/Digital Configuration
Pre-emphasis = 20.Log(VDIFF-PRE/VDIFF)
VD+
Common Mode
Voltage
VCM
VDIFF
V D+
VD-
VDIFFp-p
V CM
V_D+ - V_D-
0V
VDIFF-PRE
VDIFF
V D-
VDIFFp-p
2nd + TBIT(s)
1st TBIT
Definition of Differential Voltage
and Differential Voltage Peak-to-Peak
Definition of Pre-emphasis
FR4
Signal
Source
A
B
C
D.U.T.
SmA
Connector
SmA
Connector
In
Out
30IN
Test Condition Referenced in the Electrical Characteristic Table
xO+
xI+
EQ
xO-
xIx_EM
Recommended coupling
capacitors are 4.7nF
MODE
Emphasis Setting for PCB Trace or Cable
Output
T/S/T 4/8/4 mil
FR4 PCB trace
Output
AWG 28 SATA
Cable
R3
< 6 inch
< 36 inch
0
> 6 inch
> 36 inch
open
R3
Standard Mode Implementation Diagram
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PS9072A
03/23/10
PI3EQX4951ST
3.3V, 1-Port, SATA2 i/m ReDriver™with Analog/Digital Configuration
VDD
Equalization Setting for PCB Trace or Cable
J1
MODE
x_EQ
Output
T/S/T 4/8/4 mil
FR4 PCB trace
Output
AWG 28 SATA
Cable
J1
< 6 inch
< 36 inch
0
> 6 inch
> 36 inch
open
xO+
EQ
REM Suggested Inital Test Values for PCB Trace or Cable
xOx_EM
Recommended coupling
capacitors are 4.7nF
REM
1.0K<REM<15K
REM sets output
emphasis level
(See table)
Output
T/S/T 4/8/4 mil
FR4 PCB trace
Output
AWG 28 SATA
Cable
Pre-emphasis
dB
REM
< 3 inch
< 18 inch
0
33k
4 inch
30 inch
1.5dB
10k
6 inch
30 inch
2.0dB
7.2k
8 inch
40 inch
2.5dB
6.2k
12 inch
60 inch
3.5dB
3.3k
16 inch
48 inch
4.5dB
2.2k
24 inch
48 inch
6.0dB
1.1k
Enhanced Mode Implementation Diagram
NC
NC
Notes:
1. Control pins are with internal 150k pull up R.
2. The R6, R10, R11 are use in standard mode.
Application Schematic
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PS9072A
03/23/10
PI3EQX4951ST
3.3V, 1-Port, SATA2 i/m ReDriver™with Analog/Digital Configuration
Packaging Mechanical: 20-contact TQFN (ZD)
1
DATE: 09/11/08
DESCRIPTION: 20-Lead, Thin Fine Pitch Quad Flat No-Lead (TQFN)
PACKAGE CODE:
ZD20
REVISION: --
DOCUMENT CONTROL #: PD-2084
08-0456
For latest package info, please check: http://www.pericom.com/products/packaging/mechanicals.php
Ordering Information
Ordering Number
Package Code
Package Description
PI3EQX4951STZDE
ZD
Pb-Free and Green 20-contact TQFN (4x4mm)
• Thermal characteristics can be found on the company web site at www.pericom.com/packaging/
• E = Pb-free and Green
• X suffix = Tape/Reel
Pericom Semiconductor Corporation • 1-800-435-2336 • www.pericom.com
10-0142
All trademarks are property of their respective owners.
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PS9072A
03/23/10