PI2EQX4432D 2.5 Gbps x2 Lane PCI Express Repeater/Equalizer with Signal Detect and Flow-Through Pinout Description Features • Two High Speed PCI Express lanes • Supports PCI Express data rates (2.5 Gbps) on each lane • Adjustable Receiver Equalization • Input Signal Level Detect & Output Squelch on all Channels • Output De-emphasis = -3.5dB • 100–Ohm Differential CML I/O’s • Low Power (100mW per Channel) • Standby Mode – Power Down State • VDD Operating Range: 1.8V +/-0.1V • Packaging (Pb-free & Green): 48-contact TQFN Pericom Semiconductor’s PI2EQX4432D is a low power, PCI Express compliant signal Re-Driver. The device provides programmable equalization, to optimize performance by reducing Inter-Symbol Interference (ISI). PI2EQX4432D supports two 100−Ohm Differential CML data I/O’s between the Protocol ASIC to a switch fabric, across a backplane, or extends the signals across other distant data pathways on the user’s platform. The integrated equalization circuitry provides flexibility with signal integrity of the PCI Express signal before the Re-Driver. Whereas the integrated de-emphasis circuitry provides flexibility with signal integrity of the PCI Express signal after the ReDriver. A low-level input signal detection and output squelch function is provided for all four channels. Each channel operates fully independantly. When a channel is enabled (EN_x=1) and operating, that channels input signal level (on xl+/-) determines whether the output is enabled. If the input level of the channel falls below the active threshold level (Vth-) then the output driver switches off, and the pin is pulled to VDD via a high impedance resistor. In addition to providing serial re-conditioning, Pericom's PIEQX4432D also provides a power management Stand-by mode operated by the enable pins. Block Diagram Pin Description (Top View) VDD SEL–EQ_A SEL–EQ_B SEL–OL_A SEL–OL_B SEL–DE_A SEL–DE_B EN_A EN_B EN_C EN_D VDD Signal Detect CML xO+ xl+ Equalizer Limiting Amp AI+ AI– VDD BO+ BO– VDD CI+ CI– VDD xO– xl– SEL–EQ_x SEL–OL_x SEL–DE_x Power Management EN_X DO+ DO– VDD 48 47 46 45 4443 42 41 40 39 38 37 36 1 35 2 34 3 33 4 32 5 31 6 GND 30 7 29 8 28 9 27 10 26 11 25 12 13 14 15 16 1718 19 20 21 22 23 24 AO+ AO– VDD BI+ BI– VDD CO+ CO– VDD DI+ DI– GND CLK+ CLK– CLKO+ Clock Buffer EN_CLK 07-0106 EN_CLK CLK+ CLK– SEL–EQ_C SEL–EQ_D SEL–OL_C SEL–OL_D SEL–DE_C SEL–DE_D CLKO+ CLKO– IREF – – Repeat 4 Times – – CLKO– IREF 1 PS8888A 04/26/07 PI2EQX4432D 2.5Gbps x2 Lane PCI Express Repeater / Equalizer with Signal Detect and Flow-through Pinout Pin Description Pin # Pin Name I/O 1 AI+ I 2 AI- I 36 AO+ O 35 AO- O 33 BI+ 32 BI- I 4 BO+ O 5 BO- O 7 CI+ I 8 CI- I 30 CO+ O 29 CO- O 27 DI+ I 26 DI- I 10 DO+ O 11 DO- O 41, 40, 39, 38 43, 42, 20, 21 47, 46, 16, 17 45, 44, 18, 19 14, 15 22, 23 13 07-0106 EN_[A, B, C, D] SEL–DE_ [A:D] SEL–EQ_ [A:D] SEL–OL_ [A:D] CLK+, CLK– CLKO, CLKO– EN_CLK I I I I Description Positive CML Input Channel A with internal 50 Ohm pull down during normal operation (EN_A = 1). When EN_A = 0, this pin is a high-impedance. Negative CML Input Channel A with internal 50 Ohm pull down during normal operation (EN_A = 1). When EN_A =0, this pin is a high-impedance. Positive CML Output Channel A internal 50 Ohm pull up during normal operation and 2KΩ pull up otherwise. Negative CML Output Channel A with internal 50 Ohm pull up during normal operation and 2K-ohm pull up otherwise. Posite CML Input Channel B with internal 50 Ohm pull down during normal operation (EN_B = 1). When EN_B = 0, this pin is a high-impedance. Negative CML Input Channel B with internal 50 Ohm pull down during normal operation (EN_B = 1). When EN_B = 0, this pin is a high-impedance. Positive CML Output Channel B with internal 50 Ohm pull up during normal operation and 2k–Ohm pull up otherwise. Negative CMLOutput Channel B with internal 50 Ohm pull up during normal operation and 2k–Ohm pull up otherwise. Positive CML Input Channel C with internal 50 Ohm pull down during normal operation (EN_C = 1). When EN_C = 0, this pin is a high-impedance. Negative CML Input Channel C with internal 50 Ohm pull down during normal operation (EN_C = 1). When EN_C = 0, this pin is a high-impedance. Positive CMLOutput Channel C with internal 50 Ohm pull up during normal operation and 2K-ohm pull up otherwise. Negative CMLOutput Channel C with internal 50 Ohm pull up during normal operation and 2k–Ohm pull up otherwise. Positive CML Input Channel D with internal 50 Ohm pull down during normal operation (EN_D = 1). When EN_D = 0, this pin is a high-impedance. Negative CML Input Channel D with internal 50 Ohm pull down during normal operation (EN_D = 1). When EN_D = 0, this pin is a high-impedance. Positive CML Output Channel D with internal 50 Ohm pull up during normal operation and 2k–Ohm pull up otherwise. Negative CML Output Channel D with internal 50Ω pull up during normal operation and 2k–Ohm pull up otherwise. EN_[A:D] is a channel enable pin with internal 50k–Ohm pull-up resistor. ALVCMOS high provides normal operation. ALVCMOS low selects a low power down mode. Output De–Emphasis configuration input for channels A, B, C and D, with internal 50k–Ohm pull up.Refer to table for modes. Equalizer configuration input for channels A, B, C and D, with internal 50k–Ohm pull-up. Refer to table for modes. Output Level configuration input for channels A, B, C, and D, with internal 50k–Ohm pull–up. Refer to table for modes. I Differential input reference clock, typically 100MHz O Differential reference clock output I Enable Clock input with 50K–Ohm pull-up. When EN_CLK is LVCMOS high level, the clock output operates normally. When EN_CLK = low, the clock outputs are turned off for power savings. A clock is not required bt the data channels for operation. 2 PS8888A 04/26/07 PI2EQX4432D 2.5Gbps x2 Lane PCI Express Repeater / Equalizer with Signal Detect and Flow-through Pinout 24 3, 6, 9, 12, 28, 31, 34, 37, 48 25, Center Pad I VDD PWR 1.8V Supply Voltage GND PWR Supply Ground, Center pad must be connected Output Swing Control SEL–OL_[A:D] 0 1 Connect to 475-Ohm resistor to ground when the reference clock is used. Otherwise do not connect. IREF Output Swing 1x 1.2x Output De-emphasis Adjustment Equalizer Selection SEL−DE_[A:D] 0 1 De-emphasis 0dB –3.5dB SEL−EQ_[A:D] 0 1 Compliance Channel [0:2.5dB] @ 1.25 GHz [0:6.5dB] @ 1.25 GHz Maximum Ratings (Above which useful life may be impaired. For user guidelines, not tested.) Storage Temperature........................................................ –65°C to +150°C Supply Voltage to Ground Potential ................................... –0.5V to +2.5V DC SIG Voltage ..........................................................–0.5V to VDD +0.5V Current Output ................................................................-25mA to +25mA Power Dissipation Continous ......................................................... 800mW Operating Temperature .............................................................. 0 to +70°C Note: Stresses greater than those listed under MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. AC/DC Electrical Characteristics (VDD = 1.8 ±0.1V) Symbol Ps Parameter Supply Power Latency CML Receiver Input RLRX Return Loss Differential Input Peak-toVRX-DIFFP-P peak Voltage AC Peak Common Mode VRX-CM-ACP Input Voltage VTHSignal Detect Threshold DC Differential Input ZRX-DIFF-DC Impedance DC Input Impedance ZRX-DC Conditions All Enables = LVCMOS High All Enables = LVCMOS Low From input to output Min. 50 MHz to 1.25 GHz Typ. Max. 0.1 0.6 Units W 2.0 ns 12 dB 0.175 1.200 V 150 mV 120 175 mV 80 100 120 40 50 60 EN_x = High Ω Equalization JRS Residual Jitter(1,2) JRM Random Jitter(1,2) Total Jitter Deterministic jitter 0.3 0.2 1.5 Ulp-p psrms Notes 1. K28.7 pattern is applied differentially at point A as shown in Figure 1. 2. Total jitter does not include the signal source jitter. Total jitter (TJ) = (14.1 × RJ + DJ) where RJ is random RMS jitter and DJ is maximum deterministic jitter. Signal source is a K28.5 ± pattern (00 1111 1010 11 0000 0101) for the deterministic jitter test and K28.7 (0011111000) or equivalent for random jitter test. Residual jitter is that which remains after equalizing media-induced losses of the environment of Figure 1 or its equivalent. The deterministic jitter at point B must be from media-induced loss, and not from clock source modulation. Jitter is measured at 0V at point C of Figure 1. 07-0106 3 PS8888A 04/26/07 PI2EQX4432D 2.5Gbps x2 Lane PCI Express Repeater / Equalizer with Signal Detect and Flow-through Pinout FR4 Signal Source A B SmA Connector SmA Connector Pericom Re–Driver In C Out ≤ 30IN Figure 1. Test Condition Referenced in the Electrical Characteristic Table AC/DC Electrical Characteristics (TA = 0 to 70˚C) Symbol Parameter Conditions Min. Typ. Max. Units 900 mVp-p 150 ps CML Transmitter Output (100Ω differential) VDIFFP Output Voltage Swing Differential Swing | VTX-D+ - VTX-D- | VTX-C Common-Mode Voltage | VTX-D+ + VTX-D- | / 2 tF, tR Transition Time 20% to 80% (1) ZOUT Output resistance Single ended ZTX-DIFF-DC 400 VDD0.3 40 50 60 Ω DC Differential TX Impedance 80 100 120 Ω CTX AC Coupling Capacitor 75 200 nF VTX-DIFFP-P Differential Peak-to-peak Ouput Voltage 0.8 1.8 V 0.65 × VDD VDD VTX-DIFFP-P = 2 * | VTX-D+ - VTX-D- | LVCMOS Control Pins VIH Input High Voltage VIL Input Low Voltage 0.35 × VDD IIH Input High Current 250 IIL Input Low Current 500 07-0106 4 PS8888A V μA 04/26/07 PI2EQX4432D 2.5Gbps x2 Lane PCI Express Repeater / Equalizer with Signal Detect and Flow-through Pinout AC Switching Characteristics for Clock Buffer (VDD = 1.8 ±0.1V, AVDD = 1.8 ±0.1V) (3) Symbol Trise / Tfall Parameters Rise and Fall Time (measured between 0.175V to 0.525V) (1) Min Max. 125 525 ΔTrise / ΔTfall Rise and Fall Time Variation VHIGH Voltage High including overshoot 660 VLOW Voltage Low including undershoot -200 Absolute crossing point voltages 200 VCROSS ΔVCROSS TDC 75 Total Variation of Vcross over all edges Duty Cycle (input duty cycle = 50%) Units 1 ps 900 550 45 55 1 1 mV 250 (2) Notes 1 1 1 % 2 Notes: 1. Measurement taken from Single Ended waveform. 2. Measurement taken from Differential waveform. 3. Test configuration is RS = 33.2Ω, Rp = 49.9Ω, and 2pF. Configuration Test Load Board Termination Figure 2. Configuration test load board termination Note: • TLA and TLB are 3” transmission lines. 07-0106 5 PS8888A 04/26/07 PI2EQX4432D 2.5Gbps x2 Lane PCI Express Repeater / Equalizer with Signal Detect and Flow-through Pinout ( "$ %&$!& ( ( ( ( "$ %&$!& Packaging Mechanical: 48-contact TQFN (ZD48) ( ( ( !%##!$ ! $ ''!&$ .OTES !LLDIMENSIONSAREINMILLIMETERSANGLESINDEGREES 2EF*%$%#-/6++$ 4HERMAL6IA$IAMETER2ECOMMENDED^MM 4HERMAL6IA0ITCH2ECOMMENDEDMM DATE: 03/10/06 DESCRIPTION: 48-Contact, Thin Fine Pitch Quad Flat No-Lead (TQFN) "ILATERALCOPLANARITYZONEAPPLIESTOTHEEXPOSEDHEATSINKSLUG ASWELLASTHETERMINALS PACKAGE CODE: ZD (ZD48) REVISION: A DOCUMENT CONTROL #: PD-2045 Ordering Information Ordering Number Package Code Package Description PI2EQX4432DZDE ZD Pb-free & Green 48-contact TQFN Notes: • Thermal characteristics can be found on the company web site at www.pericom.com/packaging/ • E = Pb-free & Green • X suffix = Tape/Reel Pericom Semiconductor Corporation • 1-800-435-2336 • www.pericom.com 07-0106 6 PS8888A 04/26/07