White Electronic Designs W3EG7265S-JD3 PRELIMINARY* 512MB – 2x32Mx72 DDR SDRAM REGISTERED, w/PLL FEATURES DESCRIPTION Double-data-rate architecture DDR200 and DDR266 The W3EG7265S is a 2x32Mx72 Double Data Rate SDRAM memory module based on 256Mb DDR SDRAM components. The module consists of eighteen 32Mx8 DDR SDRAMs in 66 pin TSOP package mounted on a 184 Pin FR4 substrate. • JEDEC design specificaitons Bi-directional data strobes (DQS) Differential clock inputs (CK & CK#) Programmable Read Latency 2,2,5 (clock) Programmable Burst Length (2,4,8) Programmable Burst type (sequential & interleave) Edge aligned data output, center aligned data input Auto and self refresh Serial presence detect Dual Rank Power Supply: 2.5V ± 0.2V JEDEC standard 184 pin DIMM package Synchronous design allows precise cycle control with the use of system clock. Data I/O transactions are possible on both edges and Burst Lenths allow the same device to be useful for a variety of high bandwidth, high performance memory system applications. * This product is under development, is not qualified or characterized and is subject to change without notice. • PCB height: 30.48mm (1.20") NOTE: Consult factory for availability of: • RoHS compliant products • Vendor source control options • Industrial temperature option OPERATING FREQUENCIES January 2005 Rev. 3 DDR266 @CL=2 DDR266 @CL=2.5 DDR200 @CL=2 Clock Speed 133MHz 133MHz 100MHz CL-tRCD-tRP 2-2-2 2.5-3-3 2-2-2 1 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs W3EG7265S-JD3 PRELIMINARY PIN CONFIGURATIONS PIN NAMES Pin Symbol Pin Symbol Pin Symbol Pin Symbol 1 VREF 47 DQS8 93 VSS 139 VSS 2 DQ0 48 A0 94 DQ4 140 DQM8 3 VSS 49 CB2 95 DQ5 141 A10 4 DQ1 50 VSS 96 VCC VCC CB6 5 DQS0 51 CB3 97 DQM0 143 VCC 6 DQ2 52 BA1 98 DQ6 144 CB7 7 VCC 53 DQ32 99 DQ7 145 VSS 8 DQ3 54 VCC 100 VSS 146 DQ36 DQ37 9 NC 55 DQ33 101 NC 147 10 RESET# 56 DQS4 102 NC 148 VCC 11 VSS 57 DQ34 103 *A13 149 DQM4 12 DQ8 58 VSS 104 VCC 150 DQ38 13 DQ9 59 BA0 105 DQ12 151 DQ39 14 DQS1 60 DQ35 106 DQ13 152 VSS 15 VCC 61 DQ40 107 DQM1 153 DQ44 16 *CK1 62 VCC 108 VCC 154 RAS# 17 *CK1# 63 WE# 109 DQ14 155 DQ45 18 VSS 64 DQ41 110 DQ15 156 VCC 19 DQ10 65 CAS# 111 CKE1 157 CS0# 20 DQ11 66 VSS 112 VCC 158 CS1# 21 CKE0 67 DQS5 113 *BA2 159 DQM5 22 VCC 68 DQ42 114 DQ20 160 VSS 23 DQ16 69 DQ43 115 A12 161 DQ46 24 DQ17 70 VCC 116 VSS 162 DQ47 25 DQS2 71 *CK2# 117 DQ21 163 CS3# 26 VSS 72 DQ48 118 A11 164 VCC 27 A9 73 DQ49 119 DQM2 165 DQ52 28 DQ18 74 VSS 120 VCC 166 DQ53 29 A7 75 *CK2# 121 DQ22 167 NC 30 VCC 76 *CK2 122 A8 168 VCC 31 DQ19 77 VCC 123 DQ23 169 DQM6 32 A5 78 DQS6 124 VSS 170 DQ54 33 DQ24 79 DQ50 125 A6 171 DQ55 34 VSS 80 DQ51 126 DQ28 172 VCC 35 DQ25 81 VSS 127 DQ29 173 NC 36 DQS3 82 VCCIQ 128 VCC 174 DQ60 DQ61 37 A4 83 DQ56 129 DQM3 175 38 VCC 84 DQ57 130 A3 176 VSS 39 DQ26 85 VCC 131 DQ30 177 DQM7 40 DQ27 86 DQS7 132 VSS 178 DQ62 41 A2 87 DQ58 133 DQ31 179 DQ63 42 VSS 88 DQ59 134 CB4 180 VCC 43 A1 89 VSS 135 CB5 181 SA0 44 CB0 90 NC 136 VCC 182 SA1 45 CB1 91 SDA 137 CK0 183 SA2 46 VCC 92 SCL 138 CK0# 184 VCC SPD January 2005 Rev. 3 2 A0 – A12 BA0-BA1 DQ0-DQ63 CB0-CB7 DQS0-DQS8 CK0 CK0# CKE0, CKE1 CS0#, CS1# RAS# CAS# WE# DQM0-DQM8 VCC VSS VREF VCCSPD SDA SCL SA0-SA2 VCCID NC RESET# VCCID Address input (Multiplexed) Bank Select Address Data Input/Output Check bits Data Strobe Input/Output Clock Input Clock Input Clock Enable Input Chip select Input Row Address Strobe Column Address Strobe Write Enable Data-In Mask Power Supply Ground Power Supply for Reference Serial EEPROM Power Supply Serial data I/O Serial clock Address in EEPROM VCC Identification Flag No Connect Reset Enable VCC Identification Flag * Not Used White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs W3EG7265S-JD3 PRELIMINARY FUNCTIONAL BLOCK DIAGRAM RCS1# RCS0# DQS4 DQM4 DQS0 DQM0 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DM I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2 CS# DQS DM I/O 0 I/O 1 I/O 6 I/O 7 I/O 2 I/O 3 I/O 4 I/O 5 CS# DQS DM I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2 CS# DQS DM I/O 0 I/O 1 I/O 6 I/O 7 I/O 2 I/O 3 I/O 4 I/O 5 CS# DQS DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DM I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2 CS# DQS DM I/O 0 I/O 1 I/O 6 I/O 7 I/O 2 I/O 3 I/O 4 I/O 5 CS# DQS DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DM I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2 CS# DQS DM I/O 0 I/O 1 I/O 6 I/O 7 I/O 2 I/O 3 I/O 4 I/O 5 CS# DQS DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 DM I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2 CS# DQS DM I/O 0 I/O 1 I/O 6 I/O 7 I/O 2 I/O 3 I/O 4 I/O 5 CS# DQS DQS5 DQM5 DQS1 DQM1 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DM I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2 CS# DQS DM I/O 0 I/O 1 I/O 6 I/O 7 I/O 2 I/O 3 I/O 4 I/O 5 CS# DQS DQS6 DQM6 DQS2 DQM2 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DM I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2 CS# DQS DM I/O 0 I/O 1 I/O 6 I/O 7 I/O 2 I/O 3 I/O 4 I/O 5 CS# DQS DQS7 DQM7 DQS3 DQM3 DM I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2 CS# DQS DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DM I/O 0 I/O 1 I/O 6 I/O 7 I/O 2 I/O 3 I/O 4 I/O 5 CS# DQS CB0 CB1 CB2 CB3 CB4 CB5 CB6 CB7 DM I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2 CS# DQS DM I/O 0 I/O 1 I/O 6 I/O 7 I/O 2 I/O 3 I/O 4 I/O 5 CS# DQS DQS8 DQM8 CS0# CS1# BA0, BA1 A0-A12 RAS# CAS# CKE0 CKE1 WE# PCK R E G I S T E R S 120 CK0 CK0# PLL DDR SDRAM DDR SDRAM DDR SDRAM DDR SDRAM DDR SDRAM DDR SDRAM DDR SDRAM DDR SDRAM DDR SDRAM REGISTER X 2 SERIAL PD RCS0# RCS1# SCL WP RBA0-RBA1 BA0-BA1: DDR SDRAMs RA0-RA12 A0-A12: DDR SDRAMs RRAS# RAS#: DDR SDRAMs RCAS# CAS#: DDR SDRAMs RCKE0 CKE: DDR SDRAMs RCKE1 RWE# CKE: DDR SDRAMs WE#: DDR SDRAMs RESET# PCK# SDA A0 A1 A2 SA0 SA1 SA2 VCCSPD SPD VCCQ DDR SDRAMS VCC DDR SDRAMS VREF DDR SDRAMS VSS DDR SDRAMS NOTE: All resistor values are 22 ohms unless otherwise specified. January 2005 Rev. 3 3 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs W3EG7265S-JD3 PRELIMINARY ABSOLUTE MAXIMUM RATINGS Parameter Symbol Value Units Voltage on any pin relative to VSS VIN, VOUT -0.5 - 3.6 V Voltage on VCC supply relative to VSS VCC, VCC -1.0 - 3.6 V °C Storage Temperature TSTG -55 - +150 Power Dissipation PD 18 W Short Circuit Current I0S 50 mA Note: Permanent device damage may occur if ‘ABSOLUTE MAXIMUM RATINGS’ are exceeded. Functional operation should be restricted to recommended operating condition. Exposure to higher than recommended voltage for extended periods of time could affect device reliability DC CHARACTERISTICS 0°C ≤ TA ≤ 70°C, VCC = 2.5V ± 0.2V Parameter Supply Voltage Symbol Min Max Unit VCC 2.3 2.7 V Supply Voltage VCC 2.3 2.7 V Reference Voltage VREF 1.15 1.35 V Termination Voltage VTT 1.15 1.35 V Input High Voltage VIH VREF + 0.15 VCC + 0.3 V Input Low Voltage VIL -0.3 VREF - 0.15 V Output High Voltage VOH VTT + 0.76 — V Output Low Voltage VOL — VTT - 0.76 V Symbol Max Unit CAPACITANCE TA = 25°C, f = 1MHz, VCC = 2.5V ± 0.2V Parameter Input Capacitance (A0-A12) CIN1 6.5 pF Input Capacitance (RAS#, CAS#, WE#) CIN2 6.5 pF Input Capacitance (CKE0) CIN3 6.5 pF Input Capacitance (CK0,CK0#) CIN4 5.5 pF Input Capacitance (CS0#) CIN5 6.5 pF Input Capacitance (DQM0-DQM8) CIN6 13 pF Input Capacitance (BA0-BA1) CIN7 6.5 pF Data input/output capacitance (DQ0-DQ63)(DQS) COUT 13 pF Data input/output capacitance (CB0-CB7) COUT 13 pF January 2005 Rev. 3 4 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs W3EG7265S-JD3 PRELIMINARY IDD SPECIFICATIONS AND TEST CONDITIONS 0°C ≤ TA ≤ 70°C, VCC = 2.5V ± 0.2V, VCC = 2.5V ± 0.2V Includes DDR SDRAM component only Parameter Symbol Conditions DDR266@CL=2.0 Max DDR266@CL=2.5 Max DDR200@CL=2 Max Units Operating Current IDD0 One device bank; Active - Precharge; tRC=tRC (MIN); tCK=tCK (MIN); DQ,DM and DQS inputs changing once per clock cycle; Address and control inputs changing once every two cycles. 2025 1980 1980 mA Operating Current IDD1 One device bank; Active-ReadPrecharge Burst = 2; tRC=tRC (MIN); tCK=tCK (MIN); lOUT = 0mA; Address and control inputs changing once per clock cycle. 2340 2295 2295 mA Precharge PowerDown Standby Current IDD2P All device banks idle; Power-down mode; tCK=tCK (MIN); CKE=(low) 72 72 72 rnA Idle Standby Current IDD2F CS# = High; All device banks idle; tCK=tCK (MIN); CKE = high; Address and other control inputs changing once per clock cycle. VIN = VREF for DQ, DQS and DM. 810 810 810 mA Active Power-Down Standby Current IDD3P One device bank active; Power-Down mode; tCK (MIN); CKE=(low) 450 450 450 mA Active Standby Current IDD3N CS# = High; CKE = High; One device bank; Active-Precharge; tRC=tRAS (MAX); tCK=tCK (MIN); DQ, DM and DQS inputs changing twice per clock cycle; Address and other control inputs changing once per clock cycle. 900 900 900 mA Operating Current IDD4R Burst = 2; Reads; Continuous burst; One device bank active; Address and control inputs changing once per clock cycle; TCK= TCK (MIN); lOUT = 0mA. 2250 2250 2250 mA Operating Current IDD4W Burst = 2; Writes; Continuous burst; One device bank active; Address and control inputs changing once per clock cycle; tCK=tCK (MIN); DQ,DM and DQS inputs changing once per clock cycle. 2115 2115 2115 rnA Auto Refresh Current IDD5 tRC = tRC (MIN) 3015 3015 3015 mA Self Refresh Current IDD6 CKE ≤ 0.2V Operating Current IDD7A Four bank interleaving Reads (BL=4) with auto precharge with tRC=tRC (MIN); tCK=tCK (MIN); Address and control inputs change only during Active Read or Write commands. January 2005 Rev. 3 5 72 72 72 mA 4050 4050 4050 mA White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs W3EG7265S-JD3 PRELIMINARY IDD SPECIFICATIONS AND TEST CONDITIONS 0°C ≤ TA ≤ 70°C, VCC = 2.5V ± 0.2V, VCC = 2.5V ± 0.2V Includes PLL and register power Parameter Symbol Conditions DDR266@CL=2.0 Max DDR266@CL=2.5 Max DDR200@CL=2 Max Units Operating Current IDD0 One device bank; Active - Precharge; tRC=tRC (MIN); tCK=tCK (MIN); DQ,DM and DQS inputs changing once per clock cycle; Address and control inputs changing once every two cycles. 2610 2565 2565 mA Operating Current IDD1 One device bank; Active-ReadPrecharge Burst = 2; tRC=tRC (MIN); tCK=tCK (MIN); lOUT = 0mA; Address and control inputs changing once per clock cycle. 2925 2880 2880 mA Precharge PowerDown Standby Current IDD2P All device banks idle; Power-down mode; tCK=tCK (MIN); CKE=(low) 72 72 72 rnA Idle Standby Current IDD2F CS# = High; All device banks idle; tCK=tCK (MIN); CKE = high; Address and other control inputs changing once per clock cycle. VIN = VREF for DQ, DQS and DM. 1120 1120 1120 mA Active Power-Down Standby Current IDD3P One device bank active; Power-Down mode; tCK (MIN); CKE=(low) 450 450 450 mA Active Standby Current IDD3N CS# = High; CKE = High; One device bank; Active-Precharge; tRC=tRAS (MAX); tCK=tCK (MIN); DQ, DM and DQS inputs changing twice per clock cycle; Address and other control inputs changing once per clock cycle. 1210 1210 1210 mA Operating Current IDD4R Burst = 2; Reads; Continuous burst; One device bank active; Address and control inputs changing once per clock cycle; TCK= TCK (MIN); lOUT = 0mA. 2835 2835 2835 mA Operating Current IDD4W Burst = 2; Writes; Continuous burst; One device bank active; Address and control inputs changing once per clock cycle; tCK=tCK (MIN); DQ,DM and DQS inputs changing once per clock cycle. 2700 2700 2700 rnA Auto Refresh Current IDD5 tRC = tRC (MIN) 3635 3635 3635 mA Self Refresh Current IDD6 CKE ≤ 0.2V 347 347 347 mA Operating Current IDD7A Four bank interleaving Reads (BL=4) with auto precharge with tRC=tRC (MIN); tCK=tCK (MIN); Address and control inputs change only during Active Read or Write commands. 4635 4635 4635 mA January 2005 Rev. 3 6 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs W3EG7265S-JD3 PRELIMINARY DETAILED TEST CONDITIONS FOR DDR SDRAM IDD1 & IDD7A IDD1 : OPERATING CURRENT: ONE BANK IDD7A: OPERATING CURRENT: FOUR BANKS 1. Typical Case: VCC = 2.5V, T = 25°C 2. Worst Case: VCC = 2.7V, T = 10°C 3. Only one bank is accessed with tRC (min), Burst Mode, Address and Control inputs on NOP edge are changing once per clock cycle. lOUT = 0mA 4. Timing patterns • DDR200 (100MHz, CL = 2) : tCK = 10ns, CL2, BL = 4, tRCD = 2*tCK, tRAg = 5*tCK Read: A0 N R0 N N P0 N A0 N - repeat the same timing with random address changing; 50% of data changing at every burst • DDR266 (133MHz, CL = 2.5) : tCK = 7.5ns, CL = 2.5, BL = 4, tRCD = 3*tCK, tRC = 9*tCK, tRAg = 5*tCK Read: A0 N N R0 N P0 N N N A0 N - repeat the same timing with random address changing; 50% of data changing at every burst • DDR266 (133MHz, CL = 2) : tCK = 7.5ns, CL = 2, BL = 4, tRCD = 3*tCK, tRC = 9*tCK, tRAg = 5*tCK Read: A0 N N R0 N P0 N N N A0 N - repeat the same timing with random address changing; 50% of data changing at every burst 1. Typical Case: VCC = 2.5V, T = 25°C 2. Worst Case: VCC = 2.7V, T = 10°C 3. Four banks are being interleaved with tRC (min), Burst Mode, Address and Control inputs on NOP edge are not changing. lout = 0mA 4. Timing patterns • DDR200 (100MHz, CL = 2) : tCK = 10ns, CL2, BL = 4, tRRD = 2*tCK, tRCD = 3*tCK, Read with autoprecharge Read: A0 N A1 R0 A2 R1 A3 R2 A0 R3 A1 R0 - repeat the same timing with random address changing; 100% of data changing at every burst • DDR266 (133MHz, CL = 2.5) : tCK = 7.5ns, CL = 2.5, BL = 4, tRRD = 3*tCK, tRCD = 3*tCK Read with autoprecharge Read: A0 N A1 R0 A2 R1 A3 R2 N R3 A0 N A1 R0 - repeat the same timing with random address changing; 100% of data changing at every burst • DDR266 (133MHz, CL = 2): tCK = 7.5ns, CL2 = 2, BL = 4, tRRD = 2*tCK, tRCD = 3*tCK Read: A0 N A1 R0 A2 R1 A3 R2 N R3 A0 N A1 R0 - repeat the same timing with random address changing; 100% of data changing at every burst Legend: A = Activate, R = Read, W = Write, P = Precharge, N = NOP A (0-3) = Activate Bank 0-3 R (0-3) = Read Bank 0-3 January 2005 Rev. 3 7 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs W3EG7265S-JD3 PRELIMINARY DDR SDRAM COMPONENT ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS AC Characteristics 262 Parameter 265/202 Symbol Min Max Min Max Units Access window of DQs from CK, CK# tAC -0.75 +0.75 -0.75 +0.75 ns CK high-level width tCH 0.45 0.55 0.45 0.55 tCK CK low-level width tCL 0.45 0.55 0.45 0.55 tCK 16 CL=2.5 tCK (2.5) 7.5 13 7.5 13 ns 22 CL=2 tCK (2) 7.5/10 13 10 13 ns 22 tDH 0.5 ns 14,17 Clock cycle time DQ and DM input hold time relative to DQS 0.5 Notes 16 DQ and DM input setup time relative to DQS tDS 0.5 0.5 ns 14,17 DQ and DM input pulse width (for each input) tDIPW 1.75 1.75 ns 17 Access window of DQS from CK, CK# tDQSCK -0.75 DQS input high pulse width tDQSH 0.35 DQS input low pulse width tDQSL 0.35 DQS-DQ skew, DQS to last DQ valid, per group, per access tDQSQ +0.75 -0.75 +0.75 0.35 ns tCK 0.35 tCK 0.5 0.5 ns 1.25 tCK Write command to first DQS latching transition tDQSS 0.75 DQS falling edge to CK rising - setup time tDSS 0.2 0.2 tCK DQS falling edge from CK rising - hold time tDSH 0.2 0.2 tCK Half clock period tHP Data-out high-impedance window from CK, CK# tHZ 1.25 0.75 tCH, tCL tCH, tCL +0.75 +0.75 13,14 ns 18 ns 8,19 Data-out low-impedance window from CK, CK# tLZ -0.75 -0.75 ns 8,20 Address and control input hold time (fast slew rate) tIHf 0.90 0.90 ns 6 Address and control input set-up time (fast slew rate) tISf 0.90 0.90 ns 6 Address and control input hold time (slow slew rate) tIHs 1 1 ns 6 6 Address and control input setup time (slow slew rate) tISs 1 1 ns Address and control input pulse width (for each input) tIPW 2.2 2.2 ns 15 15 ns LOAD MODE REGISTER command cycle time tMRD DQ-DQS hold, DQS to first DQ to go non-valid, per access tQH Data hold skew factor tQHS ACTIVE to PRECHARGE command tRAS 40 ACTIVE to READ with Auto precharge command tRAP 15 20 ns ACTIVE to ACTIVE/AUTO REFRESH command period tRC 60 65 ns AUTO REFRESH command period tRFC 75 75 ns January 2005 Rev. 3 tHP-tQHS tHP-tQHS 0.75 8 120,000 40 ns 0.75 ns 120,000 ns 13,14 15 21 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs W3EG7265S-JD3 PRELIMINARY DDR SDRAM COMPONENT ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS (continued) AC Characteristics Parameter ACTIVE to READ or WRITE delay PRECHARGE command period 262 Symbol Min tRCD 15 265/202 Max Min Max 20 Units tRP 15 DQS read preamble tRPRE 0.9 1.1 0.9 20 1.1 tCK DQS read postamble tRPST 0.4 0.6 0.4 0.6 tCK ns ACTIVE bank a to ACTIVE bank b command tRRD 15 15 ns DQS write preamble tWPRE 0.25 0.25 tCK DQS write preamble setup time tWPRES 0 DQS write postamble tWPST 0.4 Write recovery time tWR 15 15 ns Internal WRITE to READ command delay tWTR 1 1 tCK Data valid output window NA REFRESH to REFRESH command interval tREFC 0 0.6 0.4 tQH-tDQSQ 0.6 tQH-tDQSQ 70.3 ns 10,11 9 ns 13 70.3 μs 12 7.8 μs 12 Average periodic refresh interval tREFI tVTD 0 0 ns Exit SELF REFRESH to non-READ command tXSNR 75 75 ns Exit SELF REFRESH to READ command tXSRD 200 200 tCK January 2005 Rev. 3 9 19 tCK Terminating voltage delay to VCC 7.8 Notes ns White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs W3EG7265S-JD3 PRELIMINARY Notes 1. All voltages referenced to VSS 2. Tests for AC timing, IDD, and electrical AC and DC characteristics may be conducted at normal reference / supply voltage levels, but the related specifications and device operations are guaranteed for the full voltage range specified. 3. Outputs are measured with equivalent load: 11. It is recommended that DQS be valid (HIGH or LOW) on or before the WRITE command. The case shown (DQS going from High-Z to logic LOW) applies when no WRITEs were previously in progress on the bus. If a previous WRITE was in progress, DQS could be high during this time, depending on tDQSS. 12. The refresh period is 64ms. This equates to an average refresh rate of 15.625µs or 7.8125µs. However, an AUTO REFRESH command must be asserted at least once every 140.6µs or 70.3µs; burst refreshing or posting by the DRAM controller greater than eight refresh cycles is not allowed. 13. The valid data window is derived by achieving other specifications - tHP (tCK/2), tDQSQ, and tQH (tQH = tHP - tQHS). The data valid window derates directly proportional with the clock duty cycle and a practical data valid window can be derived. The clock is allowed a maximum duty cycled variation of 45/55. Functionality is uncertain when operating beyond a 45/55 ratio. The data valid window derating curves are provided below for duty cycles ranging between 50/50 and 45/55. 14. Referenced to each output group: x8 = DQS with DQ0-DQ7. 15. READs and WRITEs with auto precharge are not allowed to be issued until tRAS (MIN) can be satisfied prior to the internal precharge command being issued. 16. JEDEC specifies CK and CK# input slew rate must be > 1V/ns (2V/ns differentially). 17. DQ and DM input slew rates must not deviate from DQS by more than 10%. If the DQ/DM/DQS slew rate is less than 0.5V/ns, timing must be derated: 50ps must be added to tDS and tDH for each 100mV/ns reduction in slew rate. If slew rates exceeds 4V/ns, functionality is uncertain. 18. tHP min is the lesser of tCL min and tCH min actually applied to the device CK and CK# inputs, collectively during bank active. 19. This maximum value is derived from the referenced test load. In practice, the values obtained in a typical terminated design may reflect up to 310ps less for tHZ (MAX) and last DVW. tHZ (MAX) will prevail over the tDQSCK (MAX) + tRPST (MAX) condition. tLZ (MIN) will prevail over tDQSCK (MIN) + PRE (MAX) condition. 20. For slew rates greater than 1V/ns the (LZ) transition will start about 310ps earlier. 21. CKE must be active (High) during the entire time a refresh command is executed. That is, from the time the AUTO REFRESH command is registered, CKE must be active at each rising clock edge, until tREF later. 22. Whenever the operating frequency is altered, not including jitter, the DLL is required to be reset. This is followed by 200 clock cycles (before READ commands). VTT Output (VOUT) 4. 5. 6. 50Ω Reference Point 30pF AC timing and IDD tests may use a VIL-to-VIH swing of up to 1.5V in the test environment, but input timing is still referenced to VREF (or to the crossing point for CK/CK#), and parameter specifications are guaranteed for the specified AC input levels under normal use conditions. The minimum slew rate for the input signals used to test the device is 1V/ns in the range between VIL(AC) and VIH(AC). The AC and DC input level specifications are defined in the SSTL_ 2 standard (i.e., the receiver will effectively switch as a result of the signal crossing the AC input level, and will remain in that state as long as the signal does not ring back above [below] the DC input LOW [high] level). Command/Address input slew rate = 0.5V/ns. For -75 with slew rates 1V/ns and faster, tIS and tIH are reduced to 900ps. If the slew rate is less than 0.5V/ns, timing must be derated: tIS has an additional 50ps per each 100mV/ns reduction in slew rate from the 500mV/ns. tIH has 0ps added, that is, it remains constant. If the slew rate exceeds 4.5V/ns, functionality is uncertain. 7. Inputs are not recognized as valid until VREF stabilizes. Exception: during the period before VREF stabilizes, CKE ≤ 0.3 x VCC is recognized as LOW. 8. tHZ and tLZ transitions occur in the same access time windows as valid data transitions. These parameters are not referenced to a specific voltage level, but specify when the device output is no longer driving (HZ) and begins driving (LZ). 9. The maximum limit for this parameter is not a device limit. The device will operate with a greater value for this parameter, but system performance (bus turnaround) will degrade accordingly. 10. This is not a device limit. The device will operate with a negative value, but system performance could be degraded due to bus turnaround. January 2005 Rev. 3 10 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs W3EG7265S-JD3 PRELIMINARY ORDERING INFORMATION FOR JD3 Part Number Speed CAS Latency tRCD tRP Height* W3EG7265S262JD3 133MHz/266Mb/s 2 2 2 30.48 (1.20") W3EG7265S265JD3 133MHz/266Mb/s 2.5 3 3 30.48 (1.20") W3EG7265S202JD3 100MHz/200Mb/s 2 2 2 30.48 (1.20") NOTE: • Consult Factory for availability of RoHS compliant products. (G = RoHS Compliant) • Vendor specific part numbers are used to provide memory components source control. The place holder for this is shown as lower case “x” in the part numbers above and is to be replaced with the respective vendors code. Consult factory for qualified sourcing options. (M = Micron, S = Samsung & consult factory for others) • Consult factory for availability of industrial temperature (-40°C to 85°C) option PACKAGE DIMENSIONS FOR JD3 133.48 (5.255" MAX.) 131.34 (5.171") 128.95 (5.077") 4.06 (0.160 MAX) 3.99 (0.157 (2x)) 30.48 (1.20 MAX) 17.78 (0.700) 10.01 (0.394) 6.35 (0.250) 64.77 (2.550) 6.35 (0.250) 49.53 (1.950) 1.27 (0.050 TYP.) 1.78 (0.070) 3.99 (0.157) (MIN) 2.31 (0.091) (2x) 3.00 (0.118) (4x) 1.27 ± 0.10 (0.050 ± 0.004) * ALL DIMENSIONS ARE IN MILLIMETERS AND (INCHES). January 2005 Rev. 3 11 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs W3EG7265S-JD3 PRELIMINARY Document Title 512MB – 2x32Mx72 DDR SDRAM REGISTERED, w/PLL Revision History Rev # History Release Date Status Rev 0 Created Datasheet 5-22-02 Advanced 1.1 Updated CAP & IDD Specs. 6-04 Preliminary 2.1 Added AC Specs 11-04 Preliminary 3.1 Added lead-free and RoHS notes 1-05 Preliminary Rev 1 1.2 Changed package option to JEDEC "JD3" 1.3 Moved from Advanced to Preliminary Rev 2 Rev 3 3.2 Provided source control availability 3.3 Added industrial temperature options January 2005 Rev. 3 12 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com